五、發明説明（丨’） ㈠技術領域 經濟部中央橾準局員工消费合作杜印製 本發明是關於積體電路之薄膜界面剝離的消弭方法.，特 別是關於P通道金氧半場效電晶體之複晶矽閘極和介電層之 間之界面剝離的消弭方法。 (二)發明背景 P通道金氧半場效電晶體積體電路之製造方法是先在矽 半導體基板上形成場氧化層，然後再形成P通道金氧半場效 電晶體（PMOSFET)，而所述P通道金氧半場效電晶體包含 有鬧氧化層、複晶砂閘極與源極/汲極。而在製造金氧半場 效電晶體過程裡，會使用到離子佈植技術來形成P-淡攙雜 區域和P+濃讎源極/汲極，而通常是使用bf2離子。 使用bf2離子形成P-淡攙雜區域和P+濃攙雜源極/ 汲極時，BF2離子會進入複晶矽閘極，使氟元素累積在複晶 矽閘極，然後在後續的高溫製程被釋放出來，造成薄膜之間 發生界面剝離現象（Delamination) ^例如，後續在高溫環 境沉積中間介電層時（Inter Level Dielectri ; ILD)，累 積在複晶矽閘極的氟元素將被釋放出來（Outgassing)，造 成複晶矽閘極跟中間介電層之間發生界面剝離現象 (Delamination) ° 傳統方法是在形成『中間介電層』之前增加一個逸氣步 驟（Degas)將累積在複晶矽閘極的氟元素驅出，然後再形成 『中間介電層』，但『逸氣步驟』增加了製造成本。 本發明之方法在不需額外的光罩和不需『逸氣步驟』的 情況下，可以消弭了複晶矽閘極跟介電層之間的界面剝離’ 降低製造成本，提高積體電路可靠度。 ..--^-----{------II------¾ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印装 A 7 B7 五、發明説明（>) (三) 發明的簡要說明 本發明的主要目的是提供一種積體電路之薄膜界面剝離 的消弭方法。 本發明的另一個目的是提供一種P通道金氧半場效電晶 體之複晶矽閘極跟介電層之間之界面剝離的消弭方法。 首先，在矽半導體基板上形成場氧化層，然後形成閘氧 化層和P通道複晶矽閘極。接著，以光罩作爲離子佈植保護 罩，進行bf2離子佈植以形成P-淡攙雜區域，所述光罩之 設計雖得光阻遮住p遲複晶矽閘極和P井區。 接著，在所述P通道複晶矽閘極之二側產生介電層側壁 物（Spacer )。再以所述光罩作爲離子佈植保護罩，進行 BF2離子佈植以形成P+濃攙雜源極/汲極，所述光罩跟形 成P—淡攙雜區域之光罩相同，也是使得光阻遮住P通道複 晶矽閘極和P井區。 於 最後，形成一層中間介電層（Inter Level Dielecti^i^ ILD)、接觸窗與金屬連線，完成P通道金氧半場效電晶 積體電路的製造。 (四) 圖示的簡要說明 圖一到圖八是本發明之實施例的製程剖面示意圖。 (五) 發明的詳細說明 以下以形成P通道金氧半場效電晶體積體電路爲實施 例，說明本發明之方法，但本發明之方法可堆廣應用到其它 的積體電路。 現在參考圖一和圖二。首先，以傳統局部矽氧化技術 (LOCOS)在政半導體基板 10 上（Silicon Semiconductor (請先閲讀背面之注意事項再填寫本頁) -•St r 本紙張尺度適用中國國家#準（CNS ) A4規格（210X297公釐） ，經濟部中央揉準局負工消费合作社印蓑 A7 _B7___ 五、發明説明（邑）V. Description of the invention (丨 ') (i) Technical area The Ministry of Economic Affairs, Central Bureau of Industry and Commerce, consumer cooperation, du printing. The present invention is about the elimination method of the thin film interface peeling of integrated circuits. In particular, it relates to the P-channel metal oxide half field effect transistor The elimination method of the peeling of the interface between the polycrystalline silicon gate and the dielectric layer. (2) Background of the invention The manufacturing method of the P-channel metal oxide half field effect transistor bulk circuit is to form a field oxide layer on a silicon semiconductor substrate first, and then form the P channel metal oxide half field effect transistor (PMOSFET), and the P The channel gold-oxygen half-field effect transistor includes an oxide layer, a polycrystalline sand gate, and a source / drain. In the process of manufacturing gold-oxygen half field effect transistors, ion implantation technology is used to form the P-light doped region and the P + concentrated source / drain, and usually bf2 ions are used. When bf2 ions are used to form a P-light doped region and a P + concentrated doped source / drain, BF2 ions will enter the polycrystalline silicon gate, causing fluorine to accumulate in the polycrystalline silicon gate, and then be released in the subsequent high temperature process , Causing interfacial peeling between the films (Delamination) ^ For example, when the intermediate dielectric layer is deposited in a high-temperature environment (Inter Level Dielectri; ILD), the fluorine element accumulated in the polycrystalline silicon gate will be released (Outgassing) , Causing interface peeling between the polycrystalline silicon gate electrode and the intermediate dielectric layer (Delamination) ° The traditional method is to add a degassing step (Degas) before the formation of the “intermediate dielectric layer” will accumulate in the polycrystalline silicon gate electrode The fluorine element is driven out, and then the "intermediate dielectric layer" is formed, but the "escape step" increases the manufacturing cost. The method of the present invention eliminates the interface peeling between the polycrystalline silicon gate and the dielectric layer without the need for an additional photomask and the "escape step" to reduce the manufacturing cost and improve the reliability of the integrated circuit degree. ..-- ^ ----- {------ II ------ ¾ (Please read the precautions on the back before filling out this page) This paper size is suitable for China National Standard (CNS) A4 Specifications (210X297 mm) Printed by the Consumers ’Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A 7 B7 V. Description of the invention (>) (3) Brief description of the invention The main purpose of the invention is to provide a thin film interface peeling of integrated circuits Elimination method. Another object of the present invention is to provide a method for eliminating the peeling of the interface between the polycrystalline silicon gate of the P-channel metal-oxide half field effect transistor and the dielectric layer. First, a field oxide layer is formed on the silicon semiconductor substrate, and then a gate oxide layer and a P-channel polycrystalline silicon gate are formed. Next, a photomask is used as an ion implantation protection mask, and bf2 ion implantation is performed to form a P-light doped region. The design of the photomask is such that the photoresist shields the p-type complex silicon gate and the P-well region. Next, a dielectric layer sidewall (Spacer) is generated on both sides of the P-channel polycrystalline silicon gate. Then use the photomask as an ion implantation protection mask to perform BF2 ion implantation to form a P + concentrated impurity source / drain. The photomask is the same as the photomask that forms the P-light impurity region, which also makes the light blocking Live P channel polycrystalline silicon gate and P well area. At the end, an intermediate dielectric layer (Inter Level Dielecti ^ i ^ ILD), contact window and metal connection are formed to complete the manufacturing of the P-channel MOSFET half-effect transistor circuit. (4) Brief description of the drawings Figures 1 to 8 are schematic cross-sectional views of the manufacturing process according to an embodiment of the present invention. (5) Detailed description of the invention The following takes the formation of a P-channel metal oxide half field effect transistor volume circuit as an example to describe the method of the present invention, but the method of the present invention can be widely applied to other integrated circuits. Reference is now made to Figures 1 and 2. First, the traditional local silicon oxide technology (LOCOS) is used on the political semiconductor substrate 10 (Silicon Semiconductor (please read the precautions on the back before filling in this page)-• St r This paper standard is applicable to China National Standard #CN (CNS) A4 (210X297mm), the Ministry of Economic Affairs, Central Bureau of Accreditation, the Unemployment Consumer Cooperative, A7 _B7___ V. Description of Invention (Yi)
Substrate)形成隔離P通道金氧半場效電晶體所需的場氧 化層12 (Field Oxide)，其厚度介於3000到6000埃之 間，如圖一所示。接著，形成所述P通道金氧半場效電晶體 閛氧化層14，所述閘氧化層14是在含氧氣的高溫環境中熱 氧化所述『N型矽半導體晶圓10』之表面之矽原子而形成， 其氧化溫度介於850到950 °C之間，其厚度介於50到 200埃之間，如圖二所示》 現在參考圖三。接著，形成一層複晶矽16，並利用微影 技術與電漿蝕刻技術飩去所述複晶矽16以形成P通道複晶 矽閛極16，如圖三所示。所述『複晶矽16』再利用磷原子 之撞雜技術形成，其反應原理是低壓化學氣相沉積法，反應 氣體是PH3、SiH4與N2的混合氣體，反應溫度介於520到 580 °C之間，其厚度介於2000到4000埃之間。 對所述複晶矽16之電漿蝕刻，可以利用磁場增強式活 性離子式電漿蝕刻技術（MERIE)或電子迴旋共振電漿蝕刻技 術（ECR)，抑或是傳統的活性離子式電漿蝕刻技術 (RIE)。通常，在次微米積體電路領域或深次微米積體電路 領域，一般是利用磁場增強式活性離子式電漿蝕刻技術來蝕 刻所述複晶矽16，其電漿反應氣體是HBr等氣體。 現在參考圖四、圖五和圓六。接著，以光罩 (Photomask)作爲離子佈植保護罩，進行BF2離子佈植21 以形成P-淡攙雜區域22，所述光罩之設計是使得光阻20 遮住P通道複晶矽閘極16，如圖四所示，去除所述光阻20 後，如圖五所示。接著，沉積一層介電層24，並對所述介電 層24進行單向性的回蝕刻，以在所述P通道複晶矽閘極 本纸張尺度逋用中面«家揉準（CNS > A4规格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 五、發明説明（t) 16之二側產生介電層側壁物24，如圖六所示。所述介電層 24通常是利用低壓化學氣相沉積法形成之無摻雜的二氧化 矽，其反應氣體是四已基矽酸鹽（TetraEthOxySilane ; TE0S)，反應溫度約720 °C，反應壓力介於0.2到0.4 torr之間，其厚度介於1500到2500埃之間。 現在參考圖七和圖八。接著，以所述光罩作爲離子佈植 保護罩，進行BF2離子佈植25以形成p+濃攙雜源極/汲 極26，所述光罩跟形成所述P-淡攙雜區域22之光罩相 同，也是使得光阻28遮住所述P通道複晶矽閛極16，如 圖七所示，去除所述光阻28後，如圖八所示。 、 最後，形成一層中間介電層（Inter Level Dielectri^、 ILD)、接觸窗與金屬連線，完成P通道金氧半場效電晶體/ 積體電路的製造。所述中間介電層通常是以低壓化學氣相沉 積法形成之二氧化矽，未來，所述金屬連線將透過接觸窗跟 所述P通道金氧半場效電晶體之源極/汲極區域作電性接 觸。 由於進行BF2離子佈植時，本發明用同一個光罩形成光 經濟部t央橾準局貝工消費合作杜印*. (請先閲讀背面之注意事項再填寫本頁) 阻20和光阻28，以遮住所述P通道複晶矽閘極16，使 所述P通道複晶矽閘極16免於受到BF2離子的侵襲，避 免氟元素累積在所述P通道複晶矽閘極16，因此消弭了所 述P通道複晶矽閘極16跟所述中間介電層之間的界面剝 離，降低製造成本，提高積體電路的可靠度。 上述係以最佳實施例來闌述本發明，而非限制本發明， 並且，熟知半導體技藝之人士皆能明瞭，適當而作些微的改 變及調整，仍將不失本發明之要義所在，亦不脫離本發明之 本紙»•尺度逋用+··家標準（CNS》A4规格（210X297公釐） A7 B7 五、發明説明（匕）精神和範圍。 (請先閲讀背面之注意事項再填寫本頁)Substrate) to form the field oxide layer 12 (Field Oxide) required to isolate the P-channel metal-oxide half-field effect transistor. Its thickness is between 3000 and 6000 Angstroms, as shown in Figure 1. Next, the P channel metal oxide half field effect transistor oxide layer 14 is formed. The gate oxide layer 14 thermally oxidizes silicon atoms on the surface of the "N-type silicon semiconductor wafer 10" in a high-temperature environment containing oxygen However, the oxidation temperature is between 850 and 950 ° C, and the thickness is between 50 and 200 Angstroms, as shown in Figure II. Now refer to Figure III. Next, a layer of polycrystalline silicon 16 is formed, and the polycrystalline silicon 16 is removed using photolithography and plasma etching techniques to form a P-channel polycrystalline silicon electrode 16, as shown in FIG. 3. The "polycrystalline silicon 16" is formed by the collision technology of phosphorus atoms. The reaction principle is low-pressure chemical vapor deposition. The reaction gas is a mixed gas of PH3, SiH4 and N2. The reaction temperature is between 520 and 580 ° C. The thickness is between 2000 and 4000 Angstroms. For the plasma etching of the polycrystalline silicon 16, magnetic field enhanced active ion plasma etching technology (MERIE) or electron cyclotron resonance plasma etching technology (ECR), or the traditional active ion plasma etching technology (RIE). Generally, in the field of submicron integrated circuits or deep submicron integrated circuits, the polycrystalline silicon 16 is generally etched using a magnetic field-enhanced active ion plasma etching technique, and the plasma reaction gas is HBr or other gases. Now refer to Figure 4, Figure 5 and Circle 6. Next, a photomask is used as an ion implantation protection mask, and BF2 ion implantation 21 is performed to form a P-light doped region 22. The design of the photomask is such that the photoresist 20 covers the P-channel polycrystalline silicon gate 16. As shown in FIG. 4, after removing the photoresist 20, as shown in FIG. Next, a dielectric layer 24 is deposited, and the dielectric layer 24 is unidirectionally etched back to use the middle surface of the P-channel polycrystalline silicon gate electrode paper > A4 specification (210X297mm) (Please read the precautions on the back before filling in this page) Order V. Description of invention (t) The side wall object 24 of the dielectric layer is produced on both sides of 16 as shown in Figure 6. The dielectric layer 24 is usually undoped silicon dioxide formed by low-pressure chemical vapor deposition. The reaction gas is tetrahexyl silicate (TetraEthOxySilane; TE0S). The reaction temperature is about 720 ° C. The reaction pressure is between The thickness is between 0.2 and 0.4 torr, and the thickness is between 1500 and 2500 Angstroms. Now refer to FIGS. 7 and 8. Next, using the photomask as an ion implantation protection cover, BF2 ion implantation 25 is performed to form a p + concentration Doped source / drain 26, the photomask is the same as the photomask forming the P-light doped region 22, and it also makes the photoresist 28 cover the P-channel polycrystalline silicon semiconductor electrode 16, as shown in FIG. 7 After removing the photoresist 28, as shown in Figure 8. Finally, an intermediate dielectric layer (Inter Level Di electri ^, ILD), contact window and metal connection to complete the manufacture of P-channel metal oxide half field effect transistors / integrated circuits. The intermediate dielectric layer is usually silicon dioxide formed by low-pressure chemical vapor deposition, In the future, the metal connection will be in electrical contact with the source / drain region of the P-channel metal-oxide half-field effect transistor through the contact window. Because of the BF2 ion implantation, the present invention is formed with the same photomask Ministry of Light Economy, Ministry of Economic Affairs, Pyongyang Bureau of Industry and Consumer Cooperation Du Yin *. (Please read the precautions on the back before filling out this page) Resistor 20 and photoresist 28 to cover the P-channel polycrystalline silicon gate 16, so that The P-channel polycrystalline silicon gate 16 is protected from the attack of BF2 ions, preventing fluorine element from accumulating in the P-channel polycrystalline silicon gate 16, thus eliminating the P-channel polycrystalline silicon gate 16 and the The interface between the intermediate dielectric layers is peeled off, which reduces the manufacturing cost and improves the reliability of the integrated circuit. The above is a description of the present invention with the preferred embodiments, rather than limiting the present invention, and anyone familiar with semiconductor technology can Understand that appropriate and slight changes and adjustments are still made Without losing the essence of the present invention, and not deviating from the original paper of the present invention »• Standard Use + ·· Home Standard (CNS) A4 Specification (210X297mm) A7 B7 5. The spirit and scope of the invention description (dagger). (Please (Read the notes on the back before filling this page)
•1T 經濟部中夬標準局負工消費合作杜印褽 本紙張尺度適用中國國家橾準（CNS > A4规格（210X297公釐）• 1T Ministry of Economic Affairs, China National Bureau of Standards, Negative Workers, Consumer Cooperation, Du Yin, the standard paper size is applicable to the Chinese National Standard (CNS > A4 specification (210X297mm)