然而，以所 完成複晶磁接 S10450 五、發明说明（ 發明之技術領域 本發明是關於積體電路之複晶矽接觸結構的形成方法 2·發明背景 金氧半驗電晶體稹體麟（MOSFET 1C)的製造在完成場效電晶體後，接著 是以自動對準的方式形成複晶矽接觸結構。請參考圖一。首先，在矽晶圖2表面形 成隔離金氧半場效電晶體之摄MIL唇j，接著’形成金^半場效電晶體 (MOSFET)。所述金氧半場效養;晶體結檎含有閑氣化層6、閘極8、二氧化矽 10、二氧化矽側壁物14與源極/汲極16。接著，形成一曆複晶矽20，再利用微影 技術形成光阻圆案99 ’然後利技鐵晶矽20以在所述閘極8 上方之所述複晶矽2〇形成垂直的鼸inr’f所述場氧化層之所述複晶矽 20則形成垂直的開口 26。所述垂直的開口 24與垂直的開口 26均切斷所述複晶矽 20，以完成複晶矽接觸。 (所遽难阻喔g99雙婁y利用技術切_所述複晶砂2〇ju 讎 繫差 XMisaiigmnent)，此’在形獅 圖案99時，所述免11|| 99會左右兩邊偏移》又因爲所述涵:晶政20之電漿蝕刻 配方對矽晶圆2的蝕刻選擇率約等於1，於是在蝕去所述複晶矽20時，在所述場 氧化層4和閘極8邊緣附近之矽晶圖2的表面會被蝕刻而形成凹溝，如圖一所 示，在所述場氧化層4邊緣附近形成凹溝88A，在所述閘極8邊緣附近則形成凹 溝 88B。 所述凹溝88A接近所述金氧半場效電晶體之通道，因此會猫斷所述金氧半場效 電晶體之通_流（Channel C_t)。另一方面，所述凹溝88B則相當接近所述 金氧半場效電晶體之源極/汲極16接面，填成幾-p路（Junction Short)。 3.發明之簡要說明 本發明之主要目的是提供一種複晶矽接觸結構的形成方法《 本發明之主要製程方法如下。 首先，在矽晶圓上形成場氧化層，作爲隔離所述*·Ν通道金氣半場效電晶體』 之用，然後，在所述《矽晶圓』表面形成通道金氧半場效電晶體』’所述『Ν 通道金氧半場效電晶體』包含閘氧化層、閘極與源極/汲極。接著，沉積一層複晶矽 層與介電層。接著，利用微影技術形成光阻圈案。然後，利用蝕去所述介電層和一 部份的所述複晶矽層，然後，去除所述光阻圖案，以在所述關極上方之所述複晶矽 形成【垂直的開口】。接著，沉積一層介電赌，並利甩電薄_||摆術對所述企靈歷 進Ρ垂眞里包性敢回触刻，以在所述【垂直的開口】'的侧麓歷座J介電層f壁 。然後」以®述【弄癒遍碰g物1，痄焉醒票，ii面電娥蝕刻技術蝕去辨述【垂 本紙張尺度適用中國國家樣隼（CNS ) A4*i格（2丨OX；297公釐） --------.--1 ;------.訂------i ! ― - (請先閲請背面之注$項再填寫本頁)However, the completed polycrystalline magnetic connection S10450 5. Description of the invention (Technical Field of the Invention The present invention relates to a method for forming a polycrystalline silicon contact structure of an integrated circuit 2. Background of the invention MOSFETS (MOSFET) 1C) After the field effect transistor is completed, the polycrystalline silicon contact structure is then formed by automatic alignment. Please refer to Figure 1. First, the photo of the isolated gold oxide half field effect transistor is formed on the surface of the silicon crystal Figure 2 MIL lip j, then 'formation of gold half field effect transistor (MOSFET). The metal oxide half field effect; the crystal junction contains the idle gasification layer 6, the gate electrode 8, the silicon dioxide 10, the silicon dioxide sidewalls 14 And source / drain 16. Then, a polycrystalline silicon 20 is formed, and then photolithography technology is used to form a photoresist circle 99 ′, and then the ferrocrystalline silicon 20 is used to form the polycrystal above the gate 8 The silicon 20 forms a vertical indium inr'f, and the polycrystalline silicon 20 of the field oxide layer forms a vertical opening 26. Both the vertical opening 24 and the vertical opening 26 cut the polycrystalline silicon 20, In order to complete the contact of the polycrystalline silicon. (It is difficult to resist the g99 double Lou y using technology to cut_The complex crystal沙 2〇ju 雠 系 差 XMisaiigmnent), this' When the lion pattern 99, the free 11 || 99 will be shifted on both sides "because of the culvert: the plasma etching recipe of Jingzheng 20 for silicon wafers The etching selectivity of 2 is approximately equal to 1, so when the polysilicon 20 is etched away, the surface of the silicon crystal near the edges of the field oxide layer 4 and gate 8 will be etched to form a groove, such as As shown in Fig. 1, a concave groove 88A is formed near the edge of the field oxide layer 4, and a concave groove 88B is formed near the edge of the gate electrode 8. The concave groove 88A is close to the channel of the metal oxide semi-field effect transistor, Therefore, the channel C_t of the metal-oxide-half field-effect transistor is interrupted. On the other hand, the groove 88B is quite close to the source / drain 16 junction of the metal-oxide-half field effect transistor. Fill in a few-p paths (Junction Short). 3. Brief description of the invention The main purpose of the present invention is to provide a method for forming a polycrystalline silicon contact structure. The main process of the present invention is as follows. First, on a silicon wafer Forming a field oxide layer to isolate the * · Ν channel gold gas half field effect transistor ", then, The "silicon wafer" surface is formed with a channel metal oxide half field effect transistor "" The "N channel metal oxide half field effect transistor" includes a gate oxide layer, a gate electrode, and a source / drain electrode. Then, a layer of polycrystal is deposited The silicon layer and the dielectric layer. Next, a photoresist ring is formed using lithography. Then, the dielectric layer and a part of the polycrystalline silicon layer are etched away, and then, the photoresist pattern is removed, [Vertical opening] is formed with the polycrystalline silicon above the gate electrode. Then, a layer of dielectric gambling is deposited, and the thin film is thrown away_ || Sex dare to touch back to engrave the wall of the J dielectric layer on the side of the [vertical opening]. Then, it is described by ® [getting to touch g1 all the time, awakening the ticket, ii etched by electric etching technology] [the paper size is applicable to the Chinese National Falcon (CNS) A4 * i grid (2 丨 OX ; 297 mm) --------.-- 1; ------. Subscribe ------ i! ―-(Please read the note $ item on the back and then fill in this page )
B ? B ? M濟部中央搮嗥局員工消#合作.杜印製 五、發明説明（） 直的開口】內剩餘之複晶矽以切斷所述複晶矽。最後，利用緩衝氬氟酸涛液去除所 述【介電層側壁物】，使切斷所述複晶矽的位置呈【上面寬下面窄的梯形開口】。 4·圖示的簡要說明 圖一是複晶矽接觸結構之先前技藝的製程剖面示意圖。 圖二到圖十是本發明之實施例的製程剖面示意圖。 圖二是形成『N通道金氧半場效電晶體』後的製程剖面示意圖； 圖三是沉積一層複晶矽層與介電層後的製程剖面示意圖； 圖四是利用微影技術在所述『N通道金氧半場效電晶體j之閘極上方形成光阻圖案 後的製程剖面示意圖； 圖五是利用電漿蝕刻技術蝕去所述介電層和—部份的所述複晶矽餍後的製程剖面示 意圖； 圖六是去除所述光阻圖案，以在所述閘極上方之所述複晶矽形成垂直的開口後的製 程剖面示意圖； 圖七是沉稹一層介電層後的製程剖面示意圖； 圖八是利用電漿蝕刻技術對所述介電層進行垂直單向性的回錐刻，以在所述【垂直 的開口】的側壁形成【介電層側壁物】後的Μ剖面示意醑； 圖九是以所述【介電層側壁物】作爲護罩，利用電嫌触刻技術蝕去所述【垂直的開 口】內剩餘之複晶矽以切斷所述複晶矽後的製程剖面示意圖； 圖十是利用緩衝氫氟酸溶液（ΒΟΕ)去除所述【介電層側襞物】’使切斷所述複晶 矽的位置呈【上面寬下面窄的梯形開口】後的製程剖面示意圖。 5.發明之實施例 以下以Ν通道金氧半場效電晶讎積體電路（NMOSFET 1C)爲例說明本發明之 實施例，並配合圖二到圖十說明。但本發明之方法亦可堆廣應用到Ν通道金氧半場 效電晶體以外的稹體電路，譬如，Ρ通道金氧半場效電晶體（PMOSFET)與互補式 金氧半場效電晶體（CMOSFET)或雙載子積義電路（BipolarIC)。 參考圖二。首先，在晶格方向（100)之P型矽晶麗2上（Silicon Wafer)形 成場氧化層4，所述『場氧化層4』通常是利用熱氧化技術氧化所述f ?型矽晶圓 2』而成，其厚度介於3000埃到6000埃之間，作爲隔離所述通道金氧半場效 電晶體』之用。然後，在所述『P型砂晶圓2』之表面形成通道金氧半場效電 晶體』，所述『N通道金氧半場效電晶體』包含有閘氧化層6、閘極8、二氧化矽 10、二氧化矽側壁物14與源極/汲極，所述『源極/汲極』含有N·淡摻雜源極 12A/汲極12B和N+濃摻雜源極16A/汲極16B，如圖二:所示。 所述『閘氧化層6』是在含氧氣的高溫環境中熱加氧化所述^ P型矽晶圓2』 表面之矽原子而成，其厚度介於50到200埃之間。所述『購極8』則是利用低壓 化學氣相沉積法（LPCVD)形成之複晶矽8所構成，其厚度介於1000到4000埃 本紙張尺度逍用中國國家橾準（CNS } A4規格{ 210X29?公釐） (請先閲讀背面之注^^項再填寫本頁) 丄 訂 A7 B7 310450 五、發明说明（〉 (請先Μ讀背面之注意事項再镇寫本頁) 之間。接著，利用低壓化學氣相沉稹法形成二氧化矽10以覆蓋住所述複晶矽8。 所述『二氧化矽10』通常是也利用低壓化學氣相沉稹法形成，其反應氣體利用四已 基矽酸鹽（TetraEthOxySilane ; TEOS)，反應溫度大約720 °C，反應壓力介於0.2 到0.4托爾之間，其厚度介於500到1200埃之闇。然後，利用微影技術與蝕刻技 術蝕去所述『二氧化矽1〇』和『複晶矽8』以形成所述『金氧半場效電晶體』之閘 極結構（Gate Structure)。接著，利用離子佈値技術形成源極/汲極』的淡摻 雜源極12A/汲極12B，其離子種類是磷原子（PM )，其離子佈値劑量介於1E13到 3E14原子/平方公分之間，離子佈値能置則介於20到50 kev之間》 再參考圖二。接著，沉積一層『二氧化矽14』，並利用電槳蝕刻技術對所述 『二氧化矽14』進行垂直單向性的回蝕刻（Anisotropic Etchback)，以在所述•閘 極8』之二側形成二氧化较側壁子14。所述「二氧化砂12』通常是利用低壓化學 氣相沉稹法形成，其反應氣體是四已基矽酸鹽（TE0S),反應溫度大約720 eC ,反 應壓力介於0.2到0.4托爾之間，厚度介於1000到2500埃之間。最後，利用離子 佈値技術形成N+濃摻雜源極16A/汲極16B，其離子種類是砷原子（As%)，其離 子佈値劑量介於1E15到5E16原子/平方公分之間，離子佈値能量則介於30到100 kev之間。形成所述『N+濃摻雜源極16A/汲極16B』後，所述N通道金氧半場 效電晶體』的製造於焉完成，如圖二所示。 現在參考圖三。接著，利用低壓化學氣相沉積法沉稹一層複晶矽層20與介電 層22，如圖三所示。所述複晶矽磨20是利用同步磷原子攙雜（In-Situ)之方式形 成，反應溫度介於525到575 °C之間，厚度介於1000到3500埃之間。所述【介電 層22】是利用低壓化學氣相沉積法形成之氮化矽，其反應溫度約760"C，反應氣體 是SiH2Cl2和NH3的混合氣體，貶應壓力約0.35 tort，其摩度介於500到2000 埃之間。 > 〜 現在參考圖四、圖五與圖六。接著，利成斑姐躐案3〇, _四 所示。然後，利用電獎蝕刻技術蝕去所述介電層22 i—部份的所述複晶矽層20， 使成爲介電層22A與複晶矽層20A，如圖五所示，然後，去除所述光阻圈案30， 以在所述閘極8上方之所述複晶矽20形成垂直的開口 35，如圖六所示。 經濟部中央樣準局具工消费合作社印装 對所述【介電層22】與【複晶矽層20】之電漿触刻哥以利用磁場增強式活性 離子式電槳触刻技術（Magnetic Enhanced Reactive Ion Etching ; MERIE )或電子迴旋 共振電獎触刻技術（Electron Cyclotron Resonance ; ECR)或傳統的活性離子式電锻 蝕刻技術（Reactive Ion Etching ; RIE)。在次微米領域，通常是利用【磁場增強式 活性離子式電漿蝕刻技術】，其電鑛反應氣體是六氟化硫和澳化靝氣體。例如，美 國Lam Research公司所製造型號RAINBOW 4400之蝕刻機或美國Applied Materials公司所製造型號PR5000E之蝕刻機都屬於【磁場增強式活性離子式電漿触 刻技術】。 本紙张尺度通用中國困家橾隼（CNS ) Α4洗格（2丨0X297公釐） A7 A7 經濟部中央標準局累工消费合作杜印«. B7 五、發明説明（） 現在參考圖七與圖八。接著’沉積一層介電層40，如圖七所示，並用電漿 蝕刻技術對所述介電層40進行垂直單向性的回蝕刻，以在所述【垂直的開口 35】 的側壁形成【介電層側壁物40A】，如圖八所示。所述介爾層40通常是利用低壓 化學氣相沉積法形成之【無搛雜的二氧化砂】，反應氣體是砂甲烷或四已基矽酸 鹽，反應溫度大約720 °C ’反應室壓力介於(Π到0.4托爾之間，厚度介於！ 000到 2500埃之間。而對所述【介電層40】之垂直單向性的回蝕刻可以利用所述『磁場 增強式活性離子式電漿蝕刻技術』，反應氣髗是四氟化碳、三氟氫化碳與氧氣等氟 族氣體（Fluorine Gas )。 現在參考圖九與圖十。以所述【介電層側壁物40A】作爲護罩，利用電娥蝕刻 技術蝕去所述【垂直的開口 35】內剩餘之複晶矽以切斷所述複晶砂20A ,如圖九所 示。最後’利用緩衝氫氟酸溶液（BOE)去除所述【介電屠側壁物40A】，使切斷 所述複晶矽的位置呈【上面寬下面窄的梯形開口】，如圖十所示。 請特別注意，閘極8寬度是稹懺電路的最小尺寸，而所述梯形開口之下面寬度 可以比所述『Ν通道金氧半場效電晶髗』之剛極8寬度小，也就是說，所述梯形開 口之下面寬度小於微影解析極限，因此，所雄梯形開口之下面寬度提供了一個製程 的緩衝，賞發生光擧數調，所述砂諷的麵猶被触刻 通形成ca溝’因此解法Z—『H·通金氣举場效電晶镫』之通遒電流阻斷和接面短路 的現象，這是本發。 —..................— 以上係以最佳實施例來闊述本發明，而非限制本發明，並且，熟知半導體技藝 之人士皆能明瞭，適當而作些微的改變及調整，仍將不失本發明之要義所在，亦不 脫離本發明之精神和範圍。 本紙張尺度遘用中國國家樣率（CNS ) Α4规格{ 2丨0 X 297公羡> (請先Μ讀背面之注^*項再填寫本頁)B? B? M Ministry of Economic Affairs, Central Government Department of Consumer Affairs # cooperation. Du printed five, invention description () straight opening] remaining polycrystalline silicon to cut off the polycrystalline silicon. Finally, the buffered hydrofluoric acid solution is used to remove the [dielectric layer sidewalls], so that the position for cutting the polycrystalline silicon is [trapezoidal opening with a wide upper side and a lower narrow side]. 4. Brief description of the drawings Figure 1 is a schematic cross-sectional view of the prior art process of the polycrystalline silicon contact structure. Figures 2 to 10 are schematic cross-sectional views of the manufacturing process of an embodiment of the present invention. Figure 2 is a schematic cross-sectional view of the process after the formation of "N-channel gold-oxygen half field effect transistor"; Figure 3 is a cross-sectional schematic view of the process after depositing a polycrystalline silicon layer and a dielectric layer; Figure 4 is the use of lithography technology in the said " A schematic cross-sectional view of the process after forming a photoresist pattern over the gate of the N-channel metal-oxide half-effect transistor j; FIG. 5 is the plasma etching technique used to etch away the dielectric layer and part of the polycrystalline silicon Figure 6 is a schematic cross-sectional view of the process after removing the photoresist pattern to form a vertical opening in the polycrystalline silicon above the gate; Figure 7 is a process after a layer of Shen Zhen dielectric Schematic cross-section; FIG. 8 is a vertical cross-section of the dielectric layer using plasma etching technology to form a vertical unidirectional back-cone to form the [vertical opening] side wall after the [dielectric layer sidewall object] M cross section Schematic diagram; Figure 9 is based on the [dielectric layer sidewall object] as a shield, using electrical contact etching technology to etch the remaining polycrystalline silicon in the [vertical opening] to cut off the polycrystalline silicon Schematic diagram of the manufacturing process profile; Figure 10 is the use of Punching a hydrofluoric acid solution (ΒΟΕ) removing said dielectric layer side folds [] was' the position of cutting said polycrystalline silicon under the form of a narrow width [upper] trapezoidal cross-sectional schematic view of the opening after the process. 5. Embodiments of the invention The following describes an embodiment of the present invention with an N-channel metal-oxide half-field effect transistor integrated circuit (NMOSFET 1C) as an example, and is explained in conjunction with FIGS. 2 to 10. However, the method of the present invention can also be widely applied to N-channel metal oxide half field effect transistors, such as P channel metal oxide half field effect transistors (PMOSFET) and complementary metal oxide half field effect transistors (CMOSFET) Or bipolar IC (BipolarIC). Refer to Figure 2. First, a field oxide layer 4 is formed on the silicon wafer 2 of the p-type silicon crystal 2 in the lattice direction (100). The "field oxide layer 4" usually oxidizes the f-type silicon wafer using thermal oxidation technology. It is formed with a thickness between 3000 angstroms and 6000 angstroms, and is used to isolate the channel metal oxide half field effect transistor. Then, a channel metal oxide half field effect transistor is formed on the surface of the "P-type sand wafer 2", and the "N channel metal oxide half field effect transistor" includes a gate oxide layer 6, a gate electrode 8, and silicon dioxide 10. The silicon dioxide sidewall material 14 and the source / drain, the "source / drain" contains N · lightly doped source 12A / drain 12B and N + concentrated doped source 16A / drain 16B, As shown in Figure 2: The "gate oxide layer 6" is formed by thermally oxidizing silicon atoms on the surface of the P-type silicon wafer 2 in a high-temperature environment containing oxygen, and its thickness is between 50 and 200 angstroms. The "Purchase 8" is made of polycrystalline silicon 8 formed by low-pressure chemical vapor deposition (LPCVD), and its thickness is between 1000 and 4000 Angstroms. The paper standard is easily used by the Chinese National Standard (CNS) A4 {210X29? Mm) (Please read the note ^^ on the back side before filling out this page). Order A7 B7 310450 V. Description of invention (> (please read the precautions on the back side before writing this page). Next, a low-pressure chemical vapor deposition method is used to form silicon dioxide 10 to cover the polycrystalline silicon 8. The "silicon dioxide 10" is also usually formed by a low-pressure chemical vapor deposition method, and its reaction gas is TetraEthOxySilane (TEOS), the reaction temperature is about 720 ° C, the reaction pressure is between 0.2 and 0.4 Torr, and its thickness is between 500 and 1200 Angstroms. Then, using lithography and etching technology The "silicon dioxide 10" and "polycrystalline silicon 8" are etched away to form the gate structure of the "gold oxide half field effect transistor." Then, the source electrode is formed by using the ion distribution technology. Drain electrode's lightly doped source electrode 12A / drain electrode 12B, whose ion type is phosphorus (PM), the ion distribution value is between 1E13 to 3E14 atoms / cm2, and the ion distribution value is between 20 and 50 kev. "Refer to Figure 2. Then, deposit a layer of silicon dioxide 14 ", and the vertical unidirectional etch back (Anisotropic Etchback) of the" silicon dioxide 14 "using the paddle etching technology to form a side wall of the oxide 14 on the two sides of the" gate 8 " The "Sand Dioxide 12" is usually formed by low-pressure chemical vapor deposition, its reaction gas is tetrahexyl silicate (TEOS), the reaction temperature is about 720 eC, and the reaction pressure is between 0.2 and 0.4 Torr The thickness is between 1000 and 2500 Angstroms. Finally, the ion distribution technology is used to form N + concentrated doped source 16A / drain 16B, whose ion type is arsenic atom (As%), and the ion distribution dose is between Between 1E15 and 5E16 atoms / cm2, the ion distribution energy is between 30 and 100 kev. After forming the "N + concentrated doped source 16A / drain 16B", the N-channel metal oxide half field The manufacture of "Effective Transistors" was completed in Yan, as shown in Figure 2. Now refer to Figure 3. Then, A low-pressure chemical vapor deposition method is used to deposit a layer of polycrystalline silicon layer 20 and a dielectric layer 22, as shown in Figure 3. The polycrystalline silicon mill 20 is formed by means of synchronous phosphorus atom doping (In-Situ), and the reaction temperature It is between 525 and 575 ° C, and its thickness is between 1000 and 3500 angstroms. The [dielectric layer 22] is silicon nitride formed by low-pressure chemical vapor deposition, and its reaction temperature is about 760 " C, The reaction gas is a mixed gas of SiH2Cl2 and NH3. The decompression pressure is about 0.35 tort, and its friction is between 500 and 2000 angstroms. > ~ Now refer to Figures 4, 5, and 6. Next, Li Chengban's case is shown in 30, _4. Then, the dielectric layer 22 i- part of the polycrystalline silicon layer 20 is etched away using an electric award etching technique to become the dielectric layer 22A and the polycrystalline silicon layer 20A, as shown in FIG. 5, and then, removed In the photoresist ring case 30, a vertical opening 35 is formed on the polycrystalline silicon 20 above the gate electrode 8, as shown in FIG. The Ministry of Economic Affairs of the Central Bureau of Standards and Apparel Cooperative Consumer Cooperative printed and printed on the plasma of the [dielectric layer 22] and the [polycrystalline silicon layer 20] to utilize the magnetic field enhanced active ion paddle engraving technology (Magnetic Enhanced Reactive Ion Etching (MERIE) or Electron Cyclotron Resonance (ECR) or traditional active ion electroforging etching (Reactive Ion Etching; RIE). In the sub-micron field, [Magnetic Field Enhanced Active Ion Plasma Etching Technology] is commonly used, and the electro-ore reaction gas is sulfur hexafluoride and cerium oxide gas. For example, the etching machine model RAINBOW 4400 manufactured by Lam Research in the United States or the model PR5000E etching machine manufactured by Applied Materials in the United States belong to [Magnetic field-enhanced active ion plasma etching technology]. The size of this paper is universal Chinese sleeper falcon (CNS) Α4 wash grid (2 丨 0X297mm) A7 A7 Central China Bureau of Economic Affairs, Labor and Consumer Cooperation Du Yin «. B7 V. Invention description () Now refer to Figure 7 and Figure Eight. Next, a dielectric layer 40 is deposited, as shown in FIG. 7, and the plasma layer etching technique is used to vertically etch back the dielectric layer 40 to form the sidewall of the [vertical opening 35] [Dielectric layer sidewall object 40A], as shown in FIG. 8. The Til layer 40 is usually formed by low-pressure chemical vapor deposition method [no mixed sand dioxide], the reaction gas is sand methane or tetrahexyl silicate, the reaction temperature is about 720 ° C 'reaction chamber pressure Between (Π to 0.4 Torr, the thickness is between 000 and 2500 Angstroms. And the vertical unidirectional etch back of the [dielectric layer 40] can use the "magnetic field enhanced active ion Type plasma etching technology ”, the reaction gas is fluorocarbon gas (Fluorine Gas) such as carbon tetrafluoride, carbon trifluoride, and oxygen. Now refer to FIG. 9 and FIG. As a shield, the remaining polycrystalline silicon in the [vertical opening 35] is etched off using the E-etching technique to cut off the polycrystalline sand 20A, as shown in FIG. 9. Finally, a buffered hydrofluoric acid solution is used ( BOE) remove the [dielectric side wall 40A], so that the position of cutting the polycrystalline silicon is [trapezoidal opening with a wide upper side and a lower narrow side], as shown in Figure 10. Please pay special attention to the width of the gate 8 Is the smallest size of the Zhenyao circuit, and the width below the trapezoidal opening can be The width of the rigid pole 8 of the "N-channel gold-oxygen half field effect transistor" is small, that is to say, the width below the trapezoidal opening is smaller than the lithographic resolution limit. Therefore, the width below the trapezoidal opening provides a process buffer , To appreciate the number of light lifts, the face of the sand is still touched to form a ca ditch '. Therefore, the solution Z— "H · Tongjin Qiqi Field Effect Electric Crystal Stirrup", the current blocking and junction short circuit This phenomenon is the present invention. —.................. The above is an extensive description of the invention with preferred embodiments, not a limitation of the invention, and it is well known Those skilled in semiconductor technology can understand that appropriate and slight changes and adjustments will still not lose the essence of the present invention, and will not deviate from the spirit and scope of the present invention. This paper scale uses the Chinese National Sample Rate (CNS) Α4 Specifications {2 丨 0 X 297 Gong Xian > (Please read the note ^ * on the back before filling this page)