TW295720B - Method for manufacturing the Salicide with N2 layer silicidation mask - Google Patents

Abstract

A method of manufacturing Salicide includes a) forming the field oxide layer on the silicon substrate for the need of isolation active area. b) forming the gate oxide, the polysilicon gate electrode, and the source\drain of the MOSFET. c) forming the photoresist pattern by the microimage technique, which exposes part of the substrate of the source/drain. d) implanting the N2 ion into the exposed surface of the substrate to form an N2 layer. e) depositing a layer of metal. f) performing high-temperature anneal to cause the silicidation between the metal and the silicon atoms near the substrate surface and to form the metal silicide on the surface of the source/drain. g) the high-temperature anneal also cause the silicidation between the metal and the polysilicon gate electrode to form the metal Salicide on the surface of the polysilicon gate, and the metal without silicidation is remained on the surface of the N2 layer, and h) removing the remained metal without silicidation.

Description

B 'V. Description of the invention (/) (1) Technical Field The month m discloses the [Automatic Aligned Silicide] of the [Metal Oxide Half Field Electric Crystal] of the integrated circuit (Self-Aligned Silicide;

Salicide) manufacturing method (Method). (2) Background of the invention

A In the field of submicron integrated circuits, in order to improve the performance of [Gold Oxygen Half Field Effect Transistors]-a traditional manufacturing method called [Self-Aligned Silicide] (Self-Aligned Silicide) was revealed, The traditional [automatic alignment of silicide] process method is described below with reference to FIGS. 1 to 7. First, a field oxide layer (Field Oxide) is formed on the semiconductor substrate 2 as an isolation element, then, a gate oxide layer 4 (Gate Oxide) of [Gold Oxygen Half Field Effect Transistor] is formed, and then, [ Metal Oxygen Half Field Effect Transistor】 Polysilicon Gate Electrode 6 (Polysilicon Gate Electrode). Then, N-lightly doped ion distribution is performed to form [N-lightly doped source / drain] '. Then, a dielectric layer 8 is deposited, and the etching is performed vertically and unidirectionally using the etching technique. Electrical layer 8] Anisotropically Etchback to produce sidewall spacers 8A (Spacer) on both sides of the [Gate 6], and then perform π concentrated doping ion distribution to form [N + thick miserable Heteroly source / drain 10] (Heavi ly Doped Source / Drain) 'as shown in Figure 1. Next, a layer of silicon dioxide sand 12 (Silicon Dixoide; Si〇2) is deposited as shown in FIG. 2. Then, a photoresist pattern 14 is formed by photolithography technology, and the [photoresist pattern 14] covers a part of the [silicon dioxide layer 12], as shown by circle 3. Next, the plasma etching technique is used to etch the exposed [silicon dioxide layer 12] to form a pattern of [silicon dioxide layer 12A], and the paper and paper * ruler Jt is washed with the middle a · jialiang rate (CNS) A4 Pile (ϋίοχ 297 mm

Locust Ji # * 夹 * 袅 || »? | 二 .-4 * < >#-. 注 访 龙

_B: _ V. Description of the invention (>) As shown in Figure 4. Next, a layer of titanium metal 16 (Titanium; Ti) 'is formed as shown in FIG. 5. Then, perform [Anneal] 'The [Temperature Treatment] so that [Titanium 16] and the silicon atoms on the surface of the [Semiconductor Substrate 2] undergo a silicidation reaction (Silicidation)' Miscellaneous source / drain 10] [Automatically aligned titanium silicide 18A] (TiSi2) is formed on the surface, and [Automatically aligned titanium silicide 18B] is formed on the surface of the [polycrystalline silicon gate 6], leaving The titanium metal 16A without the [siliconization reaction], as shown in Figure 6. Finally, remove the titanium metal 16A that has not undergone the [siliconization reaction], and [automatically align the titanium silicide 18] to form, as shown in Figure 7. The problem is that the integrated circuit components are continuously shrinking. The width of the [side wall sub 8A] on both sides of the [polycrystalline silicon gate 6] is getting shorter and shorter, even less than 0.1 micron, and as shown in FIG. 4, Award etch technology uranium to expose the [silicon dioxide layer 12] to form the [silicon dioxide layer 12A] pattern '[side wall sub 8A] will be etched again and the width of the [side wall sub 8A] will be shorter In this way, it is more likely to cause leakage between the [polysilicon gate 6] and [N + concentrated doped source / drain 10], resulting in a short circuit (Short). Therefore, it is a very important issue to provide a "self-aligning silicide" without leakage phenomenon. (3) Brief description of the invention The main purpose of the present invention is to provide a "Leakage" (automatic alignment | quasi-silicide) between the i-gate and the source / drain of the [metal oxide half field effect transistor] (Self Aligned Silicide; Salicide) manufacturing i I (please first "Notes on the back of 1 # and fill in the clothes f)-Install. 緢 粢 -1- —1 .n l >

Jlsi- · Gong paper ΧΑ4Λ (CNS) (210X 297 gong) 钂 蓊 # * 夹 * 袅 马 | 二. '## < ^ 肀. 法. ％ ?. Fifth, the invention description (3) method. Another object of the present invention is to provide a [low manufacturing cost] [metal oxide half field effect transistor] [automatically aligned sands] manufacturing method. The main process of the present invention is as follows. First, the [field oxide layer] is formed on the silicon semiconductor substrate to isolate the electrical components, then, the gate oxide layer of the [gold oxide half field effect transistor] is formed (using 〖6〇 \ 1 (^), then , To form a polycrystalline silicon gate electrode (P〇lysilicon Gate Electrode) of [Gold Oxygen Half Field Effect Transistor]. Then, lightly doped ion distribution is performed to form [N · Lightly Doped Source / Drain], then , Deposit a dielectric layer (Dielectric), and use etching technology to vertically and unidirectionally etch back the [dielectric layer] (Anisotropically Etchback) to generate on both sides of the [polycrystalline silicon dendritic pole] Spacer, and then, N + concentrated doped ion distribution, to form [N + concentrated doped source / drain] (Heavily Doped Source / Drain). Then, using photolithography technology to form a photoresist pattern, so Describe [Photoresist pattern] a part of the [N + densely doped source / drain]. Then, use ion implantation technology (Ion Implantation) to implant nitrogen ions onto the surface of the [sand semiconductor substrate] to form A layer of nitrogen ion layer (N2 Layer), said [nitrogen ion layer The component is nitrided sand (SiHcon Nitride), which is used as a silicified protective cover for subsequent metal sanding (in 1 丨 {^ 衍 011! 1381 (). Then, a layer of titanium metal is formed, and then, high temperature is applied. Fire treatment] (Anneal) 'The [tempering treatment] causes the [titanium metal] to undergo a silicidation reaction with the silicon atoms on the surface of the [silicon semiconductor substrate], so that the [r concentrated doping source / drain ] Surface formation [Automatic alignment of titanium silicide] (TiSi2); The [tempering treatment] also makes --------- ^ ------ 'ΤΓ ------ ^. {Please first "Please note the precautions * Please fill in the nest treasure" family members with t 钃 面 »((210X 297mm >

V

V. Description of the invention (ψ) [Titanium metal] reacts with the silicon atoms on the surface of the [polycrystalline silicon gate] to form a [self-aligned titanium silicide] on the surface of the [polycrystalline silicon gate] (TiSi2), and on the surface of the [nitrogen ion layer] and the [side wall sub-surface], titanium metal that has not undergone the [silicidation reaction] is left. Align Titanium Silicide】 Yu Yan formation. It is easy to know that the present invention saves the deposition and plasma etching steps of the [silicon dioxide layer 12] in the traditional method (Figures 3 to 5), and uses the [nitrogen ion layer] as the silicidation protection mask (N2 Layer Silicidation Mask) To replace the traditional oxide layer protection mask (Oxide Layer Silicidation Mask), in addition to preventing the width of the [side wall] from becoming shorter, it simplifies the manufacturing process and reduces manufacturing costs. (4) Brief description of the drawings Figures 1 to 7 are prior art process cross section schematic diagrams of the prior art of [self-aligned silicide] (Prior Art Process Cross Sectional) ° Figures 8 to 13 are the processes of the embodiment of the present invention Schematic cross section. (5) Detailed description of the invention This part will be accompanied by the illustration. Only the N-Channel Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) is drawn in the part of the figure, omitting the [P channel Metal Oxide Half Field Effect Transistor] structure, and this process can be naturally extended to complementary metal oxide half field effect transistor (Complementary Metal Oxide

Semiconductor Field Effect Transistor; CM0SFET) process. (Please note clearly the «Precautions on« nose fill in this book 1) Binding Bundling paper Λ scale selection with t 面 銸 家 _ (CNS) A4 shuffle (210 · Χ 297mm>

钂 聚 # ·%: 夭-♦ 1 MA < x.: «F >» t.s. V. Description of the invention (i :) Refer to FIG. 8. First, a standard process is used to form the [field oxide layer] required to isolate the electrical active area on the P-type silicon semiconductor substrate 20 (Silicon Semiconductor Substrate) in the lattice direction (100). 】 The thickness is between 3000 Angstroms and 6000 Angstroms, which is used to isolate electrical components. Next, the surface of the [P-type silicon semiconductor substrate 20] is thermally oxidized to form a gate oxide layer 22 (Gate Oxide) with a thickness of 80 to 200 Angstroms. Then, a polysilicon layer 24 (Polysilicon) is formed by Low Pressure Chemical Vapor Deposition (LPCVD). The [polysilicon layer 24] is generally doped with synchronous phosphorus (In-situ Phosphorus Doped) The low-pressure chemical vapor deposition method is formed. The reaction gas is a mixed gas of PH3, SiH4 and N2. Its reaction temperature is between 520 and 580 ° C, and its thickness is between 1000 and 3000 Angstroms. Then, the [polysilicon layer 24] is etched away using lithography and plasma etching techniques to form a polysilicon gate electrode 24 (Gate! Electrode). The plasma etching of the [polycrystalline silicon layer 2i] can use Magnetic Enhanced Reactive Ion Etching (MERIE) or Electron Cyclotron Resonance (ECR) or traditional Reactive Ion Etching (RIE) technology, in the field of sub-micron technology, usually using [magnetic field enhanced active ion plasma saturation technology], the plasma reaction gas is generally Cl2 and HBr Wait for gas. Refer to Figure 8 again. Next, deposit a dielectric layer 26 (Dielectric), and use plasma etching technology to perform a one-way back etching (Anisotropical Etchback) on the [dielectric layer 26], {please first (Fill in). 装 · Order 粢 Christine paper permanent standard __ order __ * 4 »(CNS) A4 gauge · (210X 297mm)

5. Description of the invention (b) The side wall 26A is formed beside the [polycrystalline silicon gate 24] (Spacer). The [dielectric layer 26] is usually a silicon dioxide layer formed by [low-pressure chemical vapor deposition method] whose reaction gas is tetraethyl silicate (TetraEth0xySilane; TE0S; Si (C2H50) 4) , Its thickness is between 1000 and 3000 angstroms. The [unidirectional etch back] of the [dielectric layer 26] can use [magnetic field enhanced active ion electric prize etching] or [electron cyclotron resonance plasma etching] or traditional [active ion plasma etching] [Technology], in the field of sub-micron technology, usually [magnetic field enhanced active ion plasma etching technology], the plasma reaction gas is generally CF4, CHF3 and Ar gas. Then, perform the N + concentrated doped ion distribution to form [N + concentrated doped source / drain 28] (Heavily Doped Source / Drain). Next, a photoresist pattern 30 (photoresist pattern) is formed by using lithography technology, and the [photoresist pattern 30] exposes a part of the [N + densely doped source / drain 28] at the [opening 31], such as Figure 9 shows. Then, the ion implantation technology (Ion Implantation) is used to implant nitrogen ions into the [silicon semiconductor substrate 20] through the [opening 31] to form a nitrogen ion layer 32 (N2 Layer) on the surface of the [silicon semiconductor substrate 20], as shown in the figure 10 is shown. The composition of the [nitrogen ion layer 32] is Silicon Nitride, which is prepared to be used as a silicidation mask for subsequent metal silicidation. After removing the [photoresist pattern 30], a layer of titanium 34 (Titanium) is formed as shown in FIG. Then, implement [Anneal] with a temperature between 650 丨 ° C and 750 ° C. The [return i | fire treatment] makes the [titanium metal 34] and the [silicon semiconductor substrate 20] Surface i < please pay attention to the "please note #early writing clothes f > -installed-ordered, 钃 _ 家 箱 · (CNS) A4 present grid (210x297mm)

Fifth, the description of the invention (7) sand atoms undergo a sanding reaction (Silicidation) to form a [self-aligned titanium silicide 36A] (TiSi2) on the surface of the [N + concentrated doped source / drain 28]; The [tempering treatment] also causes the [titanium metal 34] to react with the silicon atoms on the surface of the [polycrystalline silicon gate 24] to form an [automatic pairing] on the surface of the [polycrystalline silicon gate 24] Quasi-titanium silicide 36B] (TiSi2), and the titanium metal 34A without the [siliconization reaction] left on the surface of the [nitrogen ion layer 32] and the surface of the [side roller 26], as shown in FIG. 12 . Finally, remove [Titanium Metal 34A] where [Silylation Reaction] has not occurred, and a non-leakage phenomenon [Automatically Aligning Titanium Silicide 36] is formed in Yan, as shown in Figure 13. In addition, the above [sandification reaction] can also be completed by using [Rapid Thermal Anneal; RTA]. The above is a description of the present invention using the preferred embodiments, rather than limiting the present invention, and those skilled in the art of semiconductors can understand that appropriate and slight changes and adjustments will still lose the gist of the present invention. Without departing from the spirit and scope of the present invention. {Please First "Please pay attention to the matters you need to fill in the clothes I > clothes weaving & standard sloppy t ·· Home Xiongju (CNS) Α441» (210 X 297mm)

Claims (1)

A8 B8 C8 ____ ------- Sixth, the scope of patent application 1.-Method of manufacturing [Self-Aligned Silicide] (Self-Aligned Silicide; Salicide) , Which includes: forming the [field oxide layer] required to isolate the electrical active area on the silicon semiconductor substrate (Silicon Semiconductor Substrate); forming the gate oxide layer (Gate Oxide) of the [gold oxide half field effect transistor] 、 Gate Electrode and 【Source / Drain】; Use photolithography technology to form a photoresist pattern, part of which is exposed The [source / drain] surface of the silicon semiconductor substrate; using ion implantation technology (Ion Implantation) to implant nitrogen ions into the exposed [silicon semiconductor substrate surface], so that the exposed [silicon semiconductor substrate Surface] Form a layer of nitrogen ion (N2 Layer); deposit a layer of [metal]; perform high temperature [high temperature tempering] (Anneal), the [high temperature tempering] makes the [metal] follow the surface of the [silicon semiconductor substrate] The silicon atom undergoes a sanding reaction (Silicidation) to form a [MetalSilicide] on the surface of the [source / drain], and the [high temperature tempering] also causes the [metal] to follow The silicon atoms on the surface of the [polycrystalline silicon gate] undergo a silicidation reaction to form an [automatically aligned metal silicide] (Metal Silicide) on the surface of the [polycrystalline silicon gate], and on the [nitrogen ion layer The surface and the surface of the [side wall] are left with the [metal] where the [silicidation reaction] has not occurred; removing the [metal] without the [silicidation reaction]. 2. The method as described in item 1 of the patent scope, where the "metal" refers to titanium, titanium, cobalt, and tungsten etc ... .... r skirt ---- (............ order ............; ^ (please read the notes on the back first and then fill in (This page) This paper scale applies to China National Standard (CNS) A4 (210 X 297 mm) ABCD VI. Patent application scope Refractory Metal 3. If you apply for a patent, scope_ 1 method, The "high temperature tempering" mentioned in it can be carried out using traditional furnace tubes (Furnace) or "rapid thermal annealing" (Rapid Thermal Anneal; RTA).: ... ......... installed ................................................................ (Please read the back first Please pay attention to this page and then fill out this page.) The paper printed by the Consumer Standards Bureau of the Central Standards Bureau of the Ministry of Economic Affairs applies the Chinese National Standard (CNS) A4 specification (210Χ 297 mm).