JPH06295875A - Formation of resist pattern and fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for forming a resist pattern in which the inclination angle is relaxed at the time of oblique ion implantation corresponding to fine patterning of LSI, and a method for fabricating a semiconductor device using the resist pattern. CONSTITUTION:The method for fabricating a semiconductor device comprises a step for forming a impurity blocking film on the entire surface of a semiconductor substrate 1, a step for patterning the impurity blocking film to form an impurity blocking film 8, a step for tapering the impurity blocking film 8 by isotropic etching or heating, and a step for introducing impurities at a predetermined angle into a predetermined region 10 on the semiconductor substrate 1 using the tapered impurity blocking film as a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resist forming method and a semiconductor device manufacturing method, and more particularly to a resist taper method and an oblique ion implantation method using a taper-processed resist.

[0002]

2. Description of the Related Art With miniaturization of LSI, the threshold value of a gate in a MOS transistor increases due to the hot electron effect at the drain end of the channel. Since this phenomenon occurs with the operation, the circuit malfunctions.
As one of methods for suppressing the hot electron effect, an LDD (Lightly Doped Domain) structure is incorporated in the device structure of the LSI. In the LDD structure, an N ⁻ layer (hereinafter referred to as an LDD region) is provided at the end of the drain to prevent the depletion layer formed therein from having a high electric field and reduce the hot electron effect.

In order to provide an N ^- layer in this LDD region, a technique of oblique ion implantation for selectively ion-implanting low concentration N-type impurities such as phosphorus (P) and arsenic (As) into this region is used. To be

FIG. 6 is a diagram showing a conventional oblique ion implantation method. As shown in FIG. 6, LOC is formed on the p-type silicon substrate 1.
The field oxide film 3 is formed by the OS method, and then the gate oxide film 5 is formed by the thermal oxidation method. Next, CVD
A polysilicon film is formed by the (chemical vapor deposition) method, and then the polysilicon film is patterned by lithography and RIE to form the gate electrode 4.

Next, a resist pattern 104 is formed by lithography. Using this resist pattern as a mask, N-type impurities such as arsenic (As) are selectively doped in the LDD implantation region 10 at a low concentration in the normal direction of the p-type silicon substrate 1. And oblique ion implantation is performed at a predetermined angle θ (hereinafter referred to as an ion implantation inclination angle).

[0006]

With the miniaturization of LSIs, the LDD implantation region 10 for ion implantation is also becoming smaller. On the other hand, the resist pattern 104 for selecting the implantation portion needs a certain thickness to function as a stopping mask. As a result, the aspect ratio of the resist, which is the ratio between the width of the LDD-implanted region 10 and the film thickness of the resist pattern 104, is increasing, and the inclination angle of ion implantation is decreasing.

FIG. 7 is a diagram for obtaining the tilt angle θ of ion implantation. The width of the gate electrode 4 is G, the width of the LDD implantation region 10 is G / 2, the distance between the resist pattern 104 and the gate electrode 4 is 2G, and the film thickness t of the resist pattern is t.
Is 3 G, the tilt angle θ of ion implantation is as follows.

Θ = tan ^-1 ((2G-G / 2) / 3G) However, since the gate electrode 4 may expand to the left and right by ΔL due to manufacturing processing accuracy, the implantation region 10
When the width of G is secured as G / 2, the LDD implantation region 10
The end portion of is shifted by ΔL and is located at P ₂ . Further, when the side wall that determines the LDD region is increased by ΔS due to the processing accuracy, the end portion of the LDD implantation region 10 is further increased by ΔS.
Shift and is located in P _3.

Further, since the gate electrode 4 and the resist pattern are formed by using lithography, it is necessary to align the mask. If the mask is aligned with the field oxide film 3, the alignment will be misaligned. If the margin of the gate electrode 4 is M ₁ and that of the resist pattern 104 is M ₂ , the margin of
The margin of misalignment between the resist pattern 104 and the resist pattern 104 is M
_When it becomes ₃ , it becomes the following.

M ₃ = (M ₁ ² + M ₂ ² ) ^1/2 Further, the margin of the film thickness of the resist pattern 104 is Δt.
Then, the tilt angle θ ′ of the ion implantation considering these margins is as follows.

Θ '= tan ^-1 ((2G-G / 2-ΔL-Δ
Since S−M ₃ ) / (3G + Δt)) θ ′ <θ, the tilt angle of ion implantation is further limited to a small value.

As described above, if the tilt angle of the ion implantation is limited, it becomes a problem in designing the LSI.

In order to solve this problem, a method of limiting the tilt angle of ion implantation to reduce the ability of the LSI can be considered, but this method is not practical. Also, in each ion implantation process, the energy at the time of ion implantation is different and the minimum film thickness of the resist pattern as the stopping mask is different, so the resist pattern with the minimum film thickness in each ion implantation process is used. However, since the film thickness of the resist pattern is mainly determined by the viscosity, a resist having various viscosities is required, and the inventory management of the resist becomes troublesome.

Therefore, the present invention provides a method of forming a resist pattern for mitigating the tilt angle of ion implantation at the time of oblique ion implantation and a method of manufacturing a semiconductor device using the resist pattern in order to cope with the miniaturization of LSI. The purpose is to

[0015]

According to the present invention, in the method for manufacturing a semiconductor device having a step of introducing impurities into a semiconductor substrate, a film for blocking the impurities is formed on the entire upper surface of the semiconductor substrate. A step of forming an impurity blocking film by patterning a film for blocking the impurities, and a step of making the impurity blocking film have a tapered shape by isotropic etching or heating. And a step of introducing the impurity into a predetermined region of the semiconductor substrate at a predetermined angle using the impurity blocking film having the taper shape as a mask.

Further, according to the present invention, the above problems can be preferably solved by a method for manufacturing a semiconductor device, wherein the impurity blocking film is a silicon nitride film.

[0017]

According to the present invention, after forming a resist pattern by lithography as shown in FIG. 1A, when this resist pattern 8 is isotropically etched, for example, at the corners of the resist pattern 8, the vertical and horizontal directions are formed. Since it is etched and has a higher etching rate than the others, it is sharpened to form a tapered shape. Therefore, this resist pattern 9
When the oblique ion implantation is performed by using as a mask, the resist pattern 9 has a tapered shape, and therefore the inclination angle of the Δθ ion implantation can be relaxed.

Further, according to the present invention, when the silicon nitride film 40 is used as the impurity blocking layer as shown in FIG. 3, since this silicon nitride film has a larger ability to block impurities than photoresist, the film thickness is reduced accordingly. Therefore, the aspect ratio can be made smaller and the tilt angle of ion implantation can be further relaxed.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1 and 2 are process cross-sectional views according to the first embodiment of the oblique ion implantation method according to the present invention.

As shown in FIG. 1A, a field oxide film 3 is formed on a p-type silicon substrate 1 by the LOCOS method,
After that, the gate oxide film 5 is formed by the thermal oxidation method. Next, a 200 nm-thickness polysilicon film is formed on the entire surface by the CVD method. Next, a resist film is formed on the entire surface by spin coating, and the field oxide film 3 is aligned with a mask, exposed, and developed to form a resist pattern. Next, using this resist pattern as a mask, RIE is performed.
The polysilicon film is patterned by (reactive ion etching) to form a gate electrode 4 having a width of 0.4 μm,
Strip the resist pattern.

Next, 120 is applied to the entire surface by spin coating.
A resist film having a thickness of 0 nm is formed, the field oxide film 3 is aligned with a mask, exposed, and developed to form a resist pattern 8.

Next, as shown in FIG. 1B, the resist pattern 8 is etched by 100 nm by isotropic plasma etching using oxygen plasma or the like. Since this etching is isotropic, the corners of the resist pattern 8 are etched in the vertical and horizontal directions, and since the etching rate is higher than the others, the corners are removed to form a tapered shape.

Next, as shown in FIG. 2A, the p-type silicon substrate 1 is tilted using the resist pattern 9 as a mask, and arsenic (As), for example, as an N-type impurity has an energy of 30 kev and a concentration of 2 to 3 × 10. ¹³ / cm ² with a width of 0.2
Oblique ion implantation is performed on the LDD-implanted region 10 of μm. At this time, since the resist pattern 9 has a tapered shape with an angle, the inclination angle of the ion implantation is Δθ.
The size can be increased, and the limitation on the ion implantation tilt angle can be relaxed. Next, the resist pattern 9 is peeled and removed.

Next, a SiO ₂ film with a thickness of 200 nm is formed by the CVD method, and then the entire surface is etched back by RIE to form the side wall 12 as shown in FIG. 2B, and the LDD implantation region 10 is formed. Coat the top.

Next, 1 is formed by the thermal oxidation method or the CVD method.
An oxide film with a thickness of 00 nm is formed, and the sidewall 12
As a mask, N-type impurities such as arsenic (As) are ion-implanted at an energy of 20 kev and a concentration of 5 × 10 ¹⁵ / cm ² , followed by heat treatment to activate the N ⁺ diffusion layer 11 and the N ⁻ diffusion LDD. The region 10a is formed.

FIG. 3 is a sectional view showing a second embodiment of the oblique ion implantation method according to the present invention.

In this embodiment, unlike the first embodiment, the LD
A silicon nitride film having an excellent blocking ability was used as an impurity blocking layer for selectively implanting ions into the D implantation region 10.

As shown in FIG. 3, as in the first embodiment, p
A field oxide film 3, a gate oxide film 5 and a gate electrode 4 are formed on the silicon substrate 1. Next, a silicon nitride film is formed by the CVD method, and the silicon nitride film is patterned by lithography and RIE to form a silicon nitride film pattern 40.

Next, the silicon nitride film pattern 40 is etched by isotropic etching such as wet etching to give the silicon nitride film pattern 41 a tapered shape.

Next, using the silicon nitride film pattern 41 as a mask, As is obliquely ion-implanted into the LDD-implanted region 10 in the same manner as in the first embodiment. At this time, since the silicon nitride film pattern 41 has a better impurity blocking ability than the resist pattern 8, the film thickness can be made thinner, the aspect ratio can be made smaller, and the taper shape makes the ion implantation inclination angle Δ. θ ₁ can be relaxed.

Next, the silicon nitride film pattern 41 is removed, and the sidewall 12, the LDD region 10a and the N ⁺ diffusion layer 11 are formed as in the first embodiment.

FIG. 4 is a sectional view showing a third embodiment of the oblique ion implantation method according to the present invention.

In this embodiment, the pocket layer 20 containing a p-type impurity having a concentration higher than that of the p-type impurity is provided in a region adjacent to the N ⁺ diffusion layer 21 forming the source region and the drain region. Is. This pocket layer 20
Reduces the width of the depletion layer of the source junction and the depletion layer of the drain junction and raises the threshold value of the channel end to suppress punch-through, which is a phenomenon in which the depletion layer of the source junction contacts the depletion layer of the drain junction. The short channel effect is reduced.

As shown in FIG. 4, p as in the first embodiment.
A field oxide film 3, a gate oxide film 5 and a gate electrode 4 are formed on the silicon substrate 1. Next, a resist pattern 30 is formed by lithography as in the first embodiment, and then isotropic etching such as plasma etching is performed to etch the resist pattern 31 into a tapered shape.

Next, using the resist pattern 31 as a mask, for example, boron is used as a p-type impurity in the pocket layer implantation region 23 with an energy of 60 kev and a concentration of 5 × 1.
Diagonal ion implantation is performed at 0 ¹² . At this time, since the resist pattern 31 has a tapered shape, the restriction on the ion implantation inclination angle can be relaxed by Δθ ₂ .

Next, with the gate electrode 4 as a mask, arsenic (As), for example, is used as N-type impurity with an energy of 20 ke
v, the concentration 5 × 10 ¹⁵ / cm ² with ion implantation performs activation and thereafter heat treated to form a pocket layer 20 and N ⁺ diffusion layer 21.

FIG. 5 is a sectional view showing a fourth embodiment of the oblique ion implantation method according to the present invention.

In this embodiment, oblique ion implantation is applied to contact compensation ion implantation for making ohmic contact with the p-type silicon substrate 1.

As shown in FIG. 5, after forming the field oxide film 3 by the LOCOS method, an N ⁺ diffusion layer 50 is formed to make contact with the p-type silicon substrate 1. Next, the interlayer insulating film 51 is formed by the CVD method, and then a resist pattern (not shown) is formed by lithography, and the interlayer insulating film 51 contact hole is opened by RIE using this resist pattern as a mask. At this time, if the position of the resist pattern is displaced due to the displacement of the mask (FIG. 5 shows the case where the resist pattern is displaced to the right), the end portion of the contact hole comes closer to one of the field oxide films 3. This will cause a junction leak here. Therefore, in order to prevent this, N ⁺ impurities are obliquely ion-implanted into this portion.

Therefore, the above resist pattern is peeled off.
After the removal, a resist pattern 52 is formed as an impurity blocking layer for contact compensation. After that, the resist pattern 5 is formed by isotropic etching such as plasma etching.
3 is tapered.

Next, using the resist pattern 53 as a mask, arsenic (As) as an N-type impurity is obliquely ion-implanted while rotating the silicon substrate 1 to perform contact compensation. At this time, since the resist pattern 53 has a tapered shape, the limitation of the inclination angle of the ion implantation can be relaxed by Δθ ₃ , and the margin of mask misalignment at the time of forming the contact hole can be increased.

[0043]

As described above, according to the present invention, the angle of the resist pattern is set to be a taper shape, and the oblique ion implantation is performed using this as a mask. Therefore, the limitation of the inclination angle of the ion implantation can be relaxed. It is possible to effectively take measures against the short channel effect and the hot electron effect of the fine LSI and improve the reliability of the device.

Further, since the aspect ratio can be made smaller by using the silicon nitride film as the impurity blocking layer, the limitation on the tilt angle of the ion implantation can be further relaxed.

[Brief description of drawings]

FIG. 1 is a sectional view (I) of an oblique ion implantation process according to the first embodiment.

FIG. 2 is a sectional view (II) of the oblique ion implantation process according to the first embodiment.

FIG. 3 is a sectional view showing an oblique ion implantation method according to a second embodiment.

FIG. 4 is a sectional view showing an oblique ion implantation method according to a third embodiment.

FIG. 5 is a sectional view showing an oblique ion implantation method according to a fourth embodiment.

FIG. 6 is a cross-sectional view showing a diagonal ion implantation method according to a conventional example.

FIG. 7 is a diagram for explaining a tilt angle of ion implantation.

[Explanation of symbols]

1 p-type silicon substrate 3 field oxide film 4 gate electrode 5 gate oxide film 8,30,52 resist pattern (before processing) 9,31,53 resist pattern (after processing) 10 LDD implantation region 10a LDD region (N ⁻ region) 11, 21 N ⁺ Diffusion layer 12 Sidewall 20 Pocket layer 23 Pocket layer implantation region 40 Silicon nitride film pattern (before processing) 41 Silicon nitride film pattern (after processing)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 7352-4M H01L 21/30 361 V

Claims (7)

[Claims] 1. A step of forming a resist film on the entire upper surface of a semiconductor substrate, a step of patterning the resist film by lithography to form a resist pattern, and a step of etching the resist pattern isotropically to form a tapered shape on the resist pattern. And a step of forming a resist pattern. 2. A step of forming a resist film over the entire surface of a semiconductor substrate, a step of patterning the resist film by lithography to form a resist pattern, and a step of heating and deforming the resist pattern to taper the resist pattern. And a step of imparting a shape to the resist pattern. 3. A method of manufacturing a semiconductor device, comprising a step of introducing impurities into a semiconductor substrate, the step of forming a film for blocking the impurities on the entire upper surface of the semiconductor substrate, and the step of blocking the impurities. Patterning the film to form an impurity blocking film; forming the impurity blocking film into a tapered shape by isotropic etching or heating the impurity blocking film; and using the tapered impurity blocking film as a mask. A step of introducing the impurities into a predetermined region of the semiconductor substrate at a predetermined angle, the method for manufacturing a semiconductor device. 4. A channel region containing a first impurity in a semiconductor substrate, a first region containing a low concentration second impurity in a region adjacent to the channel region, and a region adjacent to the first region. In a method of manufacturing a semiconductor device having a source region and a drain region composed of a second region containing a high concentration of the second impurity, in order to prevent the second impurity from over the entire surface of the semiconductor substrate. A step of forming a film for forming an impurity blocking film by patterning the film for blocking the second impurity, and isotropically etching or heating the impurity blocking film,
Providing the impurity blocking film with a tapered shape, and introducing the second impurity into the region of the semiconductor substrate forming the first region at a predetermined angle using the tapered impurity blocking film as a mask And a step of manufacturing the semiconductor device. 5. A channel region containing a first impurity, a source region and a drain region containing a second impurity, and a source region and a drain region adjacent to the source region and the drain region on the channel region side in a semiconductor substrate. First of the channel region
A method for manufacturing a semiconductor device having a pocket layer containing a first impurity having a concentration higher than that of the impurity, the step of forming a film for blocking the first impurity on the entire upper surface of the semiconductor substrate; Patterning the film for blocking the first impurities to form an impurity blocking film; and etching or heating the impurity blocking film isotropically.
Providing the impurity blocking film with a taper shape, and using the taper-shaped impurity blocking film as a mask, at a predetermined angle in a region of the semiconductor substrate where the pocket layer is formed and at a concentration higher than that of the channel region, The first
And a step of introducing impurities. 6. A method for manufacturing a semiconductor device, comprising a step of introducing impurities into a contact hole opened in an interlayer insulating film on a semiconductor substrate, wherein a film for blocking the first impurity is formed on the entire upper surface of the semiconductor substrate. Forming the impurity blocking film by patterning the film for blocking the first impurity, isotropically etching or heating the impurity blocking film,
A semiconductor comprising: a step of providing the impurity blocking film with a taper shape; and a step of introducing the impurity into the contact hole at a predetermined angle using the taper-shaped impurity blocking film as a mask. Device manufacturing method. 7. The method of manufacturing a semiconductor device according to claim 3, wherein the impurity blocking film is a silicon nitride film.