306058 A7 B7 五、發明説明（） (-)技術領域 本發明所揭露嘴是有關積體電路之金氧半場效電晶體之自動對準矽化物的製造 方法（Manufacturing Method )。 (二)發明背景. * 爲了提昇改進『金氧半場效電晶體』電路之性能（CircuitPerformance)，在積 體電路技術領域，一種稱爲自動對準矽化物（Self-Aligned Silicide ; Salicide)的製程 方法被揭露，現在利用圖一到圖七說明傳統自動對準砂化物之製程方法如下。 首先，在砂半導體基板10 (Silicon Semiconductor Substrate)上形成場氧化層 (Field Oxide)，作爲隔離電性元件之用，接著，形成所述『金氧半場效電晶體』之 閘氧化層12 (Gate Oxide )，接著，形成所述『金氧半場效電晶體』之閘極14 (Gate Electrode)。接著，利用離子佈値技術（Ion Implantation)來形成【N·淡慘 雜源極/汲極15A/15B】（Lightly Doped Source/Drain)，其離子種類是憐原子 (P31)，其離子佈値劑量介於1E13到3E14原子/平方公分之間，離子佈値能量 則介於20到50 kev之間。然後，沉積一層介電層16，並利用鈾刻技術垂直單向性 地對所述【介電層16】進行單向性的回蝕刻（AnisotropicallyEtchback)，以在所述 【閘極14】之兩側形成介霉層側壁子16A (Dielectric Spacer)，接著，利用離子佈 値技術（Ion Implantation)進行N+濃摻雜離子佈値i以形成『N+濃摻雜源極/汲 極 18』（Heavily Doped Source/Drain)，如圖一所示。 所述【閘極14】通常是利用磷原子之同步携雜（PhosphomsIn-SituDoped)之 低壓化學氣相沉積法所形成之複晶砂層（PolysiliconLayer)，其反應氣體是PH3和 SiH4的混合氣體，其反應溫度介於530到580 °C之間，其厚度則介於1500到4000 埃之間。所述【介電層16】通常是利用低壓化學氣相沉積法形成之二氧化矽 (Silicon Dioxide ; Si02)，其厚度介於1000到2500埃之間。所述『N+濃摻雜 經濟部中夬橾隼局貝工消费合作社印家 (諳先閱讀背面之注意事項再填寫本頁) 源極/汲極18』離子佈値之離子種類是砷原子（As75)，其離子佈値劑量介於 1E15到5E16原子/平方公分之間，離子佈値能量則介於20到100 Kev之間。 在作過適當表面淸潔處理後，接著，利用濺鍍技術形成一層鈦金屬20 (Titanium ; Ti)，如圖二所示。然後，進行『高溫回火處理』（Anneal)，所述 【高溫回火處理】使所述【鈦金屬20】跟所述【半導體基板10】表面之矽原子發 生矽化反應（Silicidation)，以在所述【N+濃摻雜源極/汲極18】表面形成一層 F自動對準鈦矽化物2〇A』（TiSi2)，而在所述【閘極14】之上表面則形成【自 動對準鈦矽化物20B】，而留下未發生【矽化反應】之鈦金屬20A，如圖三所示。 最後，去除未發生【砂化反應】之所述『鈦金屬20A』，『自動對準欽砂化物20』 於焉完成，如圖四所示。所述『自動對準欽矽化物20』能大幅提昇改進『金氧半場 效電晶體』電路之性能（CircuitPerformance)。 本紙依尺度逍用中困困家揉準（CNS > Α4规格（2丨0X297公釐） 經濟部中央標準局貝工消费合作社印製 A7 B7 五、發明説明（） 然而，當積體電路元件不斷的縮小，所述【閘極14】兩側之所述『介電層側 壁子16A』的寬度越來越短，^甚至小於0.1微米，造成所述【鈦金屬20】跟所述 【半導體基板10】表面之矽子發生矽化反應（Silicidation)時，矽原子沿著所述 『介電層側壁子16A』的表面擴散，形成『二矽化鈦』（TiSi2)，容易導致所述 【閘極14】跟所述【N+濃摻雜源極/汲極18】之間發生漏電現像（Current Leakage) ’使電路短路故障（Short)。 本發明提出了一種延長閘極跟源極/汲極之間距離的方法，可以消弭閘極跟源 極/汲極之間的漏電問題。 (三)發明的簡要說明 本發明之主要目的是提供一種無漏電之具有f自動對準矽化物』之金氧半場效 電晶體的製造方法。‘ 本發明之主要製程方法如下。首先，在矽半導體基板上形成場氧化層，作爲隔 離電性元件之用，接著，形成『金氧半場效電晶體』之閘氧化層（Gate Oxide)。然 後，沉積一層複晶砂層（Polysilicon )和一層第一介電層（First Dielectric )，並利用 微影技術和電漿蝕刻技術軸、去所述『第一介電層』和一部份厚度的所述複晶矽層， 以形成『凸型的閘極結構』'(Gate Structure)。 接著，沉積一層第二介電層（SecondDielectric),並利用電漿蝕刻技術對所述 『第二介電層』進行單向性的回触刻（AnisotropicallyEtchback)，以在所述【凸型 的閘極結構】之兩側產生第二介電層側壁子（Second Dielectric Spacer)。然後，去 除所述『第一介電層』，使得所述『複晶矽閘極』陷在所述『第二介電層側壁子』 之間。 . 接著，沉積一層鈦金屬，然後，進行『高溫回火處理』，所述【高溫回火處 理】使所述【鈦金屬】跟所述【沉積一層半導體基板】表面之矽原子發生矽化反應 (Silicidation)，以在所述【N+濃摻雜源極/汲極】表面形成一層『自動對準鈦矽 化物』（TiSi2)，而在所述『複晶矽閘極』之上表面則反應形成【自動對準鈦矽化 物】，在所述『第二介電層側壁子』表面則留下未發生『矽化反應』之鈦金屬，然 後，去除未發生『矽化反應』之所述4太金臑』。 最後，利用離子佈値技術進行N+濃摻雜離子佈値，以形成^ N+濃摻雜源極 /汲極』（Heavily Doped Source/Drain)，具有『自動對準砂化物』之金氧半場效 電晶體於焉完成。 本發明之『凸型的閘極結構』延長了所述『複晶矽閘極』跟源極/汲極之間的 距離，因此，消弭閘極跟源極/汲極之間的漏電（CurrentLeakage) ° 本紙張尺度遑用中國國家橾隼（CNS > A4«l格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)306058 A7 B7 V. Description of the invention () (-) Technical Field The disclosed mouth of the present invention is related to the manufacturing method of the automatic alignment silicide of metal oxide semi-field transistors of integrated circuits. (2) Background of the invention. * In order to improve the performance of the "metal oxide half field effect transistor" circuit (CircuitPerformance), in the field of integrated circuit technology, a process called self-aligned silicide (Self-Aligned Silicide; Salicide) The method has been revealed. Now, Figures 1 to 7 are used to illustrate the traditional automatic alignment process of sands as follows. First, a field oxide layer (Field Oxide) is formed on the sand semiconductor substrate 10 (Silicon Semiconductor Substrate), which is used for isolating electrical components, and then, a gate oxide layer 12 (Gate Oxide), then, the gate electrode 14 (Gate Electrode) of the "gold oxide half field effect transistor" is formed. Next, Ion Implantation technology is used to form [N · Light Miscellaneous Source / Drain 15A / 15B] (Lightly Doped Source / Drain), whose ion type is a poor atom (P31), and its ion distribution value The dose is between 1E13 and 3E14 atoms / cm2, and the ion distribution energy is between 20 and 50 kev. Then, a dielectric layer 16 is deposited, and the [dielectric layer 16] is vertically and unidirectionally etched back (AnisotropicallyEtchback) on the [dielectric layer 16] using uranium etching technology, so that the two of the [gate 14] The side wall 16A (Dielectric Spacer) of the mesothelium layer is formed on the side, and then, the N + concentrated doping ion distribution is performed by ion implantation technology (Ion Implantation) to form "N + concentrated doped source / drain 18" (Heavily Doped Source / Drain), as shown in Figure 1. The [Gate 14] is usually a polycrystalline sand layer (PolysiliconLayer) formed by low-pressure chemical vapor deposition of phosphorus atoms (Phosphoms In-SituDoped). The reaction gas is a mixed gas of PH3 and SiH4. The reaction temperature is between 530 and 580 ° C, and its thickness is between 1500 and 4000 Angstroms. The [dielectric layer 16] is usually silicon dioxide (Si02) formed by low-pressure chemical vapor deposition, and its thickness is between 1000 and 2500 angstroms. The "N + Concentrated Doping Ministry of Economy, Central Falcon Bureau, Beigong Consumer Cooperative Society (printer) (read the precautions on the back before filling out this page) source / drain 18" ion type is arsenic ( As75), the ion cloth dose is between 1E15 to 5E16 atoms / cm2, and the ion cloth energy is between 20 and 100 Kev. After proper surface cleaning treatment, a layer of titanium 20 (Titanium; Ti) is formed by sputtering technology, as shown in Figure 2. Then, the "high temperature tempering treatment" (Anneal) is carried out, and the [high temperature tempering treatment] causes the [titanium metal 20] and the silicon atoms on the surface of the [semiconductor substrate 10] to undergo a silicidation reaction (Silicidation), in order to A layer of F self-aligned titanium silicide 2〇A ”(TiSi2) is formed on the surface of the [N + concentrated doped source / drain 18], and [auto-alignment] is formed on the surface of the [gate 14] Titanium silicide 20B], leaving the titanium metal 20A without the [siliconization reaction], as shown in Figure 3. Finally, remove the "Titanium 20A" that does not occur in the [sanding reaction], and "Automatically align the sand 20" is completed in Yan, as shown in Figure 4. The "automatic alignment of silicon nitride 20" can greatly improve and improve the performance of the "metal oxide half field effect transistor" circuit (CircuitPerformance). This paper is easy to use according to the standard. (CNS > Α4 specification (2 丨 0X297mm) Printed A7 B7 by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of invention () However, when integrated circuit components Continuously shrinking, the width of the "dielectric layer side wall 16A" on both sides of the [gate 14] is getting shorter and shorter, ^ even less than 0.1 microns, causing the [titanium metal 20] and the [semiconductor Substrate 10] When the silicon on the surface undergoes a silicidation reaction, silicon atoms diffuse along the surface of the "dielectric layer sidewalls 16A" to form "titanium disilicide" (TiSi2), which is likely to cause the "gate" 14] A current leakage phenomenon (Current Leakage) occurs between the [N + concentrated doped source / drain 18] and the circuit is short-circuited (Short). The present invention proposes an extension between the gate and the source / drain The distance between methods can eliminate the leakage problem between the gate and the source / drain. (3) Brief description of the invention The main purpose of the present invention is to provide a metal oxide with no self-leakage and automatic alignment of silicide. The manufacturing method of half field effect transistor. The main processes of Mingming are as follows. First, a field oxide layer is formed on the silicon semiconductor substrate to isolate the electrical components, and then a gate oxide layer (Gate Oxide) is formed. Then, a layer is deposited Polycrystalline silicon layer (Polysilicon) and a layer of first dielectric (First Dielectric), and using the lithography technology and plasma etching technology axis, remove the "first dielectric layer" and a part of the thickness of the polycrystalline A silicon layer to form a "convex gate structure" (Gate Structure). Next, a second dielectric layer (SecondDielectric) is deposited, and the plasma second etching method is used to perform a single process on the "second dielectric layer" Anisotropically Etchback to generate second dielectric layer sidewalls (Second Dielectric Spacer) on both sides of the [convex gate structure]. Then, remove the first dielectric layer ", So that the" polycrystalline silicon gate "is trapped between the" second dielectric layer sidewalls. "Next, a layer of titanium metal is deposited, and then," high temperature tempering treatment ", the [high temperature Tempering The [titanium metal] and the silicon atoms on the surface of the [deposited semiconductor substrate] undergo a silicidation reaction to form a layer of "automatically aligned titanium silicide" on the surface of the [N + concentrated doped source / drain] (TiSi2), and the upper surface of the "polycrystalline silicon gate" reacts to form "automatically aligned titanium silicide", leaving nothing on the surface of the "second dielectric layer sidewall" Titanium metal of "silicification reaction", and then, remove the "4 silicon metal" that has not occurred "silicification reaction". Finally, the ion distribution technology is used to perform N + concentrated doping ion distribution to form ^ N + concentrated doped source / drain, which has a gold-oxygen half-field effect of "automatic alignment with sand" The transistor is completed in Yan. The "convex gate structure" of the present invention extends the distance between the "polycrystalline silicon gate" and the source / drain, therefore, the leakage between the gate and the source / drain is eliminated (CurrentLeakage ) ° This paper uses the Chinese National Falcon (CNS > A4 «l grid (210X297mm) (Please read the precautions on the back before filling this page)
A7 B7 306058 五、發明説明（） (四） 圖示的簡要說明 p -到圖四是『自動對準矽化物』之先前技藝的製程橫截面示意圖。 (請先閱讀背面之注意事項#填寫本萸) 圖五到圖十五爲本發明之實施例的製程橫截面示意圖。 (五) 發明的詳細說明 · 本發明之製程橫截面示意圖只畫出N通道金氧半場效電晶體（N-Channel Metal Oxide Semiconductor Field Effect Transistor ； NMOSFET )，省略【P 通道金 氧半場效電晶體】結構，並且，此製程可自然延伸到與互補式金氧半場效電晶體 (Complementary Metal Oxide Semiconductor Field Effect Transistor ;，CMOSFET )製 程相結合。 首先，以傳統製程在晶格方3 (100)的p型矽半導體基板30 (Silicon Semiconductor Substrate )·表面形成隔離電性活動區（Active Area)所需的場氧化 層，所述場氧化層之厚度介於3500埃到6500埃之間，作爲隔離電性元件之用。接 著，熱氧化（Thermal Oxidized)所述【P型矽半導體基板30】之表面以形成【金 氧半場效電晶體】之閘氧化層32 (Gate Oxide)，其厚度介於80到180埃之 間。然後，沉積一層複晶矽層34\ Polysilicon)和一層第一介電層36 (First Dielectric)，並利用微影技術形成光阻圖案38，再利用電漿触刻技術單向性的蝕 去所述『第一介電層36』和所述複晶矽層34，成爲『第一介電層36A』和所述 『複晶矽閘極34A』，如圖五所示。 經濟部中夬樣牟局貝工消费合作社印製 所述【第一介電層36】通常是利用低壓化學氣相沉積法（Low Pressure Chemical Vapor Deposition ; LPCVD)形成之二氧化砂層（Silicon Dioxide )，其反 應氣體是四乙基矽酸鹽（TetraEthOxySilane ; TEOS ; Si(C2H50)4)，其厚度介於 700到2000埃之間。所述『複晶矽層34』則是利用低壓化學氣相沉積法形成，反 應氣體是PH3和SiH4的混合氣體，其反應溫度介於525到575 °C之間，其厚度 介於1500到3500埃之間。對所述【第一介電層36】之【電漿蝕刻】可以利用磁 場增強式活性離子式電獎蝕刻（Magnetic Enhanced Reactive Ion Etching ; MERIE ) 或電子迴旋共振電费触刻（Electron Cyclotron Resonance ; ECR)或傳統的活性離子 式電漿蝕刻技術（Reactive Ion Etching ; RIE)，在次微米積體電路技術領域，通常 是利用【磁場增強式活性離子式電漿蝕刻技術】，其電漿反應氣體一般是CF4、 0^3和六1·等氣體。對所述【複晶矽層34】之單向性的電漿蝕刻可以利用磁場增 強式活性離子式電漿蝕刻或電子迴旋共振電漿蝕刻或傳統的活性離子式電漿蝕刻技 術，在次微米積體電路技術領域，通常是利用【磁場增強式活性離子式電漿蝕刻技 術】，其電漿反應氣體一般是Cl2和HBr等氣體。 接著，側向蝕去一部份的所述光阻圖案38以露出一部份的所述『第一介電層 36』之表面，如圖六所示。然後，利用電漿蝕刻技術蝕去所述『第一介電層36』 和一部份厚度的所述『複晶矽閘極34A』，如圖七所示，去除所述光阻圖案38之 本紙張尺度逋用中國國家橾率（CNS ) Μ規格（210X297公釐） A7 B7 五、發明説明（） 後則形成由『第一介電層36B』和所述『複晶矽閘極34B』所構成之『凸型的閘 極結構』（Gat* Structure)，如圖八所示。所述『凸型的閘極結構』往所述F複晶 矽閘極34B』芒中心收縮聚集，因此延長了所述『複晶矽閘極34B』跟源極/汲 極之間的距離，故能消弭所述『複晶矽閘極34B』跟源極/汲極之間的漏電 (Current Leakage ) 〇 接著，利用離子佈値技術（Ion Implantation)來形成【N-淡摻雜源極/汲極 39A39B】，其離子種類是磷原子（P31 )，其離子佈値劑量介於1E13到3E14原子 /平方公分之間，離子佈値能量則介於20到50 keY之間。然後，沉積一層第二介電 層40 (Second Dielectric)，如圖九所示，並利用電漿蝕刻技術對所述『第二介電層 40』進行單向性的回触刻（AnisotropicallyEtchback)，以在所述‘【凸型的閘極結 構】之兩側產生第二介電層側壁子40A (Second Dielectric Spacer)，如圖十所示。 然後，去除所^第一介電層』，使得所述『複晶矽閘極34A』陷在所述『第二介 電層側壁子40A』之間，如圖i^一所示。 接著，沉積一層欽金屬42，如圖十二所示，然後，在爐管中進行『高溫回火 處理』，所述【高溫回火處理】使所述【鈦金屬42】跟所述『矽半導體基板30』 表面之矽原子發生矽化反應（Silicidation)，以在所述『矽半導體基板30』表面形 成一層『自動對準鈦矽化物44A』i：TiSi2)，而在所述『複晶矽閘極34B』之上 表面則反應形成【自動對準鈦矽化物44B】，在所述『第二介電層側壁子40A』 表面則留下未發生『矽化反齒』之鈦金屬42A，如圖十三所示。所述【高溫回火處 理】之溫度介於650°C到750°C之間，另一方面，所述【高溫回火處理】也可以 利用快速熱回火技術（Rapid Thermal Anneal ; RTA)來完成。 最後，利用化學溶液去除未發生『矽化反應』之所述『鈦金屬42A』，如圖 十四所示，€利用離子佈値技術進行N+濃摻雜離子佈値，以形成金氧平場效電晶 體之『N+濃摻雜源極/汲極46』（Heavily Doped Source/Drain)，如圖十五所 示，一個具有『自動對準矽化物』之金氧半場效電晶體於焉完成。所述『N+濃摻 雜源極/汲極46』之離子佈値之離子種類是砷原子（As75)，其離子佈値劑量介 於1E15到5E16原子/平方公分之間，離子佈値能量則介於40到120 Kev之間。 經濟部中央標隼局貝工消费合作社印装 (請先閲讀背面之注意事項再填寫本頁) 必需特別說明的是，所述^ N+濃摻雜源極/汲極46』也可以在形成所述 『第二介電層側壁子40A』之前來完成。 本紙张尺度適用中國國家標率（CNS ) A4規格（2丨0><297公釐） A7 B7 五、發明説明（） 完成所述金氧半場效電晶體的製造後，可以利用標準製程形成接觸窗 (Contact Hole )、第一層金屬連線（First Level Metal Interconnection )、介層孔 (Via Hole)和第二層金屬連線（Second Level Metal Interconnection)，以形成金 氧半場效電晶體積體電路。所述第一層金屬連線通常是以鈦、氮化鈦、鎢和鋁合金 爲材料，並且，所述『第一層金屬連線』跨過所述接觸窗跟所述金氧半場效電晶體 之源極/汲極作電性接觸。所述第二層金屬連線通常也是以鈦、氮化鈦、鎮和鋁合 金爲材料’並且’『第二層金屬連線』跨過所述介層孔跟所述第一層金屬連線作電 性接觸。 以上係以最佳實施例來闡述本發明，而非限制本發明，並且，熟知半導體技藝 之人士皆能明瞭，適當而作些微的改變及調整，仍將不失本發明之要義所在，亦不 脫離本發明之精神和範圍。 {請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作社印製 本纸悵尺度適用中國國家橾率（CNS ) A4说格（210X297公釐}A7 B7 306058 V. Description of the invention () (Ⅳ) Brief description of the figures p-to figure 4 is a schematic cross-sectional view of the process of the prior art of "automatic alignment of silicide". (Please read the notes on the back # fill in the cornel) Figures 5 to 15 are schematic cross-sectional views of the manufacturing process according to an embodiment of the present invention. (5) Detailed description of the invention · The cross-sectional schematic diagram of the process of the present invention only draws N-Channel Metal Oxide Semiconductor Field Effect Transistor (NMOSFET), omitting [P-channel Metal Oxide Semiconductor Field Effect Transistor; NMOSFET] 】 Structure, and this process can be naturally extended to the combination of complementary metal oxide semiconductor field effect transistor (Complementary Metal Oxide Semiconductor Field Effect Transistor ;, CMOSFET) process. First, a conventional process is used to form the field oxide layer required to isolate the electrical active area on the surface of the p-type silicon semiconductor substrate 30 (Silicon Semiconductor Substrate) 30 (100) of lattice square 3 (100). The thickness is between 3500 Angstroms and 6500 Angstroms, which is used to isolate electrical components. Next, the surface of the [P-type silicon semiconductor substrate 30] is thermally oxidized to form a gate oxide layer 32 (Gate Oxide) with a thickness between 80 and 180 Angstroms . Then, a layer of polycrystalline silicon layer 34 \ Polysilicon) and a layer of first dielectric layer 36 (First Dielectric) are deposited, and a photoresist pattern 38 is formed using lithography technology, and then unidirectional etching is used to remove the place The "first dielectric layer 36" and the polycrystalline silicon layer 34 become the "first dielectric layer 36A" and the "polycrystalline silicon gate 34A", as shown in FIG. 5. The [First Dielectric Layer 36] printed by the Beigong Consumer Cooperative of the Ministry of Economic Affairs of Zhongzhang Mou Bureau is usually a silicon dioxide oxide layer (Silicon Dioxide) formed by Low Pressure Chemical Vapor Deposition (LPCVD) The reaction gas is tetraethyl silicate (TetraEthOxySilane; TEOS; Si (C2H50) 4), and its thickness is between 700 and 2000 angstroms. The "polycrystalline silicon layer 34" is formed by low-pressure chemical vapor deposition. The reaction gas is a mixed gas of PH3 and SiH4. Its reaction temperature is between 525 and 575 ° C, and its thickness is between 1500 and 3500. Between Egypt. For the [plasma etching] of the [first dielectric layer 36], Magnetic Enhanced Reactive Ion Etching (MERIE) or Electron Cyclotron Resonance (Electron Cyclotron Resonance) can be used; ECR) or traditional reactive ion plasma etching technology (Reactive Ion Etching; RIE), in the field of sub-micron integrated circuit technology, usually using [magnetic field enhanced active ion plasma etching technology], its plasma reaction gas Generally, it is CF4, 0 ^ 3 and Liu1 · etc. gases. For the unidirectional plasma etching of the [polycrystalline silicon layer 34], magnetic field-enhanced active ion plasma etching or electron cyclotron resonance plasma etching or traditional active ion plasma etching technology can be used. In the field of integrated circuit technology, [Magnetic Field Enhanced Active Ion Plasma Etching Technology] is generally used, and the plasma reaction gas is generally Cl2, HBr and other gases. Next, a part of the photoresist pattern 38 is etched sideways to expose a part of the surface of the "first dielectric layer 36", as shown in FIG. Then, the plasma etching technique is used to etch away the "first dielectric layer 36" and a part of the thickness of the "polycrystalline silicon gate 34A", as shown in FIG. 7, the photoresist pattern 38 is removed This paper uses the Chinese National Standard (CNS) M specifications (210X297mm) A7 B7 5. Description of the invention () After the formation of the "first dielectric layer 36B" and the "polycrystalline silicon gate 34B" The "convex gate structure" (Gat * Structure), as shown in Figure 8. The "convex gate structure" shrinks and gathers toward the center of the F polysilicon gate 34B, thus extending the distance between the "polysilicon gate 34B" and the source / drain, Therefore, the current leakage between the "polycrystalline silicon gate 34B" and the source / drain can be eliminated. Then, the ion implantation technology (Ion Implantation) is used to form the [N-light doped source / Dip 39A39B], its ion type is phosphorus atom (P31), its ion distribution dose is between 1E13 and 3E14 atoms / cm2, and its ion distribution energy is between 20 and 50 keY. Then, deposit a second dielectric layer 40 (Second Dielectric), as shown in FIG. 9, and use plasma etching technology to perform unidirectional back etching (AnisotropicallyEtchback) on the "second dielectric layer 40", The second dielectric layer sidewall 40A (Second Dielectric Spacer) is generated on both sides of the '[convex gate structure], as shown in FIG. 10. Then, the first dielectric layer is removed so that the "polycrystalline silicon gate 34A" is trapped between the "second dielectric layer sidewall 40A", as shown in FIG. Next, deposit a layer of Chin metal 42, as shown in Figure 12, and then perform "high temperature tempering treatment" in the furnace tube. The [high temperature tempering treatment] makes the [titanium metal 42] follow the "silicon The silicon atoms on the surface of the semiconductor substrate 30 undergo silicidation to form a layer of "automatically aligned titanium silicide 44A" (TiSi2) on the surface of the "silicon semiconductor substrate 30", and the "polycrystalline silicon" The upper surface of the gate 34B reacts to form [automatically aligned titanium silicide 44B], leaving the titanium metal 42A on the surface of the "second dielectric layer side wall 40A" without "silicone anti-tooth", such as Figure 13 shows. The temperature of the high temperature tempering treatment is between 650 ° C and 750 ° C. On the other hand, the high temperature tempering treatment can also use rapid thermal annealing technology (Rapid Thermal Anneal; RTA) to carry out. Finally, use chemical solution to remove the "Ti metal 42A" without the "silicidation reaction", as shown in Fig. 14, using ion distribution technology to perform N + concentrated doping ion distribution to form a metal oxide level field effect electricity The "N + Concentrated Doped Source / Drain 46" (Heavily Doped Source / Drain) of the crystal, as shown in Figure 15, a gold-oxygen half-field effect transistor with "auto-aligned silicide" was completed in Yan. The ion type of the "N + concentrated doped source / drain 46" ion type is arsenic atom (As75), the ion distribution dose is between 1E15 to 5E16 atoms / cm2, and the ion distribution energy is Between 40 and 120 Kev. Printed by Beigong Consumer Cooperative of Central Standard Falcon Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page). It must be noted that the ^ N + concentrated doped source / drain 46 can also be formed The "second dielectric layer sidewall 40A" is completed before. This paper scale is applicable to China National Standard Rate (CNS) A4 specification (2 丨 0 > < 297mm) A7 B7 Fifth, the invention description () After completing the manufacture of the gold-oxygen half-field effect transistor, it can be formed using standard processes Contact hole, First Level Metal Interconnection, Via Hole and Second Level Metal Interconnection to form the volume of metal oxide half field effect transistor体 电路。 Body circuit. The first-layer metal connection is usually made of titanium, titanium nitride, tungsten, and aluminum alloy, and the "first-layer metal connection" crosses the contact window and the metal oxide half-field effect The source / drain of the crystal is in electrical contact. The second-layer metal connection is usually made of titanium, titanium nitride, aluminum alloy and aluminum alloy 'and the' second-layer metal connection 'crosses the via hole and the first-layer metal connection Make electrical contact. The above is a description of the present invention with the preferred embodiments, rather than limiting the present invention, and anyone skilled in semiconductor technology can understand that appropriate and slight changes and adjustments will still not lose the essence of the present invention, nor Departs from the spirit and scope of the present invention. {Please read the precautions on the back before filling out this page) Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs This paper is applicable to the Chinese National Standard Rate (CNS) A4 (210X297mm)