經濟部中央樣牟局貝工消费合作社印製 A7 B7 五、發明説明（/ ) (―)技術領域 纟本發明所揭露的是關於積體電路之具有『自動對準矽化物』之金氧半場效電晶 體的數造方法（Method)。 (二)發明背景 爲了增進『金氧半場效電晶體』電路之執行速度（Circuit Performance )，在數 位積體電路技術領域，一種稱爲自動對準矽化物（Self-AlignedSilicide; Salicide)的 製程方法被揭露，現在利用圖一到圖四說明傳統f自動對準矽化物』的製程方法如 下。 · 首先，在砍半導體晶圓10 (Silicon Semiconductor Wafer)上形成一層厚度很 厚的場氧化層（FieldOxide)，作爲隔離『金氧半場效電晶體』之用。接著，形成所 述『金氧半場效電晶體』·之閘氧化層14 (GateOxide)，再接著，形成所述f金氧 半場效電晶體』之複晶砂閛極16A (Polysilicon Gate Electrode)。然後，利用離子 佈値技術（Ion Implantation)來形成ΓΝ·淡摻雜源極/汲極98』（Lightly Doped Source/Drain)、，其離子種類是磷原子（P31 )，其離子佈値劑量介於1E13到3E14 原子/平方公分之間，離子佈値能量則介於20到50 kev之間。然後，沉積一層介電 層99，並利用蝕刻技術垂p：單向性地對所述『介電層99』進行單向性的回蝕刻 (AnisotropicallyEtchback),以在戶斤述『鬧極16A』之兩側形成介電層側壁子99A (Dielectric Spacer )，接著，利用離子佈値技術（Ion Implantation )進行N+濃摻雜 離子佈値，以形成『N+濃摻雜源極/汲極22』（Heavily Doped Source/Drain)， 如圖一所示。 所述【閘極16A】通常是利用磷原子之同步攙雜（PhosphorusIn-SituDoped) 之低壓化學氣相沉積法所形成之複晶矽層（PolysiliconLayer)，其反應氣體是PH3 和SiH4的混合氣體，其反應溫度介於530到580 °C之間，其厚度則介於1500到 4000埃之間。所述【介電層99】通常是利用低壓化學氣相沉積法形成之二氧化矽 (SiliconDioxide ; Si〇2)，其厚度介於1〇〇〇到2500埃之間《所述Γ N+濃摻雜 源極/汲極22』離子佈値之離子種類是砷原子（As%)，其離子佈値劑量介於 1E15到5E16原子/平方公分之間，離子佈値能量則介於20到100 Kev之間。 在作過適當表面淸潔處理後，接著，利用濺鍍技術形成一層鈦金屬28 (Titanium ; Ti)，如圖二所示。然後，進行高溫回火處理』（Anneal)，所述 【高溫回火處理】使所述【鈦金屬28】跟所述【矽半導體晶圓10】表面之矽原子 發生矽化反應（Silicidation)，以在所述【N+濃摻雜源極/汲極22】表面形成一 層『自動對準鈦矽化物30A』（TiSi2)，而在所述【閘極16A】之上表面則形成 【自動對準鈦矽化物30B】，而留下未發生【矽化反應】之鈦金屬28A，如圖三所 示。最後，去除未發生【矽化反應】之所述欽金屬28A』，『自動對準鈦矽化物 2 本紙張尺度適用中國國家搮準（CNS ) A4规格（210X297公釐）Printed by A7 B7, Shellfish Consumer Cooperative, Central Sample Bureau of the Ministry of Economic Affairs V. Description of the Invention (/) (―) Technical Field 纟 The invention discloses a metal-oxygen half-field with "auto-aligned silicide" for integrated circuits Method for making effect transistor. (II) Background of the Invention In order to improve the circuit performance of "metal oxide half field effect transistor" circuits, in the field of digital integrated circuit technology, a process method called Self-Aligned Silicide (Salicide) It has been revealed that the process method of the conventional f auto-aligned silicide ”will now be described using FIGS. 1 to 4 as follows. · First, a thick field oxide layer (FieldOxide) is formed on the Silicon Semiconductor Wafer 10 to isolate the "Gold Oxygen Half Field Effect Transistor". Next, a gate oxide layer 14 (GateOxide) of the "metal oxide half field effect transistor" is formed, and then a polysilicon gate electrode 16A (Polysilicon Gate Electrode) of the f metal oxide half field effect transistor is formed. Then, Ion Implantation is used to form ΓΝ · Lightly Doped Source / Drain 98. The ion species is phosphorus atom (P31). Between 1E13 and 3E14 atoms / cm2, the ion cloth energy is between 20 and 50 kev. Then, a dielectric layer 99 is deposited, and an etching technique is used to p: unidirectionally etch back the "dielectric layer 99" (Anisotropically Etchback) in order to describe "Aluminum 16A" in the household Dielectric Spacer 99A (Dielectric Spacer) is formed on both sides of the dielectric layer, and then N + heavily doped ion cloth is formed by using ion implantation technology (Ion Implantation) to form "N + heavily doped source / drain electrode 22" ( Heavily Doped Source / Drain), as shown in Figure 1. [Gate 16A] is usually a polysilicon layer (PolysiliconLayer) formed by a low-pressure chemical vapor deposition method using Phosphorus In-Situ Doped. The reaction gas is a mixed gas of PH3 and SiH4. The reaction temperature is between 530 and 580 ° C, and its thickness is between 1500 and 4000 Angstroms. The [dielectric layer 99] is usually a silicon dioxide (Silicon Dioxide; SiO2) formed by a low-pressure chemical vapor deposition method, and the thickness is between 1000 and 2500 angstroms. The ion type of the heterosource / drain electrode 22 ″ ion cloth is arsenic (As%). Its ion cloth dose is between 1E15 and 5E16 atoms / cm², and the ion cloth energy is between 20 and 100 Kev. between. After proper surface cleaning is performed, a layer of titanium 28 (Titanium; Ti) is then formed by sputtering technology, as shown in FIG. Then, perform high-temperature tempering treatment (Anneal), the [high-temperature tempering treatment] causes the [titanium metal 28] and the silicon atoms on the surface of the [silicon semiconductor wafer 10] to undergo silicidation (Silicidation) to A layer of "auto-aligned titanium silicide 30A" (TiSi2) is formed on the surface of the [N + heavily doped source / drain 22], and an [auto-aligned titanium] is formed on the surface of the [gate 16A] Silicide 30B], while leaving titanium metal 28A without [silicide reaction], as shown in Figure 3. Finally, remove the Chin metal 28A that has not undergone the [silicidation reaction] "," Automatically align titanium silicide 2 This paper size applies to China National Standard (CNS) A4 specification (210X297 mm)
In tm In i m ml ^^^1 m (請先閲讀背面之注意事項再填寫本頁) 經濟部中央樣隼局負工消费合作社印製 A7 B7 五、發明説明（2 ) 30』於焉完成，如圖四所示。所述『自動對準鈦矽化物30』能大幅提昇改進f金氧 半場效電晶體』電路之執行速度（CircuitPerformance)。 然而，當積體電路元件不斷的縮小，所述【閘極16A】兩側之所述『介電層側 壁子99A』的寬度越來越短，甚至小於〇.1微米’造成所述【鈦金屬28】跟所述 【半導體晶圓1〇】表面之矽原子發生矽化反應（Silicidation)時，矽原子沿著所述 『介電層側壁子99A』的表面擴散，形成11二矽化鈦』（TiSi2) ’容易導致所述 【閘極16A】跟所述【N+濃摻雜源極/汲極22】之間發生漏電現像（Current Leakage),使電路識故障（Short)。 本發明揭露了一種延長閘極跟源極/汲極之間之幾何路徑的方法，可以避免閘 極跟源極/汲極之間的橋接現像，消弭金氧半場效電晶體電路的漏電（Current Leakage)。 (三)發明的簡要說明’ 本發明之主要目的是提供一種無漏電現像之具有^動對準矽化物』之金氧半 場效電晶體的滅造方法。 . 本發明之主要製程方法如下。首先，在矽半導體晶圓上形成場氧化層，作爲隔 離『金氧半場效電晶體』乏用途。接著，形成『金氧半場效電晶體』之閘氧化層 (Gate Oxide )。然後，沉積一層複晶砂層（Polysilicon)和第一介電層（First Dielectric),並利用微影技術和電漿蝕刻技術蝕去所述『第一介電層』和『複晶砂 層』，蝕刻所述『複晶矽層』時，故意側向蝕去一部份的所述『複晶矽層』以在所 述1第一介零層』和*閘氧化層』之間形成空腔（Cavity)，以形成具有T型閘極 結構（T-ShapidGateStructure)之f金氧半場效電晶體』。可以看出，所述ΓΤ型閘 極結構』延長了所述閘極跟源極/汲極之間的幾何路徑。 接著，利用離子佈値技術（IonImplantation)來形成*·Ν·淡摻雜源極/汲極』 (Lightly Doped Source / Drain )。然後，沉積一層第二介電層（Second Dielectric)，並利用電漿蝕刻技術對所述『第二介電層』進行單向性的回蝕刻 (AnisotropicallyEtchback)，以在所述『T型閘極結構』之F空腔表面』形成第二 介電層側壁子（Second Dielectric Spacer)。 接著，去除所述『第一介電層』以在所述『T型閘極結構』的上部形成『凹陷 結構』，自然，所述『凹陷結構』也延長了所述閘極跟源極/汲極之間的幾何路徑 (Geometry Path)。接著，沉積一層鈦金屬（Titanium ; Ti)，然後，進行『高溫回 火處理』，所述『高溫回火處理』使所述『鈦金屬』跟所述『矽半導體晶圓』表面 之矽原子發生矽化反應（Silicidation)，以在所述【N-淡摻雜源極/汲極】表面形 成一層F自動對準鈦矽化物』（TiSi2)，而在所述『複晶矽閘極』之上表面也反應In tm In im ml ^^^ 1 m (Please read the precautions on the back before filling in this page) Printed by A7 B7, the Consumer Cooperatives of the Central Samples Bureau of the Ministry of Economic Affairs. 5. The description of the invention (2) 30. As shown in Figure 4. The "Automatic Alignment Titanium Silicide 30" can greatly improve the circuit execution speed of the circuit. However, when the integrated circuit components are continuously shrinking, the width of the "dielectric layer sidewall 99A" on both sides of the [gate 16A] is getting shorter and shorter, even smaller than 0.1 micron ', causing the [titanium Metal 28] When silicidation occurs with the silicon atoms on the surface of the [semiconductor wafer 10], the silicon atoms diffuse along the surface of the "dielectric layer sidewall 99A" to form 11 titanium silicides "( TiSi2) 'It is easy to cause a current leakage between the [gate 16A] and the [N + heavily doped source / drain 22], so that the circuit recognizes a short. The invention discloses a method for extending the geometric path between a gate and a source / drain, which can avoid a bridge image between the gate and the source / drain, and eliminate the leakage of the metal-oxide half field effect transistor circuit. Leakage). (3) Brief Description of the Invention 'The main object of the present invention is to provide a method for destroying a gold-oxygen half field-effect transistor having a dynamic alignment silicide without leakage phenomenon. The main process method of the present invention is as follows. First, a field oxide layer is formed on a silicon semiconductor wafer, which is used for isolating the "metal oxide half field effect transistor". Next, a gate oxide (Gate Oxide) of a "metal oxide half field effect transistor" is formed. Then, a polysilicon layer and a first dielectric layer are deposited, and the "first dielectric layer" and the "polycrystalline sand layer" are etched away using lithography technology and plasma etching technology, and then etched. When the "multi-crystalline silicon layer" is used, a part of the "multi-crystalline silicon layer" is deliberately etched laterally to form a cavity between the 1st first dielectric layer and the * gate oxide layer. Cavity) to form a f-metal-oxygen half field-effect transistor with a T-ShapidGate Structure. It can be seen that the ΓΤ gate structure ′ extends the geometric path between the gate and the source / drain. Then, Ion Implantation is used to form a lightly doped source / drain. Then, a second dielectric layer (Second Dielectric) is deposited, and the "second dielectric layer" is subjected to unidirectional etch back (Anisotropically Etchback) using a plasma etching technique, so that the "T-gate" The "F cavity surface" of the structure forms a second dielectric layer (Second Dielectric Spacer). Next, the "first dielectric layer" is removed to form a "depression structure" on the upper part of the "T-gate structure". Naturally, the "depression structure" also extends the gate and source / Geometry Path between drains. Next, a layer of titanium metal (Titanium; Ti) is deposited, and then a "high-temperature tempering treatment" is performed, which makes the "titanium metal" and silicon atoms on the surface of the "silicon semiconductor wafer" A silicidation reaction occurs to form a layer of F-automatically aligned titanium silicide (TiSi2) on the surface of the [N-lightly doped source / drain], and in the "multi-crystalline silicon gate" Upper surface also reacts
A 本纸張尺度適用中國B家揉牟（CNS ) A4规格（2丨0X297公釐） n n^i 1^1 m nn till 1-^1 UK f flu· nn i tn TJ ^i (請先聞讀背面之注意事項再填寫本頁) 經濟部中央猱车局貝工消费合作社5-«. A7 B7 五、發明説明（3 ) 形成『自動對準鈦矽化物』，在所述『第二介電層側壁子』則留下未發生『矽化反 應』之鈦金屬，然後，去除未發生『矽化反應』之所述『欽金屬』。 最後，利用離子佈値技術進行N+濃慘雜離子佈値，以形成『N+濃摻雜源 極/汲極』（Heavily Doped Source/Drain)，具有『自動對準砂化物』之金氧半場 效電晶體於焉完成。 本發明之『T型閘極結構』和『凹陷結構』延長了所述閘極跟源極/汲極之間 的幾何路徑（Geometry Path)，因此，可以避免閘極跟源極/汲極之間的橋接現 像，消弭金氧半場效電晶體電路的漏電（CurrentLeakage)。 (四) 圖示的簡要說明 圖一到圖四是『N通道金氧半場效電晶體』之『自動對準矽化物』之先前技藝的製 程橫截面示意圖，其中，98是『N·淡摻雜源極/汲極』，99A是介電層側壁子 (Dielectric Spacer )。 圖五到圖十五是本發明之實施例的製程橫截面示意圖（Process Cross Section)。 (五) 發明的詳細說明 本發明之製程橫截面示意圖只畫出N通道金氧半場效電晶體（N-Channel Metal Oxide Semiconductor Field Effect Transistor ; NMOSFET)，省略【P 通道金 氧半場效電晶體】結構，並且，此製程可自然延伸到與互補式金氧半場效電晶體 (Complementary Metal Oxide Semiconductor Field Effect Transistor ; CMOSFET )製 程相結合。 參考圖五。首先，以傳統製程在晶格方向（100)的p型矽半導體晶圓ίο (Silicon Semiconductor Wafer)表面形成隔離電性活動區（Active Area)所需要的 場氧化層12，所述『場氧化層12』（Field Oxide)之厚度介於3000埃到6000 埃之間，作爲隔離所述『N通道金氧半場效電晶體』之用。接著，在高溫環境中加 熱氧化（Thermal Oxidized)所述【P型矽半導體晶圓10】之表面以形成所述 【金氧半場效電晶體】之閘氧化層14 (Gate Oxide)，其厚度介於80到200埃 之間。然後，沉積一層複晶砂層16 (Polysilicon)和第一介電層18 (First Dielectric)，並利用微景多技術和電漿蝕亥!j技術（Lithography and Etching)餓去所述 『第一介電層18』和『複晶矽層16』。所述『複晶矽層16』是利用『低壓化學 氣相沉積法』形成，反應氣體是PH3和SiH4的混合氣體，其反應溫度介於525 到575 °C之間，其厚度介於1500到3500埃之間。所述『第一介電層18』通 常是利用低壓化學氣相沉積法（Low Pressure Chemical Vapor Deposition ; LPCVD ) 形成之氮化矽層（Silicon Nitride)，其反應氣體是SiCl2H2和NH3 ,其厚度介於800 到2000埃之間。 對所述『第一介電層18』之【電漿蝕刻】可以利用磁場增強式活性離子式電 _4 本紙张尺皮適用中Η因家樣丰（CNS )人4規_格（2丨Ox297公疫） —^1 d I I , —裝 —— — — —訂— — —— — · 银 (請先HV讀背面之注$項再填寫本頁) 經濟部中央搮车局貝工消费合作社印裝 A7 B7 五、發明説明（斗） 策倉虫刻（Magnetic Enhanced Reactive Ion Etching ; MERIE)或電子迴旋共振電獎餘 刻（Electron Cyclotron Resonance ; ECR )或傳統的活性離子式電漿蝕刻技術 (Reactive Ion Etching ; RIE),在次微米積體電路技術領域’通常是利用『磁場增 強式活性離子式電槳蝕刻技術』，其電漿反應氣體一般是CF4、CHF3和Ar等 氣體。對所述『複晶矽層16』之單向性的電漿蝕刻則是利用磁場增強式活性離子 式電漿蝕刻或電子迴旋共振電漿蝕刻或傳統的活性離子式電漿蝕刻技術，在次微米 積體電路技術領域，通常是利用『磁場增強式活性離子式電漿蝕刻技術』，其電漿 反應氣體一般是Cl2和HBr等氣體。 現在參考圖六。接著，故意側向蝕去一部份的所述『複晶矽層16』以成爲 『複晶矽層16A』’以在所述『第一介電層18』和『閘氧化層14』之間形成空腔 19 (Cavity)，以形成具有T型閘極結構（T-Shaped Gate Structure)之『金氧半 場效電晶體』，如圖六所示。可以看出，所述由『第一介電層18』和『複晶矽層 16A』構成之『T型閘極結構』延長了所述閘極上表面（Top Surface)跟源極/汲 極之間的幾何路徑。 接著，利用離子佈値技術（Ion Implantation)來形成『N·淡摻雜源極/汲極 98』（Lightly Doped Source/Drain)參考圖七，其離子種類是憐原子（P31)，其 離子佈値劑量介於1E13到3E14原子/平方公分之間，離子佈値能量則介於20 到50 kev之間。 現在參考圖八。然後，沉積一層第二介電層24 (Second Dielectric)，並形成 空腔25 (Cavity)，再利用電漿蝕刻技術對所述『第二介電層24』進行單向性的 回餓刻（Anisotropically Etchback)，以在所述『T型聞極結構』之『空腔19之 表面』形成第二介電層側壁子24A (Second Dielectric Spacer) ’如圖九所示。 所述『第二介電層24』通常是利用低壓化學氣相沉積法（Low Pressure Chemical Vapor Deposition ; LPCVD)形成之二氧化砂（Silicon Dioxide)，其反應 氣體是四乙基矽酸鹽（TetraEthOxySilane ; TEOS)，其厚度介於300到Π00埃 之間。對所述F第二介電層24』之『電漿蝕刻』可以利用『磁場增強式活性離子 式電漿蝕刻』或『電子迴旋共振電漿蝕刻』或傳統的『活性離子式電漿蝕刻技 術』’在次微米積體電路技術領域’通常是利用『磁場增強式活性離子式電漿蝕刻 技術』，其電漿反應氣體一般是CF4、CHF3和Ar等氣體。 接著，利用熱磷酸溶液去除所述『第一介電層18』，以在所述『T型閘極結 構』的上部形成『凹陷結構27』’如圖十所示。，自然，所述『凹陷結構27』也 延長了所述閘極16A之上表面（Top Surface)跟『N-淡摻雜源極/汲極98』之 間的幾何路徑（Geometry Path)。所述『凹陷結構27』延長了所述『閘極16A之 上表面』跟『N_淡摻雜源極/汲極98』之間的幾何距離，故消强了所述『複晶砂 閘極16A』跟『N-淡摻雜源極/汲極98』之間的漏電現像（CurrentLeakage)。 5 本紙用中田國家^牟（CNS ) 格（2丨0X297公ifj --------ί'_裝------訂------線 (請先Μ讀背面之注$項再填寫本頁) 經洗部中夫搮车局貝工消费合作社印輦. A7 B7 五、發明说明（s ) _ 接著，利用濺鍍技術沉積一層鈦金屬28 (Titanium)，如圖十一所示。然 後，在爐管中進行『高溫回火處理』（Furnace Anneal)，所述【高溫回火處理】 使所述【鈦金屬28】跟所述『矽半導體晶圓10』表面之矽原子發生矽化反應 (Silicidation)，以在所述『矽半導體晶圓10』表面形成一層『自動對準鈦矽化物 30A』（TiSi2)，而在所述『複晶矽閘極16A』之上表面則反應形成【自動對準鈦 矽化物30B】，使所述『複晶矽閘極16A』成爲『複晶矽閘極16B』，而在所述 『第二介電層側壁子24A』表面則留下未發生『矽化反應』之鈦金屬28A，如圖 十二所示。通常，所述『高溫回火處理』之爐管溫度介於650°C到750°C之間’ 另一方面，所述『高溫回火處理』也可以利用『快速熱回火技術』（Rapid ThermalA This paper size is applicable to China ’s B family (CNS) A4 size (2 丨 0X297 mm) nn ^ i 1 ^ 1 m nn till 1- ^ 1 UK f flu · nn i tn TJ ^ i (Please read first (Please read the notes on the back and fill in this page again)) 5- «. A7 B7, Central Coach Bureau of the Ministry of Economic Affairs, A7 B7 V. Description of the invention (3) Form" Automatically align titanium silicide ". The "electrical layer side wall" leaves the titanium metal that has not undergone the "silicidation reaction", and then the "chin metal" that has not undergone the "silicidation reaction" is removed. Finally, N + dense miscellaneous ions were fabricated using ion cloth technology to form "Heavily Doped Source / Drain", which has a gold-oxygen half-field effect of "automatically aligned sands". The transistor was completed in 焉. The "T-gate structure" and the "depression structure" of the present invention extend the Geometry Path between the gate and the source / drain, so that the gate and the source / drain can be avoided. The phenomenon of bridging in between eliminates the current leakage of the metal oxide half field effect transistor circuit (CurrentLeakage). (IV) Brief description of the diagrams Figures 1-4 are cross-sectional schematic diagrams of the previous process of the "auto-aligned silicide" of "N-channel metal-oxide half-field-effect transistor", of which 98 is "N · Light doped "Hybrid / Drain", 99A is a dielectric spacer (Dielectric Spacer). 5 to 15 are schematic diagrams of a process cross section of a process according to an embodiment of the present invention. (5) Detailed description of the invention The cross-sectional schematic diagram of the process of the present invention only draws N-channel metal oxide semiconductor field effect transistor (NMOSFET), omitting [P channel metal oxide half field effect transistor] Structure, and this process can be naturally extended to be combined with a complementary metal oxide semiconductor field effect transistor (CMOSFET) process. Refer to Figure 5. First, a conventional process is used to form a field oxide layer 12 on the surface of a p-type silicon semiconductor wafer (100) in the lattice direction (Silicon Semiconductor Wafer). The field oxide layer 12 is needed to isolate the active area. 12 "(Field Oxide) has a thickness between 3000 Angstroms and 6000 Angstroms, and is used to isolate the" N-channel metal-oxygen half field effect transistor ". Next, the surface of the [P-type silicon semiconductor wafer 10] is thermally oxidized in a high-temperature environment to form the gate oxide layer 14 (Gate Oxide) of the [gold-oxygen half field effect transistor]. Between 80 and 200 angstroms. Then, deposit a polysilicon layer 16 (Polysilicon) and a first dielectric layer 18 (First Dielectric), and use the micro-view multi-technology and plasma etching technology (Lithography and Etching) to starve the "first media "Electric layer 18" and "Multi-crystalline silicon layer 16". The "polycrystalline silicon layer 16" is formed by using "low pressure chemical vapor deposition". The reaction gas is a mixed gas of PH3 and SiH4. Its reaction temperature is between 525 and 575 ° C and its thickness is between 1500 and 1500. Between 3500 Angstroms. The "first dielectric layer 18" is usually a silicon nitride layer (Silicon Nitride) formed by using a Low Pressure Chemical Vapor Deposition (LPCVD) method. The reaction gases are SiCl2H2 and NH3. Between 800 and 2000 Angstroms. For the [plasma etching] of the "first dielectric layer 18", a magnetic field-enhanced active ion-type electricity can be used._4 This paper ruler is applicable to the 4 rules of the Chinese family (CNS) _ grid (2 丨Ox297 public epidemic) — ^ 1 d II, —loading — — — — order — — — — · · Silver (please read H $ on the back of the HV before filling this page) Printed A7 B7 5. Description of the Invention (Battle) Magnetic Enhanced Reactive Ion Etching (MERIE) or Electron Cyclotron Resonance (ECR) or traditional reactive ion plasma etching technology (ECR) Reactive Ion Etching; RIE), in the field of sub-micron integrated circuit technology, usually uses the "magnetic field-enhanced active ion paddle etching technology", and the plasma reaction gas is generally CF4, CHF3, and Ar gas. The unidirectional plasma etching of the "multi-crystalline silicon layer 16" is using magnetic field enhanced active ion plasma etching or electron cyclotron resonance plasma etching or traditional active ion plasma etching technology. In the field of micro-integrated circuit technology, "field-enhanced active ion plasma etching technology" is usually used, and the plasma reaction gas is generally Cl2 and HBr. Reference is now made to FIG. Then, a portion of the "multicrystalline silicon layer 16" is intentionally etched laterally to become a "multicrystalline silicon layer 16A" 'in the "first dielectric layer 18" and the "gate oxide layer 14" Cavity 19 is formed in between to form a "metal oxide half field effect transistor" with a T-Shaped Gate Structure, as shown in Figure 6. It can be seen that the "T-gate structure" composed of "the first dielectric layer 18" and the "polycrystalline silicon layer 16A" extends the top surface of the gate and the source / drain. Geometric path. Next, Ion Implantation was used to form "N · lightly doped source / drain 98" (see Figure 7). Its ion type is a pity atom (P31). The tritium dose is between 1E13 and 3E14 atoms / cm2, and the ion cloth energy is between 20 and 50 kev. Reference is now made to FIG. Then, a second dielectric layer 24 (Second Dielectric) is deposited, and a cavity 25 (Cavity) is formed, and then the "second dielectric layer 24" is unidirectionally etched back using plasma etching technology ( Anisotropically Etchback), to form a second dielectric layer side wall 24A (Second Dielectric Spacer) on the "surface of the cavity 19" of the "T-shaped odor structure" as shown in FIG. The "second dielectric layer 24" is usually a silicon dioxide (Silicon Dioxide) formed by a Low Pressure Chemical Vapor Deposition (LPCVD) method, and the reaction gas is TetraEthOxySilane. TEOS), with a thickness between 300 and Π00 Angstroms. The "plasma etching" of the "F second dielectric layer 24" can use "magnetic field enhanced active ion plasma etching" or "electron cyclotron resonance plasma etching" or the traditional "active ion plasma etching technology" "In the field of sub-micron integrated circuit technology", "field-enhanced active ion plasma etching technology" is commonly used, and the plasma reaction gas is generally CF4, CHF3, Ar and other gases. Next, the "first dielectric layer 18" is removed using a hot phosphoric acid solution to form a "depression structure 27" on the upper portion of the "T-shaped gate structure" as shown in Fig. 10. Naturally, the "depression structure 27" also extends the geometric path between the top surface of the gate 16A and the "N-lightly doped source / drain 98". The "depression structure 27" prolongs the geometric distance between the "surface above the gate 16A" and the "N_lightly doped source / drain 98", thereby weakening the "composite sand gate" Current Leakage between "Pole 16A" and "N-Lightly Doped Source / Drain 98". 5 This paper uses the Zhongtian National ^ Mou (CNS) grid (2 丨 0X297 male ifj -------- ί'_install ------ order ------ line (please read the first Note: Please fill in this page again.) Printed by the Shibuya Automobile Co., Ltd. Shellfish Consumer Cooperative in the Ministry of Washing. A7 B7 V. Description of Invention (s) _ Next, a layer of titanium 28 (Titanium) is deposited by sputtering technology, as shown in the figure. Eleven. Then, "Furnace Anneal" is performed in the furnace tube, and the "High Temperature Tempering Treatment" makes the "Titanium Metal 28" and the "Silicon Semiconductor Wafer 10" surface The silicon atom undergoes a silicidation reaction to form a layer of "Automatically Aligned Titanium Silicide 30A" (TiSi2) on the "Silicon Semiconductor Wafer 10" surface, and the "Silicon Gate 16A" The upper surface reacts to form [auto-aligned titanium silicide 30B], so that the "multi-crystalline silicon gate 16A" becomes a "multi-crystalline silicon gate 16B", and the "second dielectric layer sidewall 24A" On the surface, 28A titanium metal without "silicidation reaction" is left, as shown in Fig. 12. Generally, the furnace temperature of the "high temperature tempering treatment" is between 650 ° C and 750 ° C. Between 'the other hand, the "high-temperature tempering" may also use the "rapid thermal annealing technique" (Rapid Thermal
Anneal ; RTA)來完成。此時透過事先實驗或模擬計算結果可控制『N-淡摻雜源 極/汲極98』因高溫回火產生的橫向熱擴散效應，使得『N-淡摻雜源極/汲極98』 的邊緣擴大達『複晶矽閛極16B』下方以形成完整之結構，如圖十二所示。 接著，利用化學溶液去除未發生『矽化反應』之所述『鈦金屬28Α』，如圖 十三所示。接著，利用離子佈値技術進行Ν+濃摻雜離子佈値，以形成金氧半場 效電晶體之『Ν+濃摻雜源極/汲極22』（Heavily Doped Source/Drain)，如圖 十三所示。所述『N+濃摻雜源極/汲極22』之離子佈値之離子種類是砷原子 (AS75)，其離子佈値劑量介於丨E15到5Ei6原子/平方公分之間，離子佈値能 量貝(I介於40到120 Kev之間。 接著，沈積一層第三介電層32 (Third Dielectric)，並利用微影技術和電漿 蝕刻技術蝕去所述『第三介電層32』以形成接觸窗33 (Contact Hole)，如圖十 四所示。所述『第三介電層32』通常是利用大氣壓化學氣相沉積法（Atmosphere Pressure Chemical Vapor Deposition ; APCVD)形成之硼磷攙雜二氧化砂膜 (BoroPhosphoSilicateGlass ; BPSG)或磷攙雜二氧化砂膜（PhosphoSilicate Glass ; PSG)，其厚度介於4000到10000埃之間。 最後，形成一層金屬層34並利用微影技術和電漿蝕刻技術蝕去所述『金屬 層34』以形成金屬連線34 (Metal Interconnection),如圖十五所示，一種無橋接 (Bridge-Free)、無漏電（Current Leakage)之具有『自動對準砂化物』之金氧半 場效電晶體於焉完成。所述『金屬層34』通常是由駄（Titanium)、氮化欽 (Titanium Nitride )和錦合金（Aluminum Alloy )組成之複層結構。 以上係以最佳實施例來闡述本發明，而非限制本發明，並且，熟知半導體技藝 之人士皆能明瞭，適當而作些微的改變及調整，仍將不失本發明之要義所在，亦不 脫離本發明之精神和範圍。 6 本Λ張只Jit逍用中®®家搮牟（CNS > A4*L格（2丨0X297公釐） i I ---..——^----------- .裝------订------银 (請先Mtt背面之注$項存填¾本茛)Anneal; RTA). At this time, the lateral thermal diffusion effect of "N-lightly doped source / drain 98" due to high temperature tempering can be controlled through prior experiments or simulation calculation results. The edge is enlarged to the bottom of the "polycrystalline silicon electrode 16B" to form a complete structure, as shown in Figure 12. Next, the chemical solution is used to remove the "titanium metal 28A" that has not undergone the "silicidation reaction", as shown in Fig. 13. Next, N + heavily doped ion cloth is formed by using ion cloth technology to form a "Heavily Doped Source / Drain" of a gold-oxygen half field effect transistor, as shown in Figure 10. Three shown. The ion type of the ionic cloth of the "N + doped source / drain electrode 22" is arsenic atom (AS75), and the ionic cloth dose is between E15 and 5Ei6 atoms / cm2, and the ion cloth energy (I is between 40 and 120 Kev. Then, a third dielectric layer 32 (Third Dielectric) is deposited, and the "third dielectric layer 32" is etched away using lithography technology and plasma etching technology. A contact hole 33 is formed, as shown in Fig. 14. The "third dielectric layer 32" is usually a boron-phosphorus dopant II formed by using atmospheric pressure chemical vapor deposition (APCVD). An oxide sand film (BoroPhosphoSilicateGlass; BPSG) or a phosphorus doped sand oxide film (PhosphoSilicate Glass; PSG) with a thickness between 4000 and 10,000 Angstroms. Finally, a metal layer 34 is formed and lithography and plasma etching techniques are used. The "metal layer 34" is etched to form a metal interconnection 34 (Metal Interconnection). As shown in Fig. 15, a bridge-free and current leak-free device with "automatically aligned sanding material" Oxyhalf effect The crystal is completed in rhenium. The "metal layer 34" is usually a multi-layered structure composed of Titanium, Titanium Nitride, and Aluminum Alloy. The above description is based on the preferred embodiment. Invention, rather than limiting the invention, and those skilled in the art of semiconductors will be able to understand that appropriate changes and adjustments will still not lose the essence of the invention, nor depart from the spirit and scope of the invention. Λ Zhang only Jit Free use ® ® furniture (CNS > A4 * L grid (2 丨 0X297 mm) i I ---..—— ^ -----------. ------ Order ------ Silver (please deposit ¾ of this butternut on the back of Mtt)