經濟部中央橾準扃負工消費合作社印装 316334 A7 B7 五、發明説明（） 1. 發明之技術領域 本發明是關於積體電路之快閃可擦拭/可程式唯讀記憶體（flashEPROM)的製. 造方法，特S隄關於具有大表面積之(floatinggate)和高麵|含由例（high Gate Coupling Ratio ; high GCR).之快閃可癀拭/可程式記憶體的製一 ' 2. 發明背景 隨著微影技術和電漿蝕刻技術的快速進步，積體電路元件不斷縮小以達到高積 集密度的目的，例如，今天的電漿蝕刻技術已經可以形成非常完美之0.35微米的線 條。但積體電路元件不斷縮小時，必需兼顧其它因素，使得在稹體電路元件縮小 時，仍然可以維持電路表現（circuitperformance)。 以快閃可擦拭/可程式唯讀記憶體爲例，要達到快閃可擦拭/可程式唯讀記憶體 之髙集積密度的目的而縮小記憶元尺寸時，其閘藕合比例（Gate Coupling Ratio ; GCR)亦隨之降低，但這將造成記憶元進行擦拭或程式時所禱芝孺昇，菝务化 了電路表現（degradecirrcuitperformance)。 本發明揭露了一種形成具有較大的表面積之懸浮閘極的方法，由於，閘藕合比 例（Gate Coupling Ratio ; GCR)等於複晶矽間介電層的面積除以隧穿氧化層的面 稹，因此，具有較大的表面積之懸浮閘極能增加複晶矽間介電層的表面稹，因此增 加了閘藕合比例，故能提昇電路表現，並達到髙積集密度的快閃可擦拭/可程式唯讀 記憶體之目的。 3. 發明之簡要說明 本發明的主要目的是提供一種具有大的表面積之懸浮閘極（floatinggate)之快 閃記憶體的製造方法。 本發明的另一個目的是提供一種具有高閘藕合比例（high Gate Coupling Ratio ; high GCR)之快閃記憶體的製造方法。 本發明的再一個目的是提供一種具有高密度和高電路表現之快閃記憶體的製造 方法。 茲簡述本發明之主要方法如下。首先，利用傳統淺凹槽隔離技術（Shallow Trench Isolation ; STI)在矽半導體基板上形成隔離電晶體所需的厚氧化層。接著， 形成一層第一介電層，再利用微影技術在預備作爲懸浮閘極（floating gate)之位置 形成光阻圓案和第一光阻開口。 2 本紙張尺度適用中國國家樣準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注^^項再填寫本頁) 裝. 316334 A7 B7 五、發明説明（） ， 接著，在電漿蝕刻反應室內形成非揮發性的有機高分子（non-volatile organic polymer)。然後，利用電漿蝕刻技術蝕亥彳所述第一介電層，以形成第一凹溝，所述 第一凹溝之寬度小於微影解析極限。接著，在所述第一凹溝內形成隧穿氧化層 (tunnel oxide)。然後，沈積一層第一複晶砂。 接著，形成一層複晶砂間介電層（inter-polysi dielectric )，所述複晶砂間介電層 沒有塡滿所述第一凹溝，而形成間隙。然後，形成一層第二複晶矽，所述第二複晶 矽塡滿所述間隙。接著，利用化學機械式琢磨技術（Chemical Mechanical Polishing ; CMP)對所述第二複晶矽、複晶矽間介電層、第一複晶矽和第一介電層進行琢磨處 理，所述琢磨處理掉了一小部份的所述第一介電層。所述琢磨處理結束後，所述第 一凹溝以外之所述第二複晶矽、複晶矽間介電層和第一複晶矽被去除。最後，利用 稀釋氫氟酸去除所述第一介電層，以露出所述複晶矽、複晶矽間介電層和第一複晶 砂，以形成懸浮閘極（floatinggate)和控制閘極（controlledgate)。最後，以標準 技術形成源極/汲極，一種具有髙密度和高電路表現之快閃可擦拭/可程式唯讀記憶 體於焉完成。 4.圖示的簡要說明 圖一到圖十二是本發明之實施例的製程剖面示意圖。 圖一是在矽半導體基板上形成一層第一介電層後的製程剖面示意圖； 圖二是利用微影技術形成光阻圖案和第一光阻開口後的製程剖面示意圖； 圖三是形成非揮發性的有機高分子（non-volatile organic polymer)後的製程剖面示 惠圖， 圖四是利用電漿蝕刻技術蝕刻所述第一介電層，以形成第一凹溝後的製程剖面示意 I ρ ί 圖， 圖五是去除所述光阻圖案和非揮發性的有機髙分子側壁物後的製程剖面示意圖； 圖六是在所述第一凹溝內形成隧穿氧化層後的製程剖面示意圖； 圖七是沈積一層第一複晶矽後的製程剖面示意圖； 經濟部中央樣準局貝工消费合作社印策 (請先閱讀背面之注意事項再填寫本頁) 圖八是形成一層複晶砂間介電層（inter-poiysidielectric)，所述複晶砂間介電層沒 有塡滿所述第一凹溝·，而形成間隙後的製程剖面示意圖。 圖九是形成一層第二複晶矽後的製程剖面示意圖，所述第二複晶矽塡滿所述間隙； 圖十是去除所述第一凹溝以外之所述第二複晶矽、複晶矽間介電層和第一複晶砂 後的製程剖面示意圖；. 圖十I是去除所述第一介電層後的製程剖面示意圖； 圖十二是形成N+源極/汲極後的製程剖面示意圖。 3 本紙浪尺度逍用中國國家椟準（CNS )八4说格（210X297公釐） S16334 經濟部中央搮準局員工消費合作社印裝 A7 B7 五、發明説明（） 5.發明之詳細說明 首先，利用傳統淺凹槽隔離技術（Shallow Trench Isolation ; STI)在電阻値約 2.5 ohm-cm、晶格方位（100 )的p型砂半導體基板上loo形成隔離n通道金氧半 場效電晶體所需的厚氧化層（thick oxide )，所述厚氧化層之厚度介於3000埃到 8000埃之間，所述厚氧化層未顯示於圖示。除了利用淺凹槽隔離技術形成厚氧化層 以外，也可以利用習知的局部砂氧化技術形成(LOCOS)形成厚氧化層，只是利用 淺凹槽隔離技術形成之厚氧化層提供了比較平坦的地形地勢。 現在請參考圖一與圖二。接著，形成一層第一介電層110，如圖一所示，再利 用微影技術在預備作爲懸浮閘極（floatinggate)之位置形成光阻圖案112和第一光 阻開口 113，如圖二所示。 •所述第一介電層110可以是利用低壓化學氣相沉積法形成之攙雜的或無攙雜 的二氧化矽，其反應氣體是SiH4與02，反應溫度介於650到800 °C之間，反應壓 力介於0.2到0.4 torr之間，厚度介於3000到8000埃之間。也可以是利用大氣壓 化學氣相沉積法（APCVD)或次大氣壓化學氣相沉積法（SACVD)形成之硼磷摻雜 的二氧化矽膜（BPSG)或磷摻雜的二氧化矽膜（PSG)，其反應氣體是TMB與 TMP，其厚度介於3000到8000埃之間。所述光阻圖案112是正光阻，其厚度介 於8000到12〇00埃之間。第一光阻開口 113之寬度介於0.2到0.5微米之間，視 步進機之微影解析極限而定。 ， 現在請參考圖三、圖四與圖五。接著，在介電層電漿蝕刻反應室內形成非揮發 性的有機髙分子 114 (non-volatile organic polymer)，如圖 三所示。然後，利用磁場 增強式活性離子式電漿蝕刻技術蝕刻所述第一介電層11.0，以形成第一凹溝116， 如%四所示。請特別注意，所述第一凹溝116之寬度第一光阻開口 113 ,亦 即，V所述第一凹溝116之寬度小於微影解析極限。在蝕刻所述第一介電層110過程 裡會形成非揮發性的有機高分子側壁物115 (sidewall spacer)，所述非揮發性的有 機高分子側壁物115窄化了所述第一光阻開口 113。另外，在形成所述「非揮發性 的有機髙分子114」時，需在介.電層電漿蝕刻反應室內增加三氟氫化碳或四氟化碳 氣體的流量。接著，利用氧氣電漿、硫酸和稀釋氫氟酸去除所述光阻圖案112和非 揮發性的有機高分子側壁物115.後，如圖五所示》 對所述第一介電層110之電漿蝕刻以形成所述第一凹溝116，可以利用磁場 增強式活性離子式電漿蝕刻技術（MERIE)或電子迴旋共振電漿蝕刻技術（ECR) 或傳統的活性離子式電漿蝕刻技術（RIE)，而通常是利用磁場增強式活性離子式電 本紙張尺度逍用中國國家樣準（CN§ > A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝· 訂 經濟部中央樣準局貝工消费合作社印製 A7 B7 五、發明説明（） ： 漿蝕刻技術，其電漿反應氣體是三氟氫化碳和氣氣’例如’日本電氣公司（TEL)所 製造型號TEL8500之餓刻機或美國應用材料公司（appliedmaterials)所製造型號 PR5000E之蝕刻機，其蝕刻原理均屬於磁場增強式活性離子式電漿蝕刻技術，能提 供效果相當理想的蝕刻均勻度’對所述P型矽半導體基板上1〇〇之触刻選擇率也非 常高，是商業化的触刻設備。另外’形成所述第一光阻開口 Π3之微影光所述光阻 圖案112是傳統形成N通道金氧半場效電晶體之懸浮閘極的逆圖案（reversed-tone pattern) 〇 現在請參考圖六與圖七。接著，在所述第一凹溝116內形成隧穿氧化層1 丄8 (tunneloxide)，如圖六所示。所述隧穿氧化層118是在乾氧的高溫環境中熱氧化 所述P型矽半導體基板上1〇〇之表面之矽原子而形成，其氧化溫度介於8ip到？ 1000 °C之間，其厚度介於50到200埃之間。然後，沈積一層第一複晶矽120， 如圖七所示。所述第一複晶矽120通常是利用同步磷原子攙雜之低壓化學氣相沉積 法形成，其反應氣體是PH3、SiH4與N2或AsH3、SiH4與N2的混合氣體，反應 溫度介於500到050 °C之間，其厚度介於1〇〇〇到3000埃之間，其雜質離子濃度介 於1E20到1E21原子/立方公分之間，而較佳的濃度是5E20原子/立方公分。請注 意，在沈積所述第一複晶矽120之H或之捧，可視必要性而利用離无^植技術在所 述第一凹溝116內進行通道摻雜，以形成淡摻雜區域，以調整所述N通道金氧半場 效電晶體之臨界電壓（threshold voltage)，通常，所述通道摻雜離子佈植，其離子 常是禪 現在請參考圖八與圖九。接著，形成一層複晶砂間介電層ip ( inter-polysi dielectric)，所述複晶矽間介電層122沒有塡滿所述第一凹溝116^而形成間隙 123，如圖八所示。然後，形成一層第二複晶矽124，所述第二複晶矽124塡滿所述 間隙123，如圖九所示。 所述複晶矽間介電層122之厚度介於50到200埃之間。所述第二複晶矽 124也是利用同步磷原子攙雜之低壓化學氣相沉積法形成，其反應氣體是三氫化磷 與矽甲烷的混合氣體，反應溫度介於500到600 °C之間，其厚度介於1000到3000 埃之間’以能塡滿所述間隙123.作爲考慮，其雜質原子濃度介於1E20到1E21原子 /立方公分之間，比較恰當的數値是5E20原子/立方公分。另外，除了利用同步磷 原子攙雜之低壓化學氣相沉積法形成所述第二複晶矽124外，也可以利用離子佈植 技術攙雜所述第二複晶矽124使具導電性》 現在請參考圖十與圖^。接著，利用化學機械式琢磨技術（Chemical Mechanical Polishing ; CMP)對所述第二複晶矽124、複晶矽間介電層122、第一複 ._ 5 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐） (锖先閲讀背面之注意事項再填寫本頁) 裝. -·訂 經濟部中央樣準局員工消費合作社印製 A7 B7 五、發明説明（） 晶矽120和第一介電層110進行琢磨處理，所述琢磨處理掉了一小部份的所述第一 介電層110，如圖十所示。所述琢磨處理結束後，所述第一凹溝116以外之所述第 二複晶矽124、複晶矽間介電層122和第一複晶矽120被去除，分別剩餘第二複晶 矽124a、複晶矽間介電層122a和第一複晶矽120a，所述第一介電層110也被去除 掉一部份成爲第一介電層ll〇a，而所述複晶矽124a、複晶矽間介電層122a和第一 複晶矽120a被埋在所述第一凹溝116內、最後，利用稀釋氫氟酸去除所述第一介 電層ll〇a，以露出所述複晶矽124a、複晶矽間介電層122a和第一複晶矽120a， 必以形成懸浮閘極120a (floatinggate)和控制閘極124a (controlledg§ip)，如圖*— 1 «ι.—'"··*· 1 "I I _ - . - m >' - 1 " " 所示。 請注意，_轉含比例（Gate CQypUngRatio ; QCBji等於複晶砂間介電層122a 的面積除以所述隧SiS層118的g稹，因此，所述懸浮閘極120a具有比傳統較 大的表面積，故增加了所述複晶砂k介電層122a的面積，因此增加了閘藕合比 例，降低擦拭或每式時所需之偏霉，提昇了電路表現。 現在請參考圖十二。完成所述控制閘極124a後，接著，以標準技術形成N+ 源極/汲極126，一種具有高密度和髙電路表現之快閃可擦拭/可程式唯讀記憶體終 於完成，如圖十二所示。通常，所述N+源極/汲極126之離子佈植之離子種類是 砷原子，其離子佈植劑量介於1E15到5E16原子/平方公分之間，離子佈植能童則 介於30到100 Kev之間。 完成所述N+源極/汲極126的製造後，可以利用標準製程形成接觸窗、第 —金屬連線、介層孔和第二金屬連線，以形成N通道金氧半場效電晶體稹體電路。 所述第一金屬連線通常是以鈦、氮化鈦、鎢和鋁合金爲材料1並且，所述第一金屬 連線跨過所述接觸窗跟所述金氧半場效電晶體之源極/汲極作電性接觸。所述第二 金屬連線通常也是以鈦、氮化鈦、鎢和鋁合金爲材料，並且，第二金屬連線跨過所 述介層孔跟所述第一金屬連線作電性接觸。本發明之方法也能應用於雙層金屬連線 製程以上的多層金屬連線製程積體電路。 以上係利用最佳實施例來闡述本發明，而非限制本發明，並且，熟知半導體技 藝之人士皆能明瞭，適當而作^微的改變及調整，仍將不失本發明之要義所在，亦 不脫離本發明之精神和範圍。 6 本紙張尺度適用中國國家梂率（CNS)A4規格（210X297公釐） (請先S讀背面之注^^項再填寫本頁) 裝· 卜打Printed 316334 A7 B7 by the Central Ministry of Economic Affairs Consumer Cooperatives V. Description of the invention () 1. Technical Field of the Invention The present invention relates to flash erasable / programmable read-only memory (flashEPROM) of integrated circuits Manufacturing method, special S bank on the large surface area (floatinggate) and high surface | Containing examples (high Gate Coupling Ratio; high GCR). The flash flash can be wiped / programmable memory system one 2. BACKGROUND OF THE INVENTION With the rapid progress of lithography technology and plasma etching technology, integrated circuit components are continuously shrinking to achieve the purpose of high accumulation density. For example, today's plasma etching technology can form very perfect 0.35 micron lines. However, as the integrated circuit components continue to shrink, other factors must be taken into account, so that when the small circuit components shrink, the circuit performance can still be maintained. Taking flash erasable / programmable read-only memory as an example, to reduce the size of the memory cell in order to achieve the purpose of high accumulation density of flash erasable / programmable read-only memory, its gate coupling ratio (Gate Coupling Ratio ; GCR) is also reduced, but this will cause the memory cells to be erased or erased during programming, which will degrade the circuit performance (degradecirrcuitperformance). The present invention discloses a method of forming a floating gate with a large surface area, because the gate coupling ratio (Gate Coupling Ratio; GCR) is equal to the area of the intercrystalline silicon dielectric layer divided by the surface of the tunnel oxide layer Therefore, a floating gate with a larger surface area can increase the surface pitch of the dielectric layer between polycrystalline silicon, thus increasing the gate coupling ratio, so it can improve the circuit performance and achieve the flashing density of the flash accumulation density. / Programmable read-only memory purpose. 3. Brief description of the invention The main object of the present invention is to provide a method for manufacturing a flash memory having a floating gate with a large surface area. Another object of the present invention is to provide a method for manufacturing a flash memory having a high gate coupling ratio (high Gate Coupling Ratio; high GCR). Still another object of the present invention is to provide a method for manufacturing flash memory with high density and high circuit performance. The main method of the present invention is briefly described as follows. First, the traditional shallow trench isolation technology (Shallow Trench Isolation; STI) is used to form the thick oxide layer required to isolate the transistors on the silicon semiconductor substrate. Next, a first dielectric layer is formed, and then photolithography technology is used to form a photoresist circle and a first photoresist opening at a position to be used as a floating gate. 2 The size of this paper is applicable to China National Standard (CNS) A4 (210X297mm) (please read the note ^^ on the back before filling in this page). 316334 A7 B7 5. Description of invention (), then A non-volatile organic polymer (non-volatile organic polymer) is formed in the slurry etching reaction chamber. Then, the first dielectric layer is etched by plasma etching technology to form a first concave groove, and the width of the first concave groove is smaller than the lithography resolution limit. Next, a tunnel oxide layer is formed in the first groove. Then, a layer of first polycrystalline sand is deposited. Next, an inter-polysi dielectric layer (inter-polysi dielectric) is formed. The inter-polysi dielectric layer does not fill the first groove, but forms a gap. Then, a layer of second polycrystalline silicon is formed, and the second polycrystalline silicon fills the gap. Next, using chemical mechanical polishing (Chemical Mechanical Polishing; CMP) to polish the second polycrystalline silicon, the polycrystalline silicon interlayer dielectric layer, the first polycrystalline silicon and the first dielectric layer, the polishing A small portion of the first dielectric layer is processed. After the polishing process is completed, the second polycrystalline silicon, the intercrystalline polysilicon dielectric layer and the first polycrystalline silicon other than the first groove are removed. Finally, dilute hydrofluoric acid is used to remove the first dielectric layer to expose the polycrystalline silicon, the polycrystalline silicon interlayer dielectric layer and the first polycrystalline sand to form a floating gate and a control gate (Controlledgate). Finally, the standard technology is used to form the source / drain, a flash erasable / programmable read-only memory with high density and high circuit performance. 4. Brief description of the drawings Figures 1 to 12 are schematic cross-sectional views of the manufacturing process according to an embodiment of the present invention. Figure 1 is a schematic cross-sectional view of the process after forming a first dielectric layer on a silicon semiconductor substrate; Figure 2 is a cross-sectional schematic view of the process after forming a photoresist pattern and a first photoresist opening using lithography; Figure 3 is a non-volatile layer A cross-sectional view of the process cross-section after a non-volatile organic polymer (non-volatile organic polymer) is shown in FIG. 4. FIG. 4 is a schematic cross-sectional view of the process cross-section after the first dielectric layer is etched by plasma etching technology to form a first groove I ρ FIG. 5 is a schematic cross-sectional view of the process after removing the photoresist pattern and non-volatile organic high molecular sidewall material; FIG. 6 is a schematic cross-sectional view of the process after forming a tunnel oxide layer in the first recess; Figure 7 is a schematic diagram of the process profile after depositing a layer of first polycrystalline silicon; printed by the Beigong Consumer Cooperative of the Central Bureau of Samples of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) Figure 8 is the formation of a layer of polycrystalline sand In the dielectric layer (inter-poiysidielectric), the dielectric layer between the polycrystalline sands does not fill the first groove, but a schematic cross-sectional view of the process after the gap is formed. FIG. 9 is a schematic cross-sectional view of the process after forming a layer of second polycrystalline silicon, the second polycrystalline silicon fills the gap; FIG. 10 is the second polycrystalline silicon and complex except for the first groove The schematic cross-sectional view of the process after the inter-silicon dielectric layer and the first polycrystalline sand; Figure 10I is the schematic cross-sectional view of the process after removing the first dielectric layer; Figure 12 is the formation of N + source / drain Schematic diagram of process profile. 3 This paper wave scale is used in the Chinese National Standard (CNS) 8-4 (210X297mm) S16334 printed by the Central Consumers Bureau of the Ministry of Economic Affairs of the Staff Consumer Cooperative A7 B7 5. Description of the invention () 5. Detailed description of the invention First, Use the shallow shallow trench isolation technology (Shallow Trench Isolation; STI) to form the thickness required to isolate n-channel metal oxide half field effect transistors on a p-type sand semiconductor substrate with a resistance value of about 2.5 ohm-cm and a lattice orientation (100) An oxide layer (thick oxide). The thickness of the thick oxide layer is between 3000 angstroms and 8000 angstroms. The thick oxide layer is not shown in the figure. In addition to using shallow groove isolation technology to form a thick oxide layer, the conventional local sand oxidation technology (LOCOS) can also be used to form a thick oxide layer, but the thick oxide layer formed using shallow groove isolation technology provides a relatively flat terrain terrain. Now please refer to Figure 1 and Figure 2. Next, a first dielectric layer 110 is formed, as shown in FIG. 1, and then a photoresist pattern 112 and a first photoresist opening 113 are formed at a position prepared as a floating gate by using lithography technology, as shown in FIG. 2 Show. • The first dielectric layer 110 may be doped or non-doped silicon dioxide formed by low-pressure chemical vapor deposition, the reaction gas is SiH4 and 02, and the reaction temperature is between 650 and 800 ° C. The reaction pressure is between 0.2 and 0.4 torr, and the thickness is between 3000 and 8000 angstroms. It can also be a boron-phosphorus doped silicon dioxide film (BPSG) or a phosphorus-doped silicon dioxide film (PSG) formed by atmospheric pressure chemical vapor deposition (APCVD) or subatmospheric pressure chemical vapor deposition (SACVD) The reaction gases are TMB and TMP, and the thickness is between 3000 and 8000 angstroms. The photoresist pattern 112 is a positive photoresist, and its thickness is between 8000 and 12,000 angstroms. The width of the first photoresist opening 113 is between 0.2 and 0.5 microns, depending on the lithographic resolution limit of the stepper. Now please refer to Figure 3, Figure 4 and Figure 5. Next, a non-volatile organic high molecular 114 (non-volatile organic polymer) is formed in the plasma etching reaction chamber of the dielectric layer, as shown in FIG. 3. Then, the first dielectric layer 11.0 is etched using a magnetic field enhanced active ion plasma etching technique to form a first recess 116, as shown in% D. Please note in particular that the width of the first groove 116 is the first photoresist opening 113, that is, the width of the first groove 116 is smaller than the lithography resolution limit. During the etching of the first dielectric layer 110, a non-volatile organic polymer sidewall spacer 115 is formed. The non-volatile organic polymer sidewall spacer 115 narrows the first photoresist口 113。 The opening 113. In addition, when forming the "non-volatile organic high molecule 114", it is necessary to increase the flow rate of trifluorohydrogen or carbon tetrafluoride gas in the dielectric layer plasma etching reaction chamber. Next, using oxygen plasma, sulfuric acid, and diluted hydrofluoric acid to remove the photoresist pattern 112 and the non-volatile organic polymer sidewall material 115. After the first dielectric layer 110 is removed as shown in FIG. 5 Plasma etching to form the first groove 116 may use magnetic field enhanced active ion plasma etching technology (MERIE) or electron cyclotron resonance plasma etching technology (ECR) or traditional active ion plasma etching technology ( RIE), usually using magnetic field-enhanced active ion type electric paper size standard Chinese standard (CN§ > A4 specification (210X297mm) (please read the precautions on the back before filling this page) A7 B7 printed by the Beigong Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs V. Description of the invention (): slurry etching technology, the plasma reaction gas is trifluorohydrocarbon and gas gas, for example, the model manufactured by Japan Electric Company (TEL) The etching principle of the TEL8500 hungry engraving machine or the PR5000E etching machine manufactured by American Applied Materials, the etching principle belongs to the magnetic field enhanced active ion plasma etching technology, which can provide equivalent effects The ideal etch uniformity 'is also very high for the contact selectivity of 100 on the P-type silicon semiconductor substrate, which is a commercial touch etching device. In addition, the lithographic light forming the first photoresist opening Π3 The photoresist pattern 112 is a reversed-tone pattern of the floating gate of a conventional N-channel metal-oxide half field effect transistor. Now please refer to FIGS. 6 and 7. Next, in the first groove 116 A tunnel oxide layer 1 ~ 8 (tunneloxide) is formed therein, as shown in Figure 6. The tunnel oxide layer 118 is to thermally oxidize the surface of 100 on the P-type silicon semiconductor substrate in a high temperature environment of dry oxygen It is formed by silicon atoms, whose oxidation temperature is between 8 ip and 1000 ° C, and its thickness is between 50 and 200 angstroms. Then, a layer of first polycrystalline silicon 120 is deposited, as shown in Figure 7. A polycrystalline silicon 120 is usually formed by low-pressure chemical vapor deposition doped with synchronous phosphorus atoms, the reaction gas is PH3, SiH4 and N2 or AsH3, SiH4 and N2 mixed gas, the reaction temperature is between 500 and 050 ° C Its thickness is between 1000 and 3000 angstroms, and its impurity ion concentration Between 1E20 to 1E21 atoms / cubic centimeter, and the preferred concentration is 5E20 atoms / cubic centimeter. Please note that the H or the first polycrystalline silicon 120 in Shenji can be used according to necessity. The implantation technique performs channel doping in the first groove 116 to form a lightly doped region to adjust the threshold voltage of the N-channel metal-oxide half-field transistor. Generally, the channel doping Ion implantation, the ion is always Zen. Please refer to Figure 8 and Figure 9. Next, a layer of inter-polysi dielectric (ip) is formed, and the inter-polysilicon dielectric layer 122 is not full. The first groove 116 ^ forms a gap 123, as shown in FIG. 8. Then, a layer of second polycrystalline silicon 124 is formed, and the second polycrystalline silicon 124 fills the gap 123, as shown in FIG. 9. The thickness of the intercrystalline silicon dielectric layer 122 is between 50 and 200 angstroms. The second polycrystalline silicon 124 is also formed by a low-pressure chemical vapor deposition method in which synchronous phosphorus atoms are doped. The reaction gas is a mixed gas of phosphorus trihydride and silane, and the reaction temperature is between 500 and 600 ° C. The thickness is between 1000 and 3000 angstroms to fill the gap 123. For consideration, the impurity atom concentration is between 1E20 and 1E21 atoms / cubic centimeter, and the more appropriate value is 5E20 atoms / cubic centimeter. In addition, in addition to forming the second polycrystalline silicon 124 by low-pressure chemical vapor deposition doped with synchronous phosphorus atoms, the second polycrystalline silicon 124 can also be doped with ion implantation technology to make it conductive. Now please refer to Figure X and Figure ^. Then, using chemical mechanical polishing technology (Chemical Mechanical Polishing; CMP) on the second polycrystalline silicon 124, the polycrystalline silicon interlayer dielectric layer 122, the first complex. _ 5 This paper size is applicable to the Chinese National Standard (CNS ) A4 specification (210X297mm) (Read the precautions on the back before filling out this page). Installed.-· Order A7 B7 printed by the Employee Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economy. V. Description of invention () Crystal silicon 120 and A dielectric layer 110 is polished, and the polishing process removes a small portion of the first dielectric layer 110, as shown in FIG. After the polishing process is completed, the second polysilicon 124, the inter-polysilicon dielectric layer 122 and the first polysilicon 120 other than the first groove 116 are removed, leaving the second polysilicon respectively 124a, a polycrystalline silicon interlayer dielectric layer 122a and a first polycrystalline silicon layer 120a, the first dielectric layer 110 is also partially removed to become a first dielectric layer 110a, and the polycrystalline silicon layer 124a 1. The polycrystalline silicon interlayer dielectric layer 122a and the first polycrystalline silicon layer 120a are buried in the first groove 116. Finally, the first dielectric layer 110a is removed by diluted hydrofluoric acid to expose The polycrystalline silicon 124a, the polycrystalline silicon interlayer dielectric layer 122a and the first polycrystalline silicon 120a must form a floating gate 120a (floatinggate) and a control gate 124a (controlledg§ip), as shown in figure * — 1 «ι .— '" ·· * · 1 " II _-.-M >'-1 " " as shown. Please note that the _ turn content ratio (Gate CQypUngRatio; QCBji is equal to the area of the intercrystalline sand dielectric layer 122a divided by the g Si of the tunnel SiS layer 118, therefore, the floating gate 120a has a larger surface area than conventional Therefore, the area of the polycrystalline sand k dielectric layer 122a is increased, so the gate coupling ratio is increased, and the mildew required for wiping or each type is reduced to improve the circuit performance. Now please refer to FIG. 12. After the control gate 124a, the N + source / drain 126 is formed by standard technology, a flash erasable / programmable read-only memory with high density and high circuit performance is finally completed, as shown in FIG. 12 In general, the ion implantation type of the N + source / drain 126 is arsenic atom, and the ion implantation dose is between 1E15 to 5E16 atoms / cm 2, and the ion implantation energy is between 30 Between 100 Kev. After completing the manufacture of the N + source / drain 126, a standard process can be used to form the contact window, the first metal connection, the via hole and the second metal connection to form an N-channel gold oxide A half field effect transistor circuit. Often titanium, titanium nitride, tungsten and aluminum alloy are used as the material 1 and the first metal connection makes electrical contact with the source / drain of the metal oxide semi-field effect transistor across the contact window The second metal connection is usually made of titanium, titanium nitride, tungsten and aluminum alloy, and the second metal connection makes electrical contact with the first metal connection across the via hole The method of the present invention can also be applied to a multi-layer metal wiring process integrated circuit above a two-layer metal wiring process. The above uses the best embodiments to illustrate the present invention, not to limit the present invention, and is well known in semiconductor technology Everyone can understand that appropriate and slight changes and adjustments will still not lose the essence of the present invention, and will not deviate from the spirit and scope of the present invention. 6 This paper scale is applicable to the Chinese National Frame Rate (CNS) A4 specification ( 210X297mm) (Please read the note on the back ^^ before filling in this page) 装 · 卜 打