A7 B7 五、發明説明（) 1. 發明之技術領域 本發明是關於積體電路之動態隨機存取記億體的製造方法，特別是關於堆疊式 動態隨機存取記憶體的製造方法。 2. 發明背景 「堆叠式動態隨機存取記億體」是在矽半導體晶圓上製造一個金氧半場效電晶 體與堆叠式電容器，並利用所述金氧半場效電晶體的源極（source)來連接電容器的 電荷儲存電極（storage node)以形成動態隨機存取記憶體的記億元。數目龐大的記 億元聚集成爲記憶元陣列。另一方面，在記億元陣列的附近則有其它電路圍繞，例 如感測放大器（sense amplifier)等電路，這些外部電路，稱爲週邊電路區域 (peripheral circuit)。 電容的公式是C= eA/T，其中，e是電容器介電層（capacitor dielectric)之介 電常數，A是電容器下層電極之表面稹，T是電容器介電層之厚度，因此，要增加 電容器之電容可以從兩個方向著手，第一個方向是採用高介電常數的材料作爲電容 器介電層，例如，Ta205、Ti02和SrTi03材料都具有非常高的介電常數，可 惜，由於這些高介電常數的材料之薄膜品質不佳，存在有絕緣層的奔潰電壓等可靠 性問題，因此到目前爲止還無法應用到動態隨機存取記億體。 要達到動態隨機存取記憶體之高積集密度的目的，必需縮小記億體之記憶元的 尺寸，然而電容器尺寸的縮小會降低電容値，使得記憶體電路的訊號/雜訊（Signal Noise ; S/N)比例降低，造成電路誤判或電路不穩定等缺點。職是之故，爲了達成 高積集密度的動態隨機存取記億體，必需尋找更尖端的製程技術，以在降低記億元 之平面電路佈局面積之同時，能夠維持或增加電容器之電容値。 經濟部中央揉準局貝工消费合作社印裝 (請先Μ讀背面之注ί項再填寫本頁) 而一如前面分析，使用高介電常數的電容器介電層既然不甚可行，吾人由電容 的公式C= e A/T可知電容的大小跟電容器下層電極之表面積成正比，因此，增加 電容器下層電極之表面積是增加電容器之電容的另一個方向，而目前最普遍的是所 謂三度空間電容器（3-D capacitor)。所述三度空間電容器是在所述轉移閘電晶體之 上方或下方的第三度空間形成電容器，以在有限的平面電路佈局面積內增加電容器 之電容値。電容器製造在所述轉移閘電晶體之上方時，稱爲堆疊式電容器（stack capacitor)，而電容器製造在所述轉移閘電晶體之下方時稱爲凹溝式電容器（trench capacitor) °A7 B7 V. Description of the Invention (1) Technical Field of the Invention The present invention relates to a method for manufacturing dynamic random access memory of integrated circuits, and particularly to a method for manufacturing stacked dynamic random access memory. 2. Background of the invention "Stacked Dynamic Random Access Memory" is to manufacture a metal-oxide-semiconductor field-effect transistor and a stacked capacitor on a silicon semiconductor wafer, and use the source of the metal-oxide-semiconductor half-field effect transistor. ) To connect the capacitor's charge storage electrode (storage node) to form a dynamic random access memory memory. A huge number of billions of yuan are gathered into a memory cell array. On the other hand, there are other circuits around the 100 million yuan array, such as circuits such as sense amplifiers. These external circuits are called peripheral circuits. The formula for capacitance is C = eA / T, where e is the dielectric constant of the capacitor dielectric layer, A is the surface of the capacitor's lower electrode T, and T is the thickness of the capacitor dielectric layer. Therefore, it is necessary to increase the capacitor Capacitance can start from two directions. The first direction is to use high dielectric constant materials as the capacitor dielectric layer. For example, Ta205, Ti02 and SrTi03 materials all have very high dielectric constants. Unfortunately, due to these high dielectric constants, The material of the electric constant material is of poor quality and has reliability problems such as the breakdown voltage of the insulating layer, so it has not been applied to dynamic random access memory. To achieve the high accumulation density of dynamic random access memory, it is necessary to reduce the size of the memory cell of the billionth memory. However, the reduction in the size of the capacitor will reduce the capacitance 値, making the signal / noise of the memory circuit (Signal Noise; The S / N) ratio decreases, causing shortcomings such as misjudgment or unstable circuits. This is why, in order to achieve dynamic random access memory with high accumulation density, it is necessary to find more sophisticated process technologies to reduce or maintain the capacitance of capacitors while reducing the area of planar circuit layouts worth hundreds of millions. . Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative (please read the note on the back, and then fill out this page). As previously analyzed, since using a high dielectric constant capacitor dielectric layer is not feasible, we have to The formula of capacitance C = e A / T shows that the size of the capacitance is directly proportional to the surface area of the lower electrode of the capacitor. Therefore, increasing the surface area of the lower electrode of the capacitor is another direction to increase the capacitance of the capacitor. At present, the most common is the so-called three-dimensional space. Capacitor (3-D capacitor). The three-degree space capacitor is a capacitor formed in a third degree space above or below the transfer gate transistor to increase the capacitance of the capacitor within a limited planar circuit layout area. When the capacitor is manufactured above the transfer gate transistor, it is called a stack capacitor, and when the capacitor is manufactured below the transfer gate transistor, it is called a trench capacitor.
Watanabe 等人於 IEDM 1988 年第 600 頁戶斤發表之「stacked capacitor cells for high density dynamic RAMS」與 Wakamiya 等人於 VLSI Technology 1989 第 69 頁 所發表之「novel stacked capacitor cell for 64 Mb DRAM」均揭露了堆曼式電容器結 構。S. Kimura等人的美國專利第4742018號和T.Ema美國專利497Ή02號亦揭 露堆疊式電容器以增加電容器電容。曰本富士通公司的Masao Taguchi等人在美國 專利第5021357號更揭露了改良的堆疊式電容器結構，稱爲鰭型電容器結構（fm 本纸張尺度適用中國國家樣準（CNS ) Α4说格（210X297公釐） Μ濟部中央揉準局貝工消费合作杜印裝 A7 B7 五、發明説明（） capacitor)，大幅增加電容器電容，提高動態隨機存取記憶體之集積密度。日本 Hitachi公司的T. Kaga等人更在1994年IEDM第927頁之一篇題目爲「A 0.29 urn〕ΜΙΜ-CROWN cell and process technology for 1-Gigabit DRAMs」的論文，揭露了 一種更爲先進的稱爲「ΜΙΜ-CROWN結構」的堆疊式電容器，這些電容器結構均能 大幅增加電容器的電容値，提高動態隨機存取記憶體元件之集積密度。 本發明揭露了一種新穎的堆叠式電容器的製造方法，結合非晶矽粗糕的表面和 點狀的矽晶側壁物，能大幅增加堆盤式電容器的表k積，縮小電容器之平面電路佈 局面積和大幅提高電容器的電容，放寬電路設計準則以提高動態隨機存取記億體積 體電路的密度。 3.發明之簡要說明 本發明之主要目的是提供一種具有高積集密度之動態隨機存取記億體的製造方 法。 本發明之主要方法如下》首先，在砂半導體基板上形成場氧化層、複晶矽字語 線和轉移閘電晶體。所述轉移閘電晶體包含有閘氧化層、閘極、源極/汲極、與源極 /汲極。接著’沈積一層第一介電層，並接著利用微影技術與電漿蝕刻技術飽刻源極 /汲極上方之所述第一介電層以露出所述源極/汲極，以同時在所述源極區域形成記 憶元接觸窗，在所述汲極區域形成位元線接觸窗，即所述記憶元接觸窗和位元線接 觸窗是利用同一道微影光罩形成。然後，沈積一層第一複晶矽。接著，利用電漿蝕 刻技術對所述第一複晶矽進行回蝕刻，以蝕刻掉一部份的所述第一複晶矽。然後， 沈積一層金屬矽化物和第二介電層，並利用微影技術和蝕刻技術蝕刻所述第二介電 層，金屬矽化物和第一複晶矽以形成位元線結構，同時也在所述記憶元接觸窗內形 成第一複晶砂插塞物（polysilicon stud)。接著，沉積一層第二介電層’並利用触刻 技術對所述第三介電層進行垂直單向性的回蝕刻，以在所述位元線結構之二側形成 第三介電層側壁物。 然後，沈積一層第四介電層，並在第一複晶矽插塞物上方形成「第一凹溝」。 接著，沈積一層非晶砂（amorphous silicon )，所述非晶砂沒有塡滿所述「第一凹 溝」，而在所述「第一凹溝」內形成「第二凹溝」。然後，形成一·層點狀的矽晶 (dot silicon )，所述「點狀的矽晶」沒有塡滿所述「第二凹溝」，而在所述「第二 凹溝」內形成「第三凹溝」。接著，利用化學機械式琢磨技術（Chemical Mechanical Polishing : CMP)去除所述「第一凹溝」以外之所述「點狀的矽晶」與「非晶 矽」，以在所述「第一凹溝」內形成「非晶矽側壁物」和「點狀的矽晶側壁物」。 然後，去除所述第四介電層並對所述「非晶矽側壁物」進行高溫回火製程以形成粗 糙的表面，所述「第一複晶矽插塞物」、「具粗糙表面之非晶矽側壁物」與「點狀 的矽晶側壁物」構成了電容器的電荷儲存電極。完成所述電容器之電荷儲存電極的 製造後，接著形成一層電容器介電層和第二複晶矽，以形成電容器之上層電極，以 完成堆疊式電容器的製造。完成動態隨機存取記憶體記億元和位元線的製造後，接 著可利用標準製程形成後段金屬連線製程。 本纸張尺度適用中國國家標準（CNS ) Α4規格（2丨0Χ297公釐） (請先Μ讀背面之注項再填寫本頁)Watanabe et al., “Stacked capacitor cells for high density dynamic RAMS”, published by IEDM on page 600 in 1988, and “novel stacked capacitor cell for 64 Mb DRAM”, published by Wakamiya et al. On VLSI Technology 1989, page 69. A stack-man capacitor structure. S. Kimura et al., U.S. Patent No. 4742018 and T.Ema U.S. Patent No. 497,02 also disclose stacked capacitors to increase capacitor capacitance. Masao Taguchi et al. Of Fujitsu Company disclosed in US Patent No. 5021357 an improved stacked capacitor structure, called a fin-type capacitor structure (fm This paper size applies to China National Standards (CNS) Α4 said grid (210X297 Millimeter) The central government of the Ministry of Economic Affairs of the Ministry of Economic Affairs of the People's Republic of China and the Ministry of Economics and Industry of the People's Republic of China, cooperating with DuPont A7 and B7. V. Description of the invention () capacitor), which greatly increases the capacitor capacitance and increases the density of dynamic random access memory. T. Kaga et al. From Hitachi, Japan, also published a paper entitled "A 0.29 urn] ΜΙΜ-CROWN cell and process technology for 1-Gigabit DRAMs" on page 927 of the IEDM in 1994, revealing a more advanced These stacked capacitors are called "MI-CROWN structures". These capacitor structures can greatly increase the capacitance of the capacitors and increase the density of the dynamic random access memory elements. The invention discloses a novel method for manufacturing a stacked capacitor, which combines the surface of an amorphous silicon wafer and dot-shaped silicon crystal sidewalls, which can greatly increase the surface area of the stacked capacitor and reduce the planar circuit layout area of the capacitor. And greatly increase the capacitance of capacitors, relax circuit design guidelines to increase the density of dynamic random access memory circuits. 3. Brief Description of the Invention The main object of the present invention is to provide a method for manufacturing a dynamic random access memory with a high accumulation density. The main method of the present invention is as follows. First, a field oxide layer, a polycrystalline silicon word line, and a transfer gate transistor are formed on a sand semiconductor substrate. The transfer gate transistor includes a gate oxide layer, a gate electrode, a source / drain electrode, and a source / drain electrode. Next, a first dielectric layer is deposited, and then the first dielectric layer above the source / drain is etched by lithography and plasma etching to expose the source / drain at the same time. A memory cell contact window is formed in the source region, and a bit line contact window is formed in the drain region. That is, the memory cell contact window and the bit line contact window are formed by using the same lithography mask. A layer of first polycrystalline silicon is then deposited. Then, the first polycrystalline silicon is etched back using a plasma etching technique to etch away a part of the first polycrystalline silicon. Then, a metal silicide and a second dielectric layer are deposited, and the second dielectric layer, the metal silicide and the first polycrystalline silicon are etched using a lithography technique and an etching technique to form a bit line structure. A first polysilicon stud is formed in the memory cell contact window. Next, a second dielectric layer is deposited and a vertical unidirectional etch-back is performed on the third dielectric layer using a touch-etching technique to form a third dielectric layer sidewall on two sides of the bit line structure. Thing. Then, a fourth dielectric layer is deposited, and a “first groove” is formed above the first polycrystalline silicon plug. Next, a layer of amorphous silicon is deposited. The amorphous sand is not filled with the "first groove", and a "second groove" is formed in the "first groove". Then, a layer of dot silicon is formed, and the "dot silicon" does not fill the "second groove", and a "second groove" is formed in the "second groove" Third groove. " Next, chemical mechanical polishing technology (Chemical Mechanical Polishing: CMP) is used to remove the "dot-shaped silicon crystals" and "amorphous silicon" other than the "first recesses", so that "Amorphous silicon sidewall objects" and "dotted silicon crystal sidewall objects" are formed in the trench. Then, the fourth dielectric layer is removed, and the "amorphous silicon sidewall material" is subjected to a high-temperature tempering process to form a rough surface. The "first polycrystalline silicon plug" and "a material with a rough surface" "Amorphous silicon sidewall material" and "dotted silicon crystal sidewall material" constitute the charge storage electrode of the capacitor. After the manufacturing of the charge storage electrode of the capacitor is completed, a capacitor dielectric layer and a second polycrystalline silicon are then formed to form an upper electrode of the capacitor to complete the manufacture of the stacked capacitor. After the manufacture of the DRAM memory and the bit line of the dynamic random access memory is completed, the back-end metal connection process can be formed by the standard process. This paper size applies to Chinese National Standard (CNS) Α4 specification (2 丨 0 × 297 mm) (please read the note on the back before filling in this page)
A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（） 4.圖示的簡要說明 圖一到圖十五是本發明之第一個實施例的製程剖面示意圖。 圖一是在矽半導體基板上形成轉移閘電晶體後的製程剖面示意圖： 圖二是形成一層第一介f層，並接著利用微影技術與電欺触刻技術蝕去所述第一介 電層以同時形成記憶元接觸窗（cell contact)和位元線接觸窗（bit line contact)後的製程剖面示意圖； 圖三是沈稹一層第一複晶矽後的製程剖面示意圖： 圖四是對所述第一複晶矽進行回蝕刻，以蝕刻掉一部份的所述第一複晶矽後的製程 剖面示意圖； 圖五是沈積一層金屬矽化物和第二介電層後的製程剖面示意圖； 圖六是利用微影技術形成光阻圖案，以所述光阻圖案作爲蝕刻護罩，再利用電漿蝕 刻技術蝕刻所述第二介電層'金屬矽化物和第一複晶矽以形成位元線結構， 同時也在所述記憶元接觸窗內形成第一複晶矽插塞物（stud)後的製程剖面示 意圖： 圖七是去除光阻圖案後的製程剖面示意圖： 圖八是沉積一層第三介電層，並利用電漿蝕刻技術對所述第三介電層進行垂直單向 性的回蝕刻，以在所述位元線結構之二側形成「第三介電層側壁物」後的製程 剖面示意圖； 圖九是沈積一層第四介電層並平坦化所述第四介電層後的製程剖面示意圖； 圖十是利用微影技術和竜漿蝕刻技術蝕刻所述「第一複晶矽插塞物」上方之所述第 四介電層，以在所述第三介電層形成「第一凹溝」後的製程剖面示意圖； 圖十一是沈積一層「非晶矽」後的製程剖面示意圖，所述「非晶矽」沒有塡滿所述 「第一凹溝」，而在所述「第一凹溝」內形成「第二凹溝」： 圖十二是沈積「點狀的矽晶」後的製程剖面示意圖，所述「點狀的矽晶」沒有塡滿 所述「第二凹溝」，而在所述「第二凹溝」內形成「第三凹溝」； 圖十三是利用化學機械式琢磨技術去除所述「第三凹溝」以外之所述「點狀的矽 晶j與「非晶矽」與，以在所述「第一凹溝」內形成「非晶砂側壁物j和 「點狀的矽晶側壁物」後的製程剖面示意圖； 圖十四是去除所述第四介電層與後的製程剖面示意圖； 圖十五是對所述「非晶矽側壁物」進行高溫回火製程以形成粗糙的表面後的製程剖 面示意圖，所述「第一複晶矽插塞物」、「具粗糙表面之非晶矽側壁物」 與「點狀的矽晶側壁物」構成了電容器的電荷儲存電極。 本纸張尺度適用中國國家橾準（CNS ) Α4規格（210 X 297公釐） l·—! I ——ο! (請先閲讀背面之注項再填寫本頁)A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () 4. Brief description of the drawings Figures 1 to 15 are schematic cross-sectional views of the manufacturing process of the first embodiment of the present invention. FIG. 1 is a schematic cross-sectional view of a process after a transfer gate transistor is formed on a silicon semiconductor substrate: FIG. 2 is a layer of a first dielectric layer f, and then the first dielectric layer is etched away using lithography technology and electrical touch etching technology Figure 3 is a schematic cross-sectional view of the process after forming a cell contact window and a bit line contact; Figure 3 is a schematic cross-sectional view of the process after the first layer of polycrystalline silicon is deposited: A schematic cross-sectional view of the process after the first polycrystalline silicon is etched back to etch away a part of the first polycrystalline silicon; FIG. 5 is a schematic cross-sectional view of the process after depositing a metal silicide and a second dielectric layer Figure 6 is a photoresist pattern formed using lithography technology, using the photoresist pattern as an etching shield, and then plasma etching technology is used to etch the second dielectric layer 'metal silicide and the first polycrystalline silicon to form Bit line structure, and also a schematic cross-sectional view of a process after forming a first polycrystalline silicon plug (stud) in the memory cell contact window: FIG. 7 is a schematic cross-sectional view of the process after removing the photoresist pattern: FIG. 8 is a deposition First floor Three dielectric layers, and using plasma etching technology to perform vertical unidirectional etch back on the third dielectric layer to form a "third dielectric layer sidewall" on the two sides of the bit line structure Fig. 9 is a schematic cross-sectional view of a process after depositing a fourth dielectric layer and planarizing the fourth dielectric layer; Fig. 10 is a photolithography technique and a slurry etching technique to etch the "first complex A schematic cross-sectional view of the process of the fourth dielectric layer above the "crystalline silicon plug" to form a "first recess" in the third dielectric layer; Figure 11 is a view of a layer of "amorphous silicon" A schematic cross-sectional view of the process, the "amorphous silicon" does not fill the "first groove", and a "second groove" is formed in the "first groove": Figure 12 is the deposition "point" A schematic cross-sectional view of the process after the "shaped silicon crystal", the "point silicon crystal" does not fill the "second groove", and a "third groove" is formed in the "second groove" ; Figure 13 is the use of chemical-mechanical grinding technology to remove the "spot shape" other than the "third groove" A schematic cross-sectional view of the manufacturing process after forming "amorphous silicon side wall j" and "spot-shaped silicon side wall body" in said "first recessed groove"; and FIG. 15 is a schematic cross-sectional view of a process after removing the fourth dielectric layer and the substrate; FIG. 15 is a schematic cross-sectional view of a process after the high-temperature tempering process is performed on the “amorphous silicon sidewall material” to form a rough surface. A "polycrystalline silicon plug", "amorphous silicon sidewall with rough surface" and "dot-shaped silicon sidewall" constitute the charge storage electrode of the capacitor. This paper size applies to China National Standard (CNS) Α4 size (210 X 297 mm) l · —! I ——ο! (Please read the note on the back before filling this page)
,1T € 經濟部中央標準局員工消費合作社印裝 A7 B7 五、發明説明（） 5.發明之實施例 第一個實施例. 請參考圖一。首先’在電阻値約2.5 ohm-cm '晶格方向（1〇〇)之p型砂半導 體基板1〇〇上形成場氧化層101 ’所述場氧化層101通常是利用習知的局部矽氧 化技術形成（LOCOS)，當然’也可以利用淺凹溝隔離技術（Shall〇w Trench Isolation ; STI)來形成隔離金氧半場效電晶體所需之場氧化層ι〇1，其厚度介於 3500埃到6500埃之間，作爲隔離金氧半場效電晶體等電性元件之用。然後，在所 述場氧化層1〇1以外的所述P型矽半導體晶圓100表面形成轉移閘電晶體 (transferred gate transistor) ’所述轉移閘電晶體通常是由金氧半場效電晶體構成， 所述轉移閘電晶體包含有閘氧化層102、閘極l〇3b、N-源極/汲極104、二氧化矽 側壁子105與N+源極106a/汲極106b，如圖一所示。另外，在形成閘極丨〇3b之 同時也形成複晶矽字語線1〇如，如圖一所示。 所述閘氧化層102是在含乾氧的高溫環境中熱氧化所述P型矽半導體基板 100之表面之砂原子而成’其氧化溫度介於850到1000 °C之間，其厚度介於50 到200埃之間。所述閘極丨〇3b則一般是由低壓化學氣相沉積法（LPCVD)形成之 複晶矽103或鎢複晶矽化物所構成，若由複晶矽構成，其厚度介於2000到4000 埃之間，若由鎢複晶矽化物構成，則下層複晶矽之厚度介於1000到2000埃之 間，上層矽化鎢之厚度介於1〇〇〇到2000埃之間，其總厚度也是介於2000到 4000埃之間。然後，.利用微影技術與電漿蝕刻技術蝕去所述複晶矽或鎢複晶矽化 物，以形成所述轉移閘電晶體之閛極結構（gate structure )，如圖一所示。 形成所述複晶矽1〇3之反應溫度介於500到700 °C之間，而形成之複晶矽 可以未經摻雜，然後再利用離子佈植技術予以摻雜使具導電性，其離子佈植劑量介 於1E13到1E16原子/平方公分之間，離子佈植能量則介於30到80 Kev之 間，以完成對所述複晶矽1〇3之摻雜。當然，也能利用同步碟離子攙雜方法（in-situdoped)以完成對所述複晶矽103之摻雜，其反應氣體是PH3、SiH4與N2的 混合氣體或AsH3、SM4與N2的混合氣體，最後的磷離子濃度介於1E20到 1E21原子/立方公分之間，而較理想的磷離子濃度是5E20原子/立方公分之間。對 所述複晶矽之電漿蝕刻，其反應氣體則是六氟化硫、氯氣、氧氣和溴化氣等氣 體。 請再參考圖一。接著，利用磷離子佈植技術來形成所述轉移閘電晶體之N·源 極/汲極104，其離子佈植劑量介於1E13到3E丨4原子/平方公分之間，離子佈植 能量則介於20到50 Kev之間，如圖一所示，所述N·源極/汲極104是爲了降 低熱載子效應，以提高所述轉移閘電晶體之可靠性。接著’沉積一層二氧化矽 105，並利用磁場增強式活性離子式電漿蝕刻技術對所述二氧化矽1〇5進行垂直單 向性的回蝕刻，以在所述閘極l〇3b之二側形成二氧化砂側壁子1〇5。而所述二氧 化矽105通常是利用低壓化學氣相沉積法形成之無攙雜的二氧化砂，其反應氣體是 本纸張又度適用中國國家橾牟（CNS)A4洗格（2〗0乂2们公兼〉 (请先閲讀背面之注意事項再填寫本頁) ml HI Ι· -- - 1 - mu n^— A7 B7 經濟部申央標华局貝工消费合作社印製 五、發明説明（） 四已基矽酸鹽（Si(C2H5〇)4)，反應溫度約720 °C，反應壓力介於0.2到0.4托 爾之間，厚度介於500到1500埃之間。最後，利用離子砷佈植技術形成N+源極 106a/汲極106b，其離子佈植劑量介於1E15到5E16原子/平方公分之間，離子佈 植能量則介於30到80 Kev之間，以提供良好的歐姆接觸，如圖一所示。 現在參考圖二與圖三。完成所述轉移閘電晶體和複晶矽字語線l〇3a的製造 後，接著，沈積一層第一介電層，並接著利用微影技術與電漿蝕刻技術触去N+ 源極106a/汲極106b上方之所述第一介電層107以露出所述N+源極106a/汲極 106b，以同時在所述N+源極106a區域形成記憶元接觸窗l〇8a (cell contact)， 在所述N+汲極106b區域形成位元線接觸窗108b (bit line contact)，如圖二所 示，未來，堆疊式電容器之下層電極將透過所述記憶元接觸窗l〇8a跟轉移閘電晶 體之N+源極106a作電性接觸，而位元線將透過所述位元線接觸窗108b跟轉移 閘電晶體之N+汲極106b作電性接觸。請注意，所述記憶元接觸窗108a .和位元線 接觸窗l〇8b是利用同一道微影光罩形成，這是本發明關鍵之一。然後，沈積一層 第一複晶矽109，如圖三所示。 所述第一介電層107通常是利用低壓化學氣相沉積法形成之攙雜的或無攙雜 的二氧化矽，其厚度介於3000到8000埃之間。對所述第一介電層107之電漿蝕 刻以形成所述記憶元接觸窗l〇8a和位元線接觸窗108b，可以利用磁場增強式活 性離子式電漿蝕刻技術（MERIE)或電子迴旋共振電漿蝕刻技術（ECR)或傳統的 活性離子式電獎餓刻技術（RIE),而通常是利用磁場增強式活性離子式電漿蝕刻技 術，其電漿反應氣體一般是三氟氫化碳和氬氣，例如，日本電氣公司（TEL)所製造 型號 DRM之蝕刻機或美國應用材料公司（applied materials)所製造型號 CENTURA之蝕刻機，其蝕刻原理均屬於磁場增強式活性離子式電漿蝕刻技術。所 述第一複晶矽109通常是利用同步磷原子攙雜之低壓化學氣相沉積法形成，其反應 氣體是PH3、SiH4與N2的混合氣體，反應溫度介於500到650 °C之間’其厚 度介於500到3000埃之間。 現在參考圖四、圖五、圖六與圖七。接著，利用磁場增強式活性離子式電漿蝕 刻技術對所述第一複晶矽109進行垂直單向性的回蝕刻，以蝕刻掉一部份的所述第 一複晶矽109，使所述第一複晶矽109成爲第一複晶矽109a，如圖四所示。然 後，沈積一層第二介電層111和金屬矽化物110，如圖五所示。接著，利用微影技 術形成光阻圖案112，其厚度介於8000到12000埃之間，再利用磁場增強式活性 離子式電漿蝕刻技術蝕刻所述第二介電層111 '金屬矽化物Π0和第一複晶矽 l〇9a以形成位元線結構111/110a/109b，同時也在所述記憶元接觸窗l〇8a內形成 第一複晶矽插塞物109c，如圖六所示。利用氧氣電漿去除光阻圖案112，如圖七所 示。所述金屬矽化物110提供了位元線較低的電阻値，增加電路執行速度。 所述所述第二介電層111通常是利用低壓化學氣相沉積法形成之無攙雜的二 氧化砂或氮化矽，若爲無攙雜的二氧化矽其反應氣體是矽甲烷或四已基矽酸鹽’反 .應溫度約720 °c，反應壓力介於0.2到0.4托爾之間，厚度介於800到2000 (餚先'Mtjt背面之注意事項再填寫本頁) 訂1T € Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (5) Embodiment of the Invention The first embodiment. Please refer to Figure 1. First, a field oxide layer 101 is formed on a p-type sand semiconductor substrate 100 in a lattice direction (100) with a resistance of about 2.5 ohm-cm. The field oxide layer 101 is usually a conventional local silicon oxidation technology. (LOCOS) formation. Of course, shallow field trench isolation technology (Shall ow Trench Isolation; STI) can also be used to form the field oxide layer ι〇1 required to isolate the metal-oxygen half field effect transistor, with a thickness of 3500 angstroms to Between 6500 angstroms, it is used to isolate electrical components such as metal-oxide half field effect transistors. Then, a transfer gate transistor is formed on the surface of the P-type silicon semiconductor wafer 100 other than the field oxide layer 101. The transfer gate transistor is usually made of a metal-oxide half field-effect transistor. The transfer gate transistor includes a gate oxide layer 102, a gate electrode 103b, an N-source / drain 104, a silicon dioxide sidewall 105, and an N + source 106a / drain 106b, as shown in FIG. 1. . In addition, while the gate electrode 03b is formed, a polycrystalline silicon word line 10 is also formed as shown in FIG. The gate oxide layer 102 is formed by thermally oxidizing sand atoms on the surface of the P-type silicon semiconductor substrate 100 in a high temperature environment containing dry oxygen. Its oxidation temperature is between 850 and 1000 ° C, and its thickness is between Between 50 and 200 Angstroms. The gate 丨 〇3b is generally composed of polycrystalline silicon 103 or tungsten polycrystalline silicide formed by low pressure chemical vapor deposition (LPCVD). If it is composed of polycrystalline silicon, its thickness is between 2000 and 4000 angstroms. If it is composed of tungsten polycrystalline silicide, the thickness of the lower polycrystalline silicon is between 1000 and 2000 angstroms, and the thickness of the upper tungsten silicide is between 1000 and 2000 angstroms. Between 2000 and 4000 Angstroms. Then, the lithography technology and the plasma etching technology are used to etch away the polycrystalline silicon or tungsten polycrystalline silicon compound to form a gate structure of the transfer gate transistor, as shown in FIG. 1. The reaction temperature for forming the polycrystalline silicon 10 is between 500 and 700 ° C, and the formed polycrystalline silicon can be undoped and then doped with ion implantation technology to make it conductive. The ion implantation dose is between 1E13 and 1E16 atoms / cm 2, and the ion implantation energy is between 30 and 80 Kev to complete the doping of the polycrystalline silicon 103. Of course, in-situdoped method can also be used to complete the doping of the polycrystalline silicon 103. The reaction gas is a mixed gas of PH3, SiH4 and N2 or a mixed gas of AsH3, SM4 and N2. The final phosphorus ion concentration is between 1E20 and 1E21 atoms / cm3, and the ideal phosphorus ion concentration is between 5E20 atoms / cm3. For plasma etching of the polycrystalline silicon, the reaction gases are sulphur hexafluoride, chlorine, oxygen and bromine gas. Please refer to Figure 1 again. Next, the N · source / drain 104 of the transfer gate transistor is formed using a phosphorus ion implantation technique, the ion implantation dose of which is between 1E13 to 3E 丨 4 atoms / cm 2, Between 20 and 50 Kev, as shown in FIG. 1, the N · source / drain 104 is for reducing the hot carrier effect and improving the reliability of the transfer gate transistor. Next, a layer of silicon dioxide 105 is deposited, and a vertical unidirectional etch-back of the silicon dioxide 105 is performed by using a magnetic field-enhanced active ion plasma etching technique to etch the gate 103b. Side walls 105 are formed on the side. The silicon dioxide 105 is usually a non-doped sand dioxide formed by a low-pressure chemical vapor deposition method, and the reaction gas is the paper, which is also suitable for China National Mould (CNS) A4 Washing (2) 0 乂2 people's public> (Please read the notes on the back before filling in this page) ml HI Ι ·--1-mu n ^ — A7 B7 Printed by Shenyang Biaohua Bureau Shellfish Consumer Cooperative of the Ministry of Economic Affairs 5. Description of Invention () Tetrahexyl silicate (Si (C2H5〇) 4), the reaction temperature is about 720 ° C, the reaction pressure is between 0.2 and 0.4 Torr, and the thickness is between 500 and 1500 Angstroms. Finally, an arsenic cloth is used. The implantation technology forms N + source 106a / drain 106b. The ion implantation dose is between 1E15 and 5E16 atoms / cm², and the ion implantation energy is between 30 and 80 Kev to provide good ohmic contact. As shown in Figure 1. Reference is now made to Figures 2 and 3. After the fabrication of the transfer gate transistor and the polycrystalline silicon word line 103a is completed, a first dielectric layer is deposited, and then lithography is used. Technology and plasma etching technology to touch the first dielectric layer 107 above the N + source 106a / drain 106b to expose The N + source 106a / drain 106b forms a memory cell contact window 108a (cell contact) in the N + source 106a region, and a bit line contact window 108b (in the N + drain 106b region). bit line contact), as shown in FIG. 2, in the future, the lower electrode of the stacked capacitor will make electrical contact with the N + source 106a of the transfer gate transistor through the memory cell contact window 108a, and the bit line will Make electrical contact with the N + drain 106b of the transfer transistor through the bit line contact window 108b. Please note that the memory cell contact window 108a and the bit line contact window 108b use the same lithography Photomask formation is one of the key points of the present invention. Then, a layer of first polycrystalline silicon 109 is deposited, as shown in Fig. 3. The first dielectric layer 107 is usually doped by a low pressure chemical vapor deposition method. Or non-doped silicon dioxide with a thickness between 3000 and 8000 angstroms. Plasma etching of the first dielectric layer 107 to form the memory cell contact window 108a and the bit line contact window 108b , Can use magnetic field enhanced active ion plasma etching technology (MERIE) or electronics Rotary resonance plasma etching technology (ECR) or traditional reactive ion plasma etching (RIE), and usually magnetic field enhanced reactive ion plasma etching technology, the plasma reaction gas is generally trifluorohydrocarbon And argon, for example, the etching machine of model DRM manufactured by Japan Electric Company (TEL) or the etching machine of model CENTURA manufactured by applied materials of the United States. The etching principle belongs to magnetic field enhanced active ion plasma etching. technology. The first polycrystalline silicon 109 is usually formed by a low-pressure chemical vapor deposition method doped with synchronous phosphorus atoms. The reaction gas is a mixed gas of PH3, SiH4, and N2, and the reaction temperature is between 500 and 650 ° C. The thickness is between 500 and 3000 Angstroms. Reference is now made to Figures 4, 5, 6, and 7. Then, a vertical unidirectional etch-back is performed on the first polycrystalline silicon 109 by using a magnetic field enhanced active ion plasma etching technology to etch away a part of the first polycrystalline silicon 109, so that The first polycrystalline silicon 109 becomes the first polycrystalline silicon 109a, as shown in FIG. Then, a second dielectric layer 111 and a metal silicide 110 are deposited, as shown in FIG. Next, a photoresist pattern 112 is formed by using a lithography technique with a thickness between 8000 and 12000 angstroms, and then the second dielectric layer 111 ′ metal silicide Π0 and The first polycrystalline silicon 109a forms a bit line structure 111 / 110a / 109b, and also forms a first polycrystalline silicon plug 109c in the memory cell contact window 108a, as shown in FIG. The photoresist pattern 112 is removed using an oxygen plasma, as shown in FIG. The metal silicide 110 provides a lower resistance of the bit line and increases the speed of circuit execution. The second dielectric layer 111 is usually a non-doped sand dioxide or silicon nitride formed by a low-pressure chemical vapor deposition method. If the second dielectric layer 111 is non-doped silicon dioxide, the reaction gas is silane or tetrahedron. Silicate 'reaction temperature is about 720 ° C, reaction pressure is between 0.2 and 0.4 Torr, thickness is between 800 and 2000. (Notes on the back of the dish "Mtjt, please fill out this page) Order
-C 本纸張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） A7 B7 經濟部中央橾隼局員工消f合作社印裝 五、發明説明（） 埃之間。所述金屬矽化物110通常是由矽化鎢構成’由低壓化學氣相沉積法形成’ 其反應氣體是SiH4與WF6的混合氣體或SiCl2H2與WF6的混合氣體’其^度 介於500到2000埃之間。對所述第二介電層111之電漿蝕刻以形成所述位元線 結構111/llOa/lO%，可以利用磁場增強式活性離子式電獎餓刻技術（MERIE)或電 子迴旋共振電漿蝕刻技術（ECR)或傳統的活性離子式電漿蝕刻技術（RIE)，而通 常是利用磁場增強式活性離子式電獎触刻技術，其電漿反應氣體是四氟化碳、三氟 氫化碳、氧氣和氬氣。對所述第一複晶矽1〇9之電漿蝕刻以形成位元線結構 llla/110a/109b，也是利用磁場增強式活性離子式電漿蝕刻技術，其反應氣體是六氟 化硫、氯氣、氧氣和溴化氫等氣體，能提供效果相當理想的單向性蝕刻、餓刻率和 蝕刻均勻度。 現在參考圖八。接著，沉積一層第三介電層113，並利用電漿触刻技術對所述 第三介電層m進行垂直單向性的回蝕刻，以在所述位元線結構ma/U0a/109b 之二側形成第三介電層側壁物113。所述第三介電層113通常是利用低壓化學氣相 沉積法形成之無攙雜的二氧化矽或氮化矽，若爲無攙雜的二氧化矽，其反應氣體是 矽甲烷或四已基矽酸鹽，反應溫度約720 °C，反應壓力介於〇.2到0.4托爾之 間，厚度介於到2500埃之間。對所述第三介電層113之垂直單向性的回蝕 刻以在所述位元線結構llla/1 lOa/10%之二側形成第三介電層側壁物113，是利用 磁場增強式活性離子式電漿蝕刻技術或電子迴旋共振電漿蝕刻技術或傳統的活性離 子式電漿蝕刻技術，其電漿反應氣體是四氟化碳、三氟氫化碳和氬氣之混合氣體， 能提供效果相當理想的垂直單向性蝕刻、蝕刻率和蝕刻均句度。 現在參考圖九與圖十。然後，沈積一層第四介電層1Η並平坦化所述第四介 電層114，如圖九所示，並利用微影技術和電漿蝕刻技術蝕刻所述「第一複晶矽插 塞物1109c」上方之所述第四介電層114，使所述第四介電層114成爲第四介電層 114a，以在所述第三介電層形成「第一凹溝丨丨5」，如圖十所示。所述第四介電層 114最好是由在氫氟酸溶液中之触刻率非常快的材料構成，例如，所述第四介電層 114是由化學氣相沉積法形成之攙雜硼磷的二氧化矽，其反應溫度介於600到800 °C之間，反應壓力介於0.2到0.4托爾之間，其反應氣體是四已基矽酸鹽 (TK)S)與氧化氮（奶0)或甲烷（silane)與氧化氮（N20)，其厚度介於3000 到8000埃之間；例如，第四介電層是利用熱分解化學氣相沉積法（thermal Chemical Vapor Deposition ; thCVD)形成之二氧化矽，其反應溫度介於330到370 °C之間，其反應氣體是四已基砂酸鹽與臭氧（03)，其厚度介於3000埃到8000 埃之間；再例如，所述第四介電層丨14是由攙雜的或無攙雜的自旋塗佈式玻璃膜 (Spin-On-Glass ; SOG)組成。對所述第四介電層114之蝕刻以形成「第一凹溝 115」’是利用磁場增強式活性離子式電漿蝕刻技術或電子迴旋共振電漿蝕刻技術或 傳統的活性離子式電漿蝕刻技術，其電漿反應氣體是四氟化碳'三氟氫化碳和氬氣 之混合氣體。 現在參考圖-與圖十二。接著，沈積一層非晶砂116 (amorphous silicon)， 如圖十一所示。所述非晶矽116是利用低壓化學氣相沉積法形成，反應氣體是矽甲 烷’反應溫度介於500 °C到550 °C之間，反應壓力介於150 mtorr到250 (婧先Μ讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） 五、發明説明（） A7 B7 經濟部中央標準局員工消费合作社印裝 mtorr之間，厚度介於1〇〇到3000埃之間。所述非晶矽116沒有塡滿所述「第 —凹溝115」，而在所述「第一凹溝U5」內形成「第二凹溝117」’如圖十一， 示。接著’形成一層很薄的複晶砍半球型晶粒120 (p〇1ysilicon Hemi-sPherical Grain : HSG)，所述「薄的複晶矽半球型晶粒120」沒有塡滿所述「第二凹溝 117」，如圖十二所示。所述「複晶矽半球型晶粒12〇」是利用低壓化學氣相沉積法 形成，其反應溫度介於5〇〇到750 °C之間’其直徑介於50到1000埃之間。 現在參考圖十三、圖十四與圖十五。接著’利用化學機械式琢磨技術 (Chemical Mechanical Polishing ; CMP)去除所述「第一凹溝1丨5」以外之所述 「複晶矽半球型晶粒120」與「非晶矽116」，以在所述「第一凹溝115」內形成 「複晶矽半球型晶粒側壁物丨2〇」和「非晶砂側壁物丨丨紐」，如圖十三所示。 接著，利用氫氟酸溶液去除所述第四介電層"4a ,露出「複晶矽半球型晶粒側 壁物120」和「非晶矽側壁物116a」，如圖十四所示。然後，在大於10·6 torr的 高真空的情況下，對所述「非晶砂側壁物116a」進行回火處理99 ’回火溫度介於 550 °C到650 °C之間，以在所述「非晶矽側壁物116a」的側表面形成粗縫表 面130,如圖十五所示。所述「第一複晶矽插塞物109c」、「非晶矽側壁物 116a」、「複晶矽半球型晶粒側壁物120」與"粗糖表面130」構成了電容器的電 荷儲存電極l〇9c/116a/120/130，透過所述記憶元接觸窗108a跟所述轉移閘電晶體 之N+源極106a作電性接觸。所述『薄的複晶矽半球型晶粒120」和「粗糖表面 130」提供了較大的表面稹，故構成電容器的電荷儲存電極109C/116a/120/130提供 了較大的電容器電容，增加動態隨機存取記憶體的讎密度。 完成所述電容器之電荷儲存電極l〇9c/l 16a/120/130的製造後，必需接著形成 一層電容器介電層和第二複晶矽，以完成堆疊式電容器的製造。所述電容器介電層 通常是由氧化氮化砂（Oxynitride)、氮化砂（Nitride)和二氧化砂（Oxide)藉由下 述方法形成。首先，在溫度介於800°C到950°C之間時熱氧化由複晶矽構成之所 述電荷儲存電極l〇9c/l 163/120/130，以形成厚度介於40埃到200埃之間的氧化 矽。接著，在溫度介於650°C到750°C之間時以低壓化學氣相沉積法形成厚度介 於40埃到60埃之間的氮化矽。最後，在溫度介於800°C到950°C之間時氧化 所述氮化矽，以形成厚度介於20埃到50埃之間的氧化氮化矽。自然，所述電容 器介電層亦可由其它高介電常數材料組成，例如五氧二鉅（Ta205 )，或由Ti〇2 和SrTi03等高介電常數材料所組成。所述第二複晶矽之形成方法跟第一複晶矽 109 —樣，是利用同步攙雜之低壓化學氣相沉積法形成，其反應氣體是PH3 ' SiH4 與N2或AsH3、SiH4與N2的混合氣體，攙雜有磷和砷等雜質原子，其反應溫度 介於500到650 °C之間，其厚度介於1000到2000埃之間，所述第二複晶矽也 必需具備導電性，其雜質離子濃度介於1E20到1E21原子/立方公分之間，而較理 想的濃度是5E20原子/立方公分。而形成電容器的上層電之電漿蝕刻，也是利用磁 場增強式活性離子式電漿蝕刻技術（MERIE)，其電漿反應氣體是六氟化硫、氧氣 和溴化氫之混合氣體。 (請先Mti背面之注意事項再填寫本頁)-C This paper size is in accordance with Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) A7 B7 Printed by the staff of the Central Government Bureau of the Ministry of Economic Affairs F Cooperatives 5. Description of invention () between Egypt and Egypt. The metal silicide 110 is usually composed of tungsten silicide, which is formed by a low pressure chemical vapor deposition method. The reaction gas is a mixed gas of SiH4 and WF6 or a mixed gas of SiCl2H2 and WF6. Its degree is between 500 and 2000 Angstroms. between. Plasma etching of the second dielectric layer 111 to form the bit line structure 111 / llOa / lO%, a magnetic field enhanced active ion electrowinning technique (MERIE) or an electron cyclotron resonance plasma may be used. Etching technology (ECR) or traditional reactive ion plasma etching technology (RIE), and usually magnetic field enhanced reactive ion plasma awarding technology, whose plasma reaction gas is carbon tetrafluoride, trifluorocarbon , Oxygen and argon. Plasma etching of the first polycrystalline silicon 1009 to form a bit line structure llla / 110a / 109b is also a magnetic field enhanced active ion plasma etching technique, and the reaction gases are sulfur hexafluoride and chlorine gas. , Oxygen, hydrogen bromide and other gases, can provide unidirectional etching, starvation rate and etching uniformity. Reference is now made to FIG. Next, a third dielectric layer 113 is deposited, and the third dielectric layer m is subjected to a vertical unidirectional etch-back using a plasma etching technique to form a bit line structure ma / U0a / 109b. A third dielectric layer sidewall 113 is formed on both sides. The third dielectric layer 113 is usually doped non-doped silicon dioxide or silicon nitride formed by a low-pressure chemical vapor deposition method. If the doped non-doped silicon dioxide is used, the reaction gas is silane silicon or tetrahexyl silicon. Acid, the reaction temperature is about 720 ° C, the reaction pressure is between 0.2 and 0.4 Torr, and the thickness is between 2500 Angstroms. The vertical unidirectional etch-back of the third dielectric layer 113 to form a third dielectric layer sidewall 113 on two sides of the bit line structure llla / 1 lOa / 10% is a magnetic field enhanced method Active ion plasma etching technology or electron cyclotron resonance plasma etching technology or traditional active ion plasma etching technology, the plasma reaction gas is a mixed gas of carbon tetrafluoride, trifluorohydrocarbon and argon, which can provide The effect is quite ideal for vertical unidirectional etching, etching rate and etching. Reference is now made to Figures 9 and 10. Then, a fourth dielectric layer 1 沉积 is deposited and the fourth dielectric layer 114 is planarized, as shown in FIG. 9, and the “first polycrystalline silicon plug” is etched using a lithography technique and a plasma etching technique. 1109c "above the fourth dielectric layer 114, so that the fourth dielectric layer 114 becomes the fourth dielectric layer 114a, so as to form a" first recessed groove 5 "in the third dielectric layer, As shown in Figure 10. The fourth dielectric layer 114 is preferably made of a material having a very high etching rate in a hydrofluoric acid solution. For example, the fourth dielectric layer 114 is a doped boron phosphorus formed by a chemical vapor deposition method. The reaction temperature of silicon dioxide is between 600 and 800 ° C, and the reaction pressure is between 0.2 and 0.4 Torr. The reaction gas is tetrahexyl silicate (TK) S and nitrogen oxide (milk). 0) or methane (silane) and nitrogen oxide (N20), with a thickness between 3000 and 8000 angstroms; for example, the fourth dielectric layer is formed using a thermal chemical vapor deposition (thCVD) method The reaction temperature of silicon dioxide is between 330 and 370 ° C, and the reaction gas is tetrahexyl oxalate and ozone (03), and its thickness is between 3000 angstroms and 8000 angstroms; for example, all The fourth dielectric layer 14 is composed of a doped or non-doped spin-on-glass (SOG) film. The fourth dielectric layer 114 is etched to form a "first recess 115" using magnetic field enhanced active ion plasma etching technology or electron cyclotron resonance plasma etching technology or traditional active ion plasma etching. Technology, the plasma reaction gas is a mixed gas of carbon tetrafluoride 'trifluorohydrocarbon and argon. Reference is now made to Figures-and Figure XII. Next, a layer of amorphous silicon 116 (amorphous silicon) is deposited, as shown in FIG. The amorphous silicon 116 is formed by a low-pressure chemical vapor deposition method. The reaction gas is silicon methane. The reaction temperature is between 500 ° C and 550 ° C, and the reaction pressure is between 150 mtorr and 250. Note: Please fill in this page again.) The size of the paper is applicable to the Chinese National Standard (CNS) A4 (2 丨 0297mm). 5. Description of the invention () A7 B7 Printed on the mtorr by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, The thickness is between 100 and 3000 angstroms. The amorphous silicon 116 does not fill the "first groove 115", and a "second groove 117" is formed in the "first groove U5" as shown in Fig. 11. Next, 'a thin layer of polycrystalline silicon hemi-spherical grain 120 (p0ysilicon Hemi-sPherical Grain: HSG) was formed, and the "thin polycrystalline silicon hemisphere-shaped grain 120" did not fill the "second concave Ditch 117 ", as shown in Figure 12. The "polycrystalline silicon hemispherical grain 12" is formed by a low pressure chemical vapor deposition method, and its reaction temperature is between 500 and 750 ° C 'and its diameter is between 50 and 1000 angstroms. Reference is now made to FIGS. 13, 14 and 15. Then 'remove the "multicrystalline silicon hemispherical grain 120" and "amorphous silicon 116" other than the "first groove 1 丨 5" by using chemical mechanical polishing (CMP) to In the "first groove 115", a "polycrystalline silicon hemispherical grain sidewall 丨 20" and an "amorphous sand sidewall 丨 丨" are formed, as shown in FIG. Next, the fourth dielectric layer " 4a is removed using a hydrofluoric acid solution, and the "polycrystalline silicon hemispherical grain side wall object 120" and the "amorphous silicon side wall object 116a" are exposed, as shown in FIG. Then, in the case of a high vacuum greater than 10.6 torr, the "amorphous sand sidewall 116a" is tempered 99 '. The tempering temperature is between 550 ° C and 650 ° C, so that A rough surface 130 is formed on the side surface of the "amorphous silicon sidewall 116a", as shown in FIG. The "first polycrystalline silicon plug 109c", "amorphous silicon sidewall 116a", "polycrystalline silicon hemispherical grain sidewall 120" and "coarse sugar surface 130" constitute the charge storage electrode of the capacitor. 〇9c / 116a / 120/130, and make electrical contact with the N + source 106a of the transfer gate transistor through the memory cell contact window 108a. The "thin polycrystalline silicon hemispherical grain 120" and "coarse sugar surface 130" provide a larger surface area, so the charge storage electrode 109C / 116a / 120/130 constituting the capacitor provides a larger capacitor capacitance, Increase the density of dynamic random access memory. After the manufacturing of the capacitor's charge storage electrode 10c / l 16a / 120/130 is completed, a capacitor dielectric layer and a second polycrystalline silicon must be formed next to complete the manufacturing of the stacked capacitor. The capacitor dielectric layer is generally formed of Oxynitride, Nitride, and Oxide by the following method. First, the charge storage electrode 109c / l 163/120/130 composed of polycrystalline silicon is thermally oxidized at a temperature between 800 ° C and 950 ° C to form a thickness of 40 angstroms to 200 angstroms. Between silicon oxide. Next, a silicon nitride having a thickness between 40 angstroms and 60 angstroms is formed by a low pressure chemical vapor deposition method at a temperature between 650 ° C and 750 ° C. Finally, the silicon nitride is oxidized at a temperature between 800 ° C and 950 ° C to form a silicon oxide nitride having a thickness between 20 and 50 angstroms. Naturally, the capacitor dielectric layer may also be composed of other high dielectric constant materials, such as pentoxide (Ta205), or high dielectric constant materials such as Ti02 and SrTi03. The formation method of the second polycrystalline silicon is the same as that of the first polycrystalline silicon 109, which is formed by using a simultaneous doped low-pressure chemical vapor deposition method. The reaction gas is a mixture of PH3 'SiH4 and N2 or AsH3, SiH4 and N2. The gas is doped with impurity atoms such as phosphorus and arsenic, the reaction temperature is between 500 and 650 ° C, and the thickness is between 1000 and 2000 angstroms. The second polycrystalline silicon must also have conductivity and its impurities The ion concentration is between 1E20 and 1E21 atoms / cm3, and the ideal concentration is 5E20 atoms / cm3. The plasma etching of the upper layer of the capacitor is also a magnetic field enhanced active ion plasma etching technology (MERIE). The plasma reaction gas is a mixed gas of sulfur hexafluoride, oxygen and hydrogen bromide. (Please pay attention to the notes on the back of Mti before filling this page)
本紙張尺度適用中國國家橾準（CNS ) A4現格（210X297公廣） A7 B7 五、發明説明（） 第二個管施例. 在圖十一沈積一層非晶矽116後，不形成所述很薄的複晶矽半球型晶粒12〇 (polysilicon Hemi-Spherical Grain ; HSG)，在對所述「非晶矽側壁物 116a」進行 回火處理99後，依然可在所述「非晶矽側壁物H6a」的表面形成粗糙表面 130，增加電荷儲存電極的表面積。 第三個實施例. .圖十一中的非晶矽116以【複晶矽】替代之，再形成一層很薄的複晶矽半球型晶粒 120 (polysilicon Hemi-Spherical Grain : HSG)，接著，利用化學機械式琢磨技術去 除所述「第一凹溝115」以外之所述「複晶矽半球型晶粒120」與【複晶矽】，以 在所述「第一凹溝115」內形成「複晶矽半球型晶粒側壁物120」和【複晶砂側壁 物】，並取消後面的回火處理99。 完成上述動態隨機存取記憶體記憶元和位元線的製造後，接著可以利用標準製 程形成接觸窗、第一金屬連線、介層孔和第層金屬連線等後段金屬連線製程，以完 成具多層金屬連線之堆叠式動態隨機存取記憶體積體電路。所述第一金屬連線通常 是以鈦、氮化鈦、鎢和鋁合金爲材料，並且，所述第一金屬連線跨過所述接觸窗跟 所述金氧半場效電晶體之源極/汲極作電性接觸。所述第二金屬連線通常也是以鈦、 氮化鈦、鎢和鋁合金爲材料，並且，第二金屬連線跨過所述介層孔跟所述第一金屬 連線作電性接觸。 以上係以最佳實施例來閱述本發明，而非限制本發明，並且，熟知半導體技藝 之人士皆能明瞭，適當而作些微的改變及調整，仍將不失本發明之要義所在，亦不 脫離本發明之精神和範圍。 !11 11_ο! (請先閲讀背面之注意事項再填寫本頁) 訂 £ 經濟部中央橾隼局貝工消費合作社印装 本紙張尺度適用中國國家標準（CNS ) A4说格（2丨0X297公釐）This paper size applies to China National Standards (CNS) A4 (210X297 public) A7 B7 5. Description of the invention () The second tube example. After depositing a layer of amorphous silicon 116 in Figure 11, the said Polysilicon Hemi-Spherical Grain 12 (HSG), which is a very thin polycrystalline silicon, can still be processed in the "amorphous silicon" after the "amorphous silicon sidewall 116a" is tempered. The surface of the sidewall object H6a ″ forms a rough surface 130, which increases the surface area of the charge storage electrode. Third Embodiment ... The amorphous silicon 116 in FIG. 11 is replaced by [polycrystalline silicon], and a thin layer of polysilicon Hemi-Spherical Grain 120 (HSG) is formed, and then , Using chemical mechanical polishing technology to remove the "polycrystalline silicon hemispherical grains 120" and "polycrystalline silicon" other than the "first groove 115" to be within the "first groove 115" Form "polycrystalline silicon hemispherical grain sidewall 120" and "polycrystalline sand sidewall", and cancel the subsequent tempering treatment 99. After completing the manufacturing of the above-mentioned dynamic random access memory memory cells and bit lines, a standard metal process can then be used to form a subsequent metal connection process such as a contact window, a first metal connection, a via, and a first layer metal connection. Complete a stacked dynamic random access memory volume circuit with multilayer metal connections. The first metal connection is usually made of titanium, titanium nitride, tungsten, and aluminum alloy, and the first metal connection crosses the contact window and the source of the gold-oxygen half field effect transistor. / Drain makes electrical contact. The second metal connection is also usually made of titanium, titanium nitride, tungsten, and aluminum alloy, and the second metal connection makes electrical contact with the first metal connection across the via hole. The above is a description of the present invention in the best embodiment, but not a limitation of the present invention. Those skilled in the art of semiconductors will be able to understand that making appropriate changes and adjustments will not lose the essence of the present invention. Without departing from the spirit and scope of the invention. ! 11 11_ο! (Please read the precautions on the back before filling out this page) Order £ The printed paper size of the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives is applicable to the Chinese National Standard (CNS) A4 standard (2 丨 0X297 mm) )