A7 _____B7 五、發明説明（：/ ) 發明背景 (1) 發明領域 本發明係關於一種積體電路半導體元件，更仔細地說， 係關於一種具有雙皇冠電容器以提高電容値之動態隨機存取記 憶體(DRAM)細胞元的製造方法。 (2) 習知技藝 最近幾年，半導體基板與半導體晶片上的積體電路密度已經 大幅地提升，因爲各別的元件尺寸縮小的緣故，使得晶片上的元 件集積密度爲之提高。元件能夠縮小，要歸功於諸如高解析度的 微影技術與方向性(非均向性)的電漿蝕刻等先進的半導體技術創 新。相信，電路密度繼續提高的結果將會需要更精進的半導體製 程技術，對於元件的電性要求也會隨之提高。 在電子業界用來儲存資訊的DRAM晶片，正是需要不斷提 高密度的電路型態之一。DRAM晶片上的電路是由各個DRAM 儲存細胞元所組成的陣列所構成的，每一個細胞元的儲存電容 器內所儲存的電荷都代表一個二進爲的資料(位元）。儲存或擷 取儲存電容器內的資料時，需要透過各個記憶體細胞元上的傳 送電晶體，與DRAM晶片周邊上的選址和讀寫電路。這種傳送 電晶體通常是一個場效電晶體(FET)，而各個細胞元內的電容 器，不是在半導體基板內作成溝槽型的電容器，就是在細胞元 區域內的FET上作成堆疊型的電容器。到1998年前，DRAM晶 片上記憶體細胞元(位元)的數目預期將到達二億五千六百萬 (256百萬)個，而且預期到2001年前，DRAM晶片上的位元數 還將提高到十億位元。 DRAM晶片上的記憶細胞元數目增加得如此迅速，同時爲 ------------装-- (請先閱讀背面之注意事項再填寫本頁)A7 _____B7 V. Description of the invention (: /) Background of the invention (1) Field of the invention The present invention relates to a semiconductor device with integrated circuit, and more specifically, it relates to a dynamic random access memory with a double crown capacitor to improve the capacitance. Manufacturing method of DRAM cell. (2) Know-how. In recent years, the density of integrated circuits on semiconductor substrates and semiconductor wafers has been greatly increased. Because of the reduction in the size of individual components, the density of the components on the wafer has increased. Components can be reduced thanks to advanced semiconductor technology innovations such as high-resolution lithography and directional (non-uniform) plasma etching. It is believed that as a result of the continued increase in circuit density, more sophisticated semiconductor process technology will be required, and the electrical requirements for components will also increase. The DRAM chip used to store information in the electronics industry is one of the circuit types that need to continuously increase density. The circuit on the DRAM chip is composed of an array of storage cells in each DRAM. The charge stored in the storage capacitor of each cell represents a binary data (bit). When storing or retrieving the data in the storage capacitor, it is necessary to pass the transmission crystals on the cells of each memory and the addressing and reading and writing circuits on the periphery of the DRAM chip. This transmission transistor is usually a field effect transistor (FET), and the capacitor in each cell is either a trench capacitor in a semiconductor substrate or a stacked capacitor on a FET in the cell area. . By 1998, the number of memory cells (bits) on DRAM chips is expected to reach 256 million (256 million), and by 2001, the number of bits on DRAM chips is expected to be Will increase to one billion bits. The number of memory cells on the DRAM chip has increased so rapidly, and at the same time ------------ installed-(Please read the precautions on the back before filling this page)
,1T 本紙乐尺度通用中國國家標準（CNS ) Α4規格（210X297公釐） 經濟部十央標準局員工消費合作社印製 A7 __B7 五、發明説明（〇?) 了提高電路功能，又需要維持一個合理的晶片大小，因此就需 要進一步縮小各個細胞元的面積。細胞元縮小之後，很難製作 出具有足夠電容値的堆疊型電容器，所儲存的電荷也很難達到 讀取電路(感應放大器)可以偵測到的信號對雜訊比。電荷降低 的結果，就薷要提高這些揮發性儲存細胞元中定期重新儲存電 荷的更新周期頻率。既然DRAM晶片上容納眾多細胞元的結 果，使電容器的面積受限於細胞元的大小，要提高電容値就需 要找出其他的方法，可以不需要增加電容器在基板表面上所佔 據的面積。 目前，在文獻中已有許多三維堆疊式、可以提高電容値的 儲存電容器的報導。例如，Sim等人的5,399,518號美國專利 中，提出一種具有雙圓柱壁的儲存電容器的形成方法。這種方 法中，先蝕刻位元線接觸，形成絕緣的位元線，然後再蝕刻出 電容器節點接觸之接觸窗所形成的第二陣列。然後，在節點接 觸窗內與基板的其他地方上，沉積一層厚厚的複晶矽層，形成 了儲存電容器的電極。在此複晶矽層上形成一道用來形成外圓 柱的光罩和一道用來形成內圓柱的光罩後，就用這些光罩形成 雙圓柱形的電極。Sim等人用一層導電層形成電極。Park等人 的5,443,993號美國專利也提出一種DRAM細胞元的形成方法， 先形成位元線，然後蝕刻出作爲節點接觸之接觸窗的第二陣 歹IJ。然後，Park利用一層已制定之導電層上的絕緣空間子，挖 出部份的導電層，接著沉積第二層的導電層，並非均向性地回 蝕刻，形成圓柱形的電極。最後去除絕緣的側壁，即形成自立 的圓柱電極。Ahn等人(5.491.103號美國專利)也提出一種雙皇 冠型電容器的形成方法，需要在制定圖案後的光阻層上沉積一 (請先閲讀背面之注意事項再填寫本頁) 裝 ,11 缘 本紙張尺度適用中國國家標準（CMS ) A4規格（210X 297公釐） 經濟部中央標準局員工消費合作社印裝 A7 -___ B7 五、發明説明（汐） "~' 層低溫氧化物(LTO)，形成側壁，才不致使光阻的影像失眞。 去除光阻後，就沉積一層導電層，回蝕刻後即形成皇冠型的電 極。另一個方法是由Kim等人(5,438,013號美國專利)提出來 的，藉著控制凹削(undereut)形成雙側壁的光罩，然後在用此 光罩在導電層中形成雙圓柱的電極。但是，電容器的間隔與大 小都由凹削來控制。而且，Ahn和Kim都是在形成電容器節點 接觸窗以外，以額外的光罩與蝕刻步驟形成位元線接觸，都需 要額外的光罩步驟。 因此，在半導體業界仍然殷切地需要新的方法，可以避免 上述的各種問題，製造出更可靠、電容値更高的DRAM儲存電 容器。 發明的簡要說明 因此，本發明的主要目的是提出一種具有雙皇冠型電容器、電 容値更高的動態隨機存取記憶體(DRAM)陣列。 本發明另一個目的是在製造這些雙皇冠型電容器時，同時蝕刻 位元線接觸與電容器節點接觸，並且填上頂面具有矽化物層的複晶 砂層，最後制定圖案後，同時形成位元線與節點接觸。 接下來將說明本發明具有雙皇冠型儲存電容器之動態隨機存取 記憶體細胞元的製造方法。這個方法，也可以同時蝕刻出位元線的 接觸與儲存電容器的節點接觸。然後再以一層第二複晶矽化物眉， 形成節點接觸與位元線。 這個方法開始時，首先要在半導體基板上製作出元件區的陣 列，可用的基板有摻有P型導電雜質(如硼)的單晶矽。形成元件區 時，要形成相當厚的場氧化物圍繞在各個元件區周圍’使它們彼此 隔離。形成這些場氧化物區的—個方法是’先用氮化砂(&3&)層保 ------·,--Τ--.β------訂 (請先閲讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） 經濟部中央標準局員工消費合作社印製 A7 __B7 五、發明説明（//) 護元件區，使它們不致受到氧化，再進行熱氧化，在砂基板上形成 場氧化區。這種方法在半導體業界通稱爲矽的局部氧化(LOCOS)。 氮化砂層去除後，元件區上要形成一層薄薄的閘極氧化物，接著沉 積一層第一複晶矽化物後，再沉積第一絕緣層。第一絕緣眉與第一 複晶矽化物層制定圖案後，就在元件區上形成了場效電晶體(FET) 的閘極。制定圖案後的複晶矽化物層中有一部份會跨過場氧化物， 即作爲字元線。閘極的兩側，利用離子植入形成淡摻雜汲極(LDD) 區，接著再沉積一層保型的第二絕緣層，並非均向性地回蝕刻這層 第二絕緣層，就形成了絕緣的側壁空間子。然後將N+型的雜質植 入到側壁空間子的兩側，形成源極/汲極區。這樣，就完成了用來 形成DRAM細胞元內傳送電晶體陣列的FET陣列。 繼續本發明的方法，接下來一連串的步驟是用一層第二複晶矽 化物層形成位元線，並同時形成電容器的複晶矽節點接觸。首先沉 積一層第三絕緣層，並予以平坦化，然後在第三絕緣層上沉積一屑 第一複晶矽層，並以非均向性的電漿蝕刻制定第一複晶矽眉的圖 案。而且，蝕刻會一直持續，直到第三絕緣層位於閘極邊元件區上 的部位略爲凹陷。接著沉積一層保型的第二複晶矽層，並以非均向 性的回蝕刻，在第一凹陷區域的側壁上形成複晶矽空間子。以制定 圖案後的第一複晶矽層與複晶矽空間子作爲蝕刻光罩，非均向性地 蝕去第一凹陷區域內的第三絕緣層後，同時形成了位元線接觸窗與 電容器節點接觸窗。然後沉積一層第三複晶矽層，完全填滿這兩種 接觸窗。在此第三複晶矽層上，接著沉積一層矽化鎢(WSi2)等類的 矽化物，並在矽化物層上沉積一層氮化矽(Si3N4)層，然後制定氮化 矽、矽化物與第三複晶矽等層所形成的多層結構的圖案，形成位元 線，並在電容器的節點接觸窗內留下部份的第三複晶矽層。最後， 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公痠） (請先閲讀背面之注意事項再填寫4頁) ★, 1T Paper Chinese Standard Common Chinese National Standard (CNS) A4 Specification (210X297 mm) Printed by the Consumers' Cooperative of the Shiyang Standard Bureau of the Ministry of Economic Affairs A7 __B7 V. Description of the Invention (〇?) To improve the circuit function, it is necessary to maintain a reasonable The size of the wafer, it is necessary to further reduce the area of each cell. After the cell size shrinks, it is difficult to make a stacked capacitor with sufficient capacitance, and the stored charge is also difficult to reach the signal-to-noise ratio that can be detected by a reading circuit (sense amplifier). As a result of the reduced charge, it is necessary to increase the frequency of renewal cycles of regular re-storage of charges in these volatile storage cells. Since the DRAM chip contains many cells, the area of the capacitor is limited by the size of the cell. To increase the capacitance, other methods need to be found. The area occupied by the capacitor on the substrate surface may not be increased. At present, there have been many reports in the literature of three-dimensional stacked storage capacitors that can increase the capacitance. For example, U.S. Patent No. 5,399,518 to Sim et al. Proposes a method for forming a storage capacitor having a double cylindrical wall. In this method, the bit line contacts are etched to form an insulated bit line, and then a second array formed by the contact windows of the capacitor node contacts is etched. Then, a thick polycrystalline silicon layer is deposited in the contact window of the node and other places on the substrate to form the electrode of the storage capacitor. After forming a photomask for forming an outer cylinder and a photomask for forming an inner cylinder on the polycrystalline silicon layer, these photomasks were used to form a bi-cylindrical electrode. Sim et al. Used a conductive layer to form the electrodes. U.S. Patent No. 5,443,993 to Park et al. Also proposes a method for forming DRAM cells, first forming bit lines, and then etching out a second array of 歹 IJs as contact windows for node contact. Then, Park used an insulating spacer on the established conductive layer to dig out a portion of the conductive layer, and then deposited a second conductive layer, which was not etched back isotropically to form a cylindrical electrode. Finally, the insulated sidewalls are removed to form a free-standing cylindrical electrode. Ahn et al. (U.S. Patent No. 5.491.103) also proposed a method for forming a double crown type capacitor, which needs to be deposited on the photoresist layer after the pattern is made (please read the precautions on the back before filling this page). The size of the paper is applicable to the Chinese National Standard (CMS) A4 (210X 297 mm), printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 -___ B7 V. Description of the Invention (Xi) " ~ 'Layer Low Temperature Oxide (LTO ) To form a side wall, so that the image of the photoresist is not lost. After the photoresist is removed, a conductive layer is deposited and a crown-shaped electrode is formed after etch back. Another method is proposed by Kim et al. (U.S. Patent No. 5,438,013) to form a double-sided photomask by controlling undereut, and then use this photomask to form a double-cylinder electrode in a conductive layer. However, the spacing and size of the capacitors are controlled by the undercut. In addition, both Ahn and Kim are in addition to forming the contact window of the capacitor node, and forming the bit line contact with an additional mask and etching step requires an additional mask step. Therefore, a new method is still eagerly needed in the semiconductor industry, which can avoid the above-mentioned problems and produce a more reliable and higher capacity DRAM storage capacitor. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to propose a dynamic random access memory (DRAM) array with a double crown type capacitor and a higher capacitance. Another object of the present invention is to simultaneously etch the bit line contact with the capacitor node while manufacturing these double crown type capacitors, and fill in a polycrystalline sand layer with a silicide layer on the top surface. After the pattern is finally formulated, bit lines are formed simultaneously Contact with nodes. Next, a method for manufacturing a dynamic random access memory cell with a double crown type storage capacitor according to the present invention will be described. In this method, the contact of the bit line and the node contact of the storage capacitor can be etched at the same time. Then a second layer of polycrystalline silicide is used to form a node contact and a bit line. At the beginning of this method, an array of element regions must first be fabricated on a semiconductor substrate. A usable substrate is a single crystal silicon doped with a P-type conductive impurity (such as boron). When forming the element region, a relatively thick field oxide is formed to surround each element region 'to isolate them from each other. One way to form these field oxide regions is to 'first use nitride nitride (& 3 &) layers to protect ------ ,,-T-. Β ------ order (please first Read the notes on the reverse side and fill out this page) This paper size is applicable to Chinese National Standard (CNS) Α4 size (210X 297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 __B7 V. Description of Invention (//) Protection The element region is protected from oxidation, and then thermal oxidation is performed to form a field oxidation region on the sand substrate. This method is commonly known in the semiconductor industry as Local Oxidation of Silicon (LOCOS). After the nitrided sand layer is removed, a thin gate oxide is formed on the element region, and then a first polycrystalline silicide is deposited, and then a first insulating layer is deposited. After the first insulating eyebrow and the first compound silicide layer are patterned, a gate of a field effect transistor (FET) is formed on the element region. A part of the patterned polycrystalline silicide layer will cross the field oxide, which is referred to as a word line. On both sides of the gate electrode, a lightly doped drain (LDD) region is formed by ion implantation, and then a conformal second insulating layer is deposited. The second insulating layer is not etched back isotropically to form Insulated sidewall spacer. N + -type impurities are then implanted on both sides of the side wall spacer to form a source / drain region. Thus, a FET array for forming an intra-transistor transistor array in a DRAM cell is completed. Continuing the method of the present invention, the next series of steps is to form a bit line with a second polycrystalline silicide layer and simultaneously form a polycrystalline silicon node contact for the capacitor. A third insulating layer is deposited and planarized first, and then a chip of the first polycrystalline silicon layer is deposited on the third insulating layer, and the pattern of the first polycrystalline silicon eyebrow is formulated by anisotropic plasma etching. Moreover, the etching will continue until the portion of the third insulating layer on the gate-side element region is slightly recessed. Next, a conformal second polycrystalline silicon layer is deposited and anisotropically etched back to form a polycrystalline silicon spacer on the sidewall of the first recessed region. The patterned first polycrystalline silicon layer and the polycrystalline silicon space element are used as an etching mask. After the third insulating layer in the first recessed area is etched anisotropically, a bit line contact window and Capacitor node contact window. A third polycrystalline silicon layer is then deposited to completely fill the two contact windows. On this third polycrystalline silicon layer, a layer of silicide such as tungsten silicide (WSi2) is then deposited, and a layer of silicon nitride (Si3N4) is deposited on the silicide layer, and then silicon nitride, silicide, and silicon A pattern of a multi-layer structure formed by three layers of triple-crystal silicon, etc., forms bit lines, and a portion of the third multiple-crystal silicon layer is left in the node contact window of the capacitor. Finally, this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 male acid) (Please read the precautions on the back before filling in 4 pages) ★
•tT 線 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（f) 沉積一層第二Si3N4層，回蝕刻後，在位元線的側壁上形成了氮化 砂空間子。 繼續本發明的方法，接下來要形成的是DRAM細胞元陣列的雙 皇冠型電容器。接下來，在由氮化矽絕緣的位元線上沉積一層保型 的第四複晶矽層，並且延伸到節點接觸窗的內部與上方，形成通往 第三複晶矽層的電性接觸。在第四複晶矽層上，沉積一層相當厚的 第四絕緣層，並利用熱回整(thermal reflow)或化學/機械拋光等其 中一種方法予以平坦化。藉由光阻光罩與非均向性的蝕刻，蝕刻平 坦的第四絕緣層的一部份，留下節點接觸上的部位未加蝕刻，在基 板上的其他部位形成第二凹陷區域。環繞在未加蝕刻區域的周邊所 定義出來的區域，就是即將形成雙皇冠型電容器的位置。接著沉積 一層第五複晶矽層，非均向性地回蝕刻後，就在第二凹陷區域的側 壁上形成了複晶矽空間子。現在，利用複晶矽空間子作爲蝕刻光 罩，在氧化物對複晶矽的蝕刻選擇性爲1 : 1的蝕刻氣體中，以非均 向性的蝕刻，進一步蝕刻由氧化矽(Si02)等類材料作成的第四絕緣 層，直到第四複晶矽層。這樣，會在第五複晶矽層所形成的複晶矽 空間子底下，形成狭窄的垂直絕緣區。接著去除複晶矽空間子，並 連帶著去除部份的第四複晶矽層，直到第一Si3N4層。現在要形成 電容器底部電極的雙皇冠部份。先沉積一層保型的第六複晶砂層， 並進行非均向性的全面回蝕刻，在狭窄的垂直絕緣區上形成了複晶 砂雙皇冠側壁空間子。然後相對於露出來的複晶矽與Si3N4，蝕刻 由5102等類材料所組成的狭窄的垂直絕緣區。這樣一來，就完成了 雙皇冠電容器的底部電極陣列。現在，利用傳統的方法，沉積一眉 介電常數很高的介電薄層，並沉積一層濃摻雜複晶矽之類的導電 層，就完成了DRAM細胞元的電容器陣列。雙皇冠型電容器的電容 ------；—；—^— (請先閱讀背面之注意事項再垓寫本頁) 訂 東 本纸張尺度適用中國國家標準（CNS ) A4規格（210X29?公釐） A7 B7 經濟部中央標準局員工消费合作社印裝 五、發明説明（z) 値，比起傳統堆疊式的電容器’要高出三倍。 圖式說明： 底下將參照附圖與實施例，詳細說明本發明。所附附圖分別 爲： 圖1至圖15的橫剖面圖係DRAM細胞元陣列的一部份說明了本 發明的方法中，製作具有雙皇冠型儲存電容器之dram細胞元的一 連串製程步驟。這些橫剖面圖中，說明了兩個具有雙皇冠型電容器 的記憶體細胞元和一個共同的位元線。 圖16是習知技藝中，一個典型堆疊式電容器的示意圖。 圖17是一個與圖16中的電容器具有一樣外圍大小的雙皇冠型 電容器的示意圖。 發明的詳細說明 現在，將參照圖1製圖15仔細說明本發明具有雙皇冠型電容器 的DRAM細胞元製造方法。DRAM細胞元通常都製作在P摻雜的半 導體基板上，並以N通道場效電晶體作爲各個DRAM細胞元的傳送 電晶體。熟習這項技藝的人應該瞭解，除了這個實施例中所說明的 步驟之外，只需再加上額外的製程步驟，就可以在DRAM的晶片上 製作其他類型的元件。舉例來說，可以在P摻雜基板內形成N型井 區，然後製作P通道的FET，以形成作爲DRAM晶片上之周邊電路 的互補式金氧半(CMOS)電路。 .參閱圖1中，只畫出具有部份完成之DRAM細胞元的半導體基 板10的一部份。圖中所畫出的記憶體細胞元中，在基板表面的主動 區內，有兩個傳送電晶體(N-FET):比較理想的基板，通常是用淡 摻雜的P型單晶矽，結晶方向最好爲<1〇〇〉。製作記憶體細胞元的 各個元件區周圍都環繞著相當厚的場氧化物(FOX)12，使彼此電性 ------.—.—裝------訂 (請先閲讀背面之注意事項再填寫本頁> 本紙張尺度適用中國國家標準（CNS ) A4規格（2HTX297公釐） A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（/ ) 隔離。場氧化物12在圖1中只畫出一部份，通常都是利用矽的局部 氧化(LOCOS)所形成的。雖然在圖冲沒有說明形成FOX的各個步 驟，但大家熟知的LOCOS方法中，首先要在基板表面上沈積一層 薄薄的Si02(墊層氧化物）和一層厚厚的氮化矽(Si3N4)，作爲氧化 障蔽層，然後用傳統的微影技術和蝕刻去除想形成場氧化物之區域 上的障蔽層，而將Si3N4留在將作爲主動元件區的部位上。然後對 砂基板進行熱氧化，形成了場氧化物區12。這層氧化物通常厚約 3000至6000埃。 以濕蝕刻去除Si3N4障蔽層與墊層氧化物後，現在要再主動元 件區中形成N通道FET。舉例來說，氮化物可以利用溫度約爲180°C 的熱磷酸(h3po4)加以去除，而墊層氧化物可用氫氟酸與水的稀釋 溶液(HF/H20)去除。接著對主動元件區進行熱氧化，形成圖1中 薄薄的閘極氧化物14，作爲N-FHT的閛極氧化物。這層閘極氧化物 14的厚度一般約爲50至150埃。 接下來同樣在圖1中，藉由沉積一層第一複晶矽化物眉20，形 成了元件區中的FET閘極與場氧化物12上互連的字元線。一般說 來，複晶矽化物20是以低壓化學氣相沉積法(LPCVD)與砂焼等類的 反應氣體所沉積的複晶矽層，並以高濃度的N型雜質加以接雜。要 完成複晶矽化物層20，要在複晶矽層上沉積一層矽化鎢(WSi2)之類 的矽化物層，沉積時可用CVD與六氟化鎢之類的反應氣體。雖然 是以兩個步驟加以完成，但爲了簡化附圖，附圖中都以單一的膜層 來表示此複晶矽化物層20 :通常N摻雜的複晶矽層厚約500至1500 埃，而WSi2也厚約5⑻至15⑻埃。接下來，在複晶矽化物層20上沉 積一層氧化矽(Si02)之類的第一絕緣層22。然後用圖1中制定好的光 阻層24，遮蔽住將形成閘極與字元線之區域上的第一絕緣層22與第 ------一—^^— (請先閔讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS ) A4現格（210X297公釐）• tT line A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (f) After depositing a second layer of Si3N4, after etching back, a nitrided nitride space is formed on the side wall of the bit line. Continuing the method of the present invention, the next thing to be formed is a double crown type capacitor of a DRAM cell array. Next, a conformal fourth polycrystalline silicon layer is deposited on the bit line insulated by silicon nitride, and extends to the inside and above the node contact window to form an electrical contact to the third polycrystalline silicon layer. On the fourth polycrystalline silicon layer, a relatively thick fourth insulating layer is deposited and planarized by one of methods such as thermal reflow or chemical / mechanical polishing. Through the photoresist mask and the anisotropic etching, a part of the flat fourth insulating layer is etched, leaving no contact on the part in contact with the node, and forming a second recessed area on other parts of the substrate. The area defined around the periphery of the unetched area is where the double crown capacitor will be formed. Next, a fifth polycrystalline silicon layer was deposited and anisotropically etched back to form a polycrystalline silicon spacer on the side wall of the second recessed area. Now, using the polycrystalline silicon space element as an etching mask, in an etching gas having an etching selectivity of 1: 1 by the oxide, the silicon oxide (Si02) and the like are further etched with anisotropic etching. A fourth insulating layer made of a similar material up to the fourth polycrystalline silicon layer. In this way, a narrow vertical insulating region is formed under the polycrystalline silicon space formed by the fifth polycrystalline silicon layer. Next, the polycrystalline silicon spacer is removed, and a portion of the fourth polycrystalline silicon layer is removed together to the first Si3N4 layer. It is now time to form the double crown portion of the bottom electrode of the capacitor. A conformal sixth polycrystalline sand layer was deposited first, and anisotropic full etch-back was performed to form a double-crown sidewall spacer of polycrystalline sand on a narrow vertical insulation region. Then, with respect to the exposed polycrystalline silicon and Si3N4, a narrow vertical insulating region composed of 5102 and other materials is etched. In this way, the bottom electrode array of the double crown capacitor is completed. Now, using conventional methods, a thin dielectric layer with a high dielectric constant is deposited, and a conductive layer such as heavily doped polycrystalline silicon is deposited to complete the capacitor array of DRAM cells. Capacitance of Double Crown Capacitors ------; —; — ^ — (Please read the notes on the back before writing this page) The paper size of this book applies to the Chinese National Standard (CNS) A4 specification (210X29? A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of Invention (z) 値, which is three times higher than the traditional stacked capacitors. Description of the drawings: The present invention will be described in detail below with reference to the drawings and embodiments. The attached drawings are as follows: Figures 1 to 15 are cross-sectional views of a part of a DRAM cell array illustrating a series of process steps in the method of the present invention for making a dram cell having a double crown type storage capacitor. These cross-sectional views illustrate two memory cell cells with a double crown-type capacitor and a common bit line. FIG. 16 is a schematic diagram of a typical stacked capacitor in the conventional art. FIG. 17 is a schematic diagram of a double crown type capacitor having the same peripheral size as the capacitor in FIG. 16. FIG. DETAILED DESCRIPTION OF THE INVENTION Now, a method of manufacturing a DRAM cell having a double crown type capacitor according to the present invention will be described in detail with reference to Figs. DRAM cells are usually fabricated on a P-doped semiconductor substrate, and an N-channel field effect transistor is used as the transmission transistor for each DRAM cell. Those skilled in the art should understand that in addition to the steps described in this embodiment, other types of components can be fabricated on a DRAM chip by adding additional process steps. For example, an N-type well region can be formed in a P-doped substrate, and then a P-channel FET can be fabricated to form a complementary metal-oxide-semiconductor (CMOS) circuit as a peripheral circuit on a DRAM wafer. Referring to Fig. 1, only a portion of a semiconductor substrate 10 having a partially completed DRAM cell is drawn. In the memory cell shown in the figure, in the active area of the substrate surface, there are two transmission transistors (N-FETs): a more ideal substrate, usually a lightly doped P-type single crystal silicon, The crystallization direction is preferably < 100. Each element area of the memory cell is surrounded by a fairly thick field oxide (FOX) 12, which makes each other electrically ---------------------------- Order (Please read first Note on the back, please fill out this page again> This paper size applies to Chinese National Standard (CNS) A4 specification (2HTX297 mm) A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Inventory (/) Isolation. Field oxidation Object 12 is only shown in part in Figure 1. It is usually formed by the local oxidation of silicon (LOCOS). Although the various steps of forming FOX are not described in the figure, the well-known LOCOS method first requires Deposit a thin layer of SiO2 (pad oxide) and a thick layer of silicon nitride (Si3N4) on the surface of the substrate as an oxide barrier layer, and then use traditional lithography techniques and etching to remove the area where the field oxide is to be formed A barrier layer is left on the substrate, leaving Si3N4 on the site that will be the active device region. The sand substrate is then thermally oxidized to form the field oxide region 12. This layer of oxide is usually about 3000 to 6000 angstroms thick. Wet etching Remove Si3N4 barrier layer and pad oxide Later, it is now necessary to form an N-channel FET in the active device region. For example, the nitride can be removed by using hot phosphoric acid (h3po4) at a temperature of about 180 ° C, and the pad oxide can be diluted with hydrofluoric acid and water. The solution (HF / H20) is removed. Then, the active device region is thermally oxidized to form the thin gate oxide 14 in FIG. 1 as the ytterbium oxide of N-FHT. The thickness of this layer of gate oxide 14 is generally It is about 50 to 150 Angstroms. Next, in FIG. 1, by depositing a layer of the first polycrystalline silicide eyebrow 20, the word lines interconnecting the FET gate and the field oxide 12 in the element region are formed. Generally speaking, the polycrystalline silicide 20 is a polycrystalline silicon layer deposited by a low pressure chemical vapor deposition method (LPCVD) and a reaction gas such as sand and the like, and is doped with a high concentration of N-type impurities. To be completed In the polycrystalline silicide layer 20, a silicide layer such as tungsten silicide (WSi2) is deposited on the polycrystalline silicon layer, and a reactive gas such as CVD and tungsten hexafluoride can be used for deposition. Although it is applied in two steps Completed, but in order to simplify the drawings, the single crystal layer is used to represent the complex silicidation in the drawings Physical layer 20: Generally, the N-doped polycrystalline silicon layer is about 500 to 1500 angstroms thick, and WSi2 is also about 5 to 15 angstroms thick. Next, a layer of silicon oxide (Si02) or the like is deposited on the polycrystalline silicide layer 20 The first insulating layer 22. Then, the photoresist layer 24 prepared in FIG. 1 is used to shield the first insulating layer 22 and the first -------- one on the area where the gate and the word line will be formed. ^ — (Please read the notes on the reverse side before filling out this page) The size of the paper is applicable to China National Standard (CNS) A4 (210X297 mm)
經濟部中央檁準局員工消費合作杜印U A7 ___B7 五、發明説明（，） ^ 一複晶矽化物眉20。 在圖2中，隨即利用光阻層24，以非均向性蝕刻制定絕緣眉22 與複晶矽化物層20的圖案，形成閘極3與字元線5。舉例來說，蝕刻 Si02組成的第一絕緣雇22時，可以在反應離子蝕刻機中，利用四氟 化碳(CF4)作爲蝕刻氣體，而蝕刻複晶矽化物20時，可以利用氯氣 (Cl2)或二氯二氟甲烷(CC12F2)等含氯氣體，加上氬(Ar)等承載氣體 的反應離子蝕刻_)。 同樣在圖2中，接著在緊鄰閘極3處，以離子植入形成淡摻雜 汲極(LDD)區17。舉例來說，形成LDD時，可以在矽基板10內植入 砷(As75)之類的N+雜質。雜質的割量一般約在1.ΟΧΙΟ15至1.0X1016 離子/平方公分之間，植入能量約在20至40KeV之間。接著沉積一 層第二絕緣層26，並非均向性地回蝕刻至矽基板10，在複晶矽化物 20所形成的閘極旁形成了圖2中標爲26的絕緣側壁空間子。然後以 離子植入，在側壁空間子26旁的元件區植入高濃度的雜質，形成源 極/汲極接觸區19。或者可以在稍後的製程中，由複晶矽層往外擴 散N+雜質，來形成濃摻雜的源極/汲極區。這樣，便完成了 DRAM細胞元FET傳送電晶體的陣列。 底下將參照圖3至圖7，說明同時形成位元線與雙皇冠型儲存 電容器之節點接觸的方法。圖3中，在FET陣列上沉積了一層第三 絕緣層28，使表面得以平坦化。這眉絕緣眉最好是氧化砂。舉例來 說，可以利用硼磷矽酸鹽玻璃(BPSG)之類摻雜了硼與磷的低回整 溫度的玻璃，然後再進行熱回火使其平坦化。或者，也可以使用未 經接雜的Si02，然後再以化學/機械拋光，使第三絕緣層28得以平 坦化。膜層28最好利用四乙基矽酸鹽(TEOS)之類的氣體作爲反應 氣體，用LPCVD沉積而成，可以加以摻雜，也可以未加摻雜，厚 (請先閲讀背面之注意事項再填寫本頁) -¾. 訂 線！ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作杜印製 A7 B7 五、發明説明（/> 度約在500至1500埃之間。現在要在圖3中平坦的第三絕緣層28 上，沉積一層第一複晶矽眉30。複晶矽眉3Q最好由LPCVD沉積而 成，可用的反應氣體有矽院(SiH4)等。膜層30可以是N+摻雜，也可 以未加摻雜，最好厚約5〇〇至1500埃。接著利用傳統的微影技術塗 佈並制定一雇光阻層32，在即將形成位元線接觸與電容器的節點接 觸之部位的元件區上，留下窗口。 圖3中制定好的光阻眉32，現在作爲蝕刻光罩，以進行非均向 性的蝕刻，先制定第一複晶矽屑30的圖案，然後部份蝕入第三絕緣 層28，而形成圖4中的凹陷區7。舉例來說，這次的蝕刻可以利用 RIE進行，可用的蝕刻氣體有三氟甲烷(CHF3)或四氟化碳CF4。膜 層28凹陷的深度最好約在1000至2000埃之間。 圖5中，沉積了一層保學的第二複晶矽層34，加以非均向性地 回蝕刻後，就在制定好的第一複晶矽層30的側壁上，以及絕緣層28 凹陷區的側壁上，形成了同樣標爲34的複晶砂空間子。複晶砂層34 最好由LPCVD利用矽烷沉積而成，並經N+濃摻雜，濃度約在1.0X 1019至1.0 X1021離子/立方公分之間。膜層34的厚度最好約在500 至1500埃之間。接著利用複晶矽眉30與側壁空間子34作爲蝕刻光 罩，對第三絕緣層28進行非均向性的蝕刻，直到基板10的表面。這 樣一來，同時形成了位元線接觸窗8與電容器節點接觸窗9，而且側 壁空間子34可以縮小接觸窗的大小，也提高了元件集積的密度。 現在在圖6中，沉積了一層第三複晶矽層36，完全填滿位元線 與節點的接觸窗，而且繼續沉積到足以在接觸窗之上形成相當平坦 的表面。膜層36最好經N+满摻雜，濃度約在1.0X1019至1.ΟΧΙΟ21離 子/立方公分之間，並且最好厚約1〇〇〇至2500埃之間。爲了提高位 元線的導電性，可以在膜層36上沉積一層第二矽化物眉38。舉例來 (請先閲讀背面之注意事項再填寫本頁) 訂 ^ 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明說明（/Ρ ) 說，矽化物層38可以用矽化鎢(WSi2)組成，厚約500至1500埃。舉 例來說，以812可以用六氟化鎢(WFg)以CVD沉積而成。接著在矽化 物層38上沉積一層Si3N4層40。舉例來說，膜層40可以用LPCVD沉 積而成，可用有二氯矽烷(SiC12H2)和氨(NH3)作爲反應氣體，溫度 約在700至800°C之間。膜層40最理想的厚度約在1000至2000埃之 間。最後制定一層光阻42，以便定義DRAM細胞元的位元線與節點 接觸。 現在以制定好的光阻42作爲蝕刻光罩，蝕刻氮化矽層40、矽 化物層38與第三複晶矽層36所組成的多層結構，形成了位元線。多 層結構經非均向性地蝕刻直到第三絕緣層28的表面後，就形成了圖 7中的位元線2，同時也在節點接觸窗9內留下部份的膜層36，形成 電容器的接觸。 接著在圖8中，沉積了一層第二氮化矽層44，加以非均向性地 回蝕刻後，在位元線2的側壁上形成了同樣標爲44的氮化矽空間 子。Si3N^積的方法與沉積膜層40類似。Si3N4層40與側壁空間子 44，使位元線2得以與集積電路中形成雙皇冠型儲存電容器的下一 層金屬隔離。 現在將參照圖9至圖15，說明本實施例的其餘步驟，特別是關 於製造DRAM元件之雙皇冠儲存電容器的方法。爲了達成本發明的 目的，我們使用了複晶矽空間子作爲蝕刻光罩，從複晶矽側壁底下 的絕緣材料蝕刻出狭窄的垂直結構。這些側壁即成爲儲存電容器底 部電極的垂直雙皇冠結構。圖9中，在絕緣後的位元線上全面性地 沉積一層保型的第四複晶矽層46，這層複晶矽並同時接觸到節點接 觸窗9內的複晶矽層％。沉積複晶矽層46最好的方法是類似於沉積 膜層36的方法，並經Ν+的濃摻雜，以提高導電性。膜屑46厚約 本紙張尺度適用中國國家標準（CNS ) Α4規格（2ΐ〇χ 297公釐） ：---：—^------1T------^ I (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7_： 五、發明説明（//) 、 1500至2500埃。 圖9中，接著在第四複晶矽層46上沉積一層相當厚的第四絕緣 層48。膜層48最好由Si02組成。舉例來說，可以使用TEOS經由 LPCVD沉積而成。絕緣層48厚約8000至12000埃，並且舉例來說， 可經由化學/機械拋光的方式加以平坦化。或者，可以使用BPSG 之類低回整溫度的氧化物，然後透過熱回整回火加以平坦化。圖9 的光阻光罩50是由傳統的微影技術形成的，有一部份位於節點接觸 窗9之上，定義出即將形成底部電極的區域。 現在如圖10，利用光阻光運50，以非均向性的蝕刻制定絕緣 層48的圖案。這道非均向性的蝕刻最好在反應離子蝕刻機或其他高 電漿密度的蝕刻機內進行，並使用四氟化碳(CF4)之類的含氟氣 體。然後以傳統的方式去除光阻層，留下未經触刻的膜層48在節點 接觸9的上方，並在膜層48的其他部位形成第二凹陷區域11。凹陷 區11的深度最好約在2500至4000埃之間。 製程繼續下去，在制定好、具有凹陷區U的第四絕緣層48 上，沉積一層保型的第五複晶矽層52，加以非均向性地回蝕刻之 後，在圖H)中凹陷區11的側壁上，形成了複晶矽空間子52 °膜屑52 是以LPCVD沉積而成的，最好未經摻雜。膜層52的厚度需要加以 選擇，確使蝕刻後所形成側壁空間子52的寬度約在500至1000埃之 間° 接著在圖U中，對第四絕綠層48進行非均向性的電漿蝕刻’ 直到位於非凹陷區丨丨(圖⑴)的第四複晶矽層46表面。因爲有複晶矽 側壁空間子52的遮蔽，使得蝕刻的結果形成了狭窄的垂直區域54。 這道非均向性的電漿蝕刻是本發明的重要步驟，實施時’應使複晶 砂與第四絕緣層之間的蝕刻選擇率爲丨：1。舉例來說，如果第四絕 -----：---^—社衣------ΪΤ------後‘ (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS ) A4規格（210:<297公釐） 經濟'部中央標準局員工消費合作社印製 A7 B7 五、發明説明（/y) \ 緣層是氧化矽，要達成〗：1的選擇性，最好在反應離子蝕刻機或高 密度的電漿蝕刻機內進行蝕刻，並使用低壓的CHF3或CF4之類的 ·. 混合蝕刻氣體。當鈾刻膜層48直到非凹陷區10之膜層46表面時，.凹 陷區11中的複晶矽層46會被蝕去相當多的厚度，使圖11中凹陷區域 內的複晶矽層46更薄。這對本發明非常重要，因爲如果凹陷區的深 度約等於第四複晶矽層46的厚度，那麼利用比例1 : 1的蝕刻率，就 可以完全去除凹陷區域11內的膜層46。這樣一來，就可以形成彼此 電性隔離的底部電極陣列，這從圖12可以更清楚地看出來。 圖12中，接著以電漿蝕刻去除複晶矽空間子52剩餘的部份(如 圖11)，並且稍稍地蝕去非凹陷區域10內的複晶矽層46，確保凹陷 區域11內任何殘餘的複晶矽層46都完全去除，直到第_Si3N4層40 的表面。這樣一來，剩餘複晶矽層46所形成的DRAM細胞元上，各 相鄰的底部電極之間就得以電性隔離。去除空間子52的最理想的電 漿蝕刻，在複晶矽與氮化矽之間具有極高的触刻選擇性。舉例來 說，這道蝕刻可以在反應離子蝕刻機中進行，並使用氯氣(cy與溴 化氫(HBr)的混合氣體，作爲蝕刻氣體。 圖13中，沉積了一層保型的第六複晶矽層56，開始製作電容 器底部電極的雙皇冠部份。保型的複晶矽層會均勻地塗佈在狭窄的 垂直絕緣結構54上。第六複晶矽層56最好是用LPCVD沉積而成 的，而且舉例來說，可以用矽烷(SiH4)作爲反應氣體，並在沉積的 同時，加入膦(PH4)進行的同步濃摻雜。膜層56中的雜質濃度最 好約在1.0X 101QSU)X 102灕子/立方公分之間。膜層56的厚度最 好約在50U至10UU埃之間，而以5〇()埃最爲理想。 圖W中，第六複晶矽層56經非均向性地回蝕刻後，露出了狭 窄的垂直絕緣結構54的頂面，同時並去除了凹陷區域11內的膜層 ：I裝-- (請先鬩讀背面之注意事項再填寫本頁)Du Yin U A7 ___B7, Consumer Co-operation of Employees of the Central Government Bureau of the Ministry of Economic Affairs V. Description of the Invention (,) ^ A compound silicide eyebrow 20. In FIG. 2, the photoresist layer 24 is then used to form a pattern of the insulating eyebrows 22 and the polycrystalline silicide layer 20 by anisotropic etching, so as to form the gate electrode 3 and the word line 5. For example, when etching the first insulator 22 composed of Si02, carbon tetrafluoride (CF4) can be used as an etching gas in a reactive ion etching machine, and when the polycrystalline silicide 20 is etched, chlorine (Cl2) can be used. Or chlorine ion-containing gas such as dichlorodifluoromethane (CC12F2), and reactive ion etching with a carrier gas such as argon (Ar). Also in FIG. 2, next to the gate 3, a lightly doped drain (LDD) region 17 is formed by ion implantation. For example, when LDD is formed, N + impurities such as arsenic (As75) can be implanted in the silicon substrate 10. The cut-off amount of impurities is generally between 1.0 × 1015 and 1.0 × 1016 ions / cm 2, and the implantation energy is between 20 and 40 KeV. Next, a second insulating layer 26 is deposited, which is not etched back to the silicon substrate 10 isotropically, and an insulating sidewall spacer labeled 26 in FIG. 2 is formed beside the gate formed by the polycrystalline silicide 20. Then, by ion implantation, a high concentration of impurities is implanted in the element region next to the side wall spacer 26 to form a source / drain contact region 19. Alternatively, in a later process, a N + impurity is diffused from the polycrystalline silicon layer to form a heavily doped source / drain region. In this way, an array of DRAM cell FET transfer transistors is completed. A method of simultaneously forming a bit line contact with a node of a double crown type storage capacitor will be described below with reference to FIGS. 3 to 7. In Fig. 3, a third insulating layer 28 is deposited on the FET array to planarize the surface. The insulated eyebrow is preferably oxidized sand. For example, low tempering glass doped with boron and phosphorus, such as borophosphosilicate glass (BPSG), can be used and then tempered to flatten it. Alternatively, it is also possible to use un-doped SiO 2 and then chemical / mechanical polishing to flatten the third insulating layer 28. The film layer 28 is preferably formed by using a gas such as tetraethyl silicate (TEOS) as a reaction gas, and is deposited by LPCVD. It can be doped or undoped and thick (please read the precautions on the back first) Fill out this page again)-¾. Order! This paper size applies to China National Standard (CNS) A4 (210X297 mm). The consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs has printed A7 B7. 5. Description of the invention (/ > Degree is between 500 and 1500 Angstroms. On the flat third insulating layer 28 in Fig. 3, a layer of a first polycrystalline silicon eyebrow 30 is deposited. The polycrystalline silicon eyebrow 3Q is preferably deposited by LPCVD, and a usable reaction gas is silicon courtyard (SiH4), etc. 30 may be N + -doped or un-doped, preferably about 500 to 1500 angstroms. Then, a conventional photolithography technique is used to coat and formulate a photoresist layer 32, which will soon form a bit line contact. A window is left on the component area of the portion in contact with the node of the capacitor. The photoresist eyebrow 32 formulated in Figure 3 is now used as an etching mask to perform anisotropic etching. 30 pattern, and then partly etch into the third insulating layer 28 to form the recessed area 7 in Fig. 4. For example, this etching can be performed by RIE, and the available etching gas is trifluoromethane (CHF3) or tetrafluoromethane. Carbon CF4. Depth of film layer 28 is preferably between 1000 and 2000 Angstroms In FIG. 5, a second polycrystalline silicon layer 34 is deposited, which is etched back anisotropically. Then, the sidewalls of the first polycrystalline silicon layer 30 and the insulating layer 28 are recessed. On the side walls of the zone, a polycrystalline sand space is also labeled as 34. The polycrystalline sand layer 34 is preferably deposited by LPCVD using silane, and is doped with N +. The concentration is about 1.0X 1019 to 1.0 X1021 ion / Between cubic centimeters. The thickness of the film layer 34 is preferably between 500 and 1500 angstroms. Then, the third insulating layer 28 is anisotropically etched by using the polycrystalline silicon eyebrows 30 and the side wall spacers 34 as an etching mask Etching until the surface of the substrate 10. In this way, the bit line contact window 8 and the capacitor node contact window 9 are formed at the same time, and the side wall spacer 34 can reduce the size of the contact window and increase the density of component accumulation. Now in In Fig. 6, a third polycrystalline silicon layer 36 is deposited, completely filling the contact lines between the bit lines and the nodes, and continuing to deposit enough to form a fairly flat surface above the contact window. The film layer 36 is preferably N + Fully doped with a concentration of about 1.0X1019 to 1.0 × ΙΟ21 ion / Cubic centimeter, and preferably between about 1000 and 2500 angstroms. In order to improve the conductivity of the bit line, a second silicide eyebrow 38 can be deposited on the film layer 36. For example (please first Read the notes on the back and fill in this page) Order ^ This paper size applies to Chinese National Standard (CNS) Α4 size (210 X 297 mm) A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs It is said that the silicide layer 38 can be made of tungsten silicide (WSi2) and has a thickness of about 500 to 1500 angstroms. For example, 812 can be deposited by tungsten hexafluoride (WFg) by CVD. A Si3N4 layer 40 is then deposited on the silicide layer 38. For example, the film layer 40 can be deposited by LPCVD, and dichlorosilane (SiC12H2) and ammonia (NH3) can be used as reaction gases at a temperature of about 700 to 800 ° C. The optimal thickness of the film layer 40 is about 1000 to 2000 angstroms. Finally, a layer of photoresist 42 is developed to define the bit line of the DRAM cell to contact the node. A multi-layer structure composed of the silicon nitride layer 40, the silicide layer 38, and the third polycrystalline silicon layer 36 is etched with the prepared photoresist 42 as an etching mask to form a bit line. After the multilayer structure is anisotropically etched up to the surface of the third insulating layer 28, the bit line 2 in FIG. 7 is formed, and a part of the film layer 36 is also left in the node contact window 9, forming a capacitor s contact. Next, in FIG. 8, a second silicon nitride layer 44 is deposited and anisotropically etched back, and a silicon nitride space also labeled 44 is formed on the side wall of the bit line 2. The method of Si3N deposition is similar to that of the deposited film layer 40. The Si3N4 layer 40 and the side wall spacer 44 enable bit line 2 to be isolated from the next layer of metal forming a double crown type storage capacitor in the integrated circuit. The remaining steps of this embodiment will now be described with reference to Figs. 9 to 15, particularly regarding a method of manufacturing a double crown storage capacitor of a DRAM element. In order to achieve the purpose of the invention, we used polycrystalline silicon spacers as an etching mask to etch a narrow vertical structure from the insulating material under the side walls of the polycrystalline silicon. These side walls become the vertical double crown structure of the bottom electrode of the storage capacitor. In FIG. 9, a conformal fourth polycrystalline silicon layer 46 is deposited on the bit lines after insulation. This polycrystalline silicon layer simultaneously contacts the polycrystalline silicon layer in the node contact window 9%. The best method for depositing the polycrystalline silicon layer 46 is similar to the method for depositing the film layer 36, and it is strongly doped with N + to improve the conductivity. Film thickness 46 is about this paper size Applicable to China National Standard (CNS) Α4 specification (2ΐ〇χ 297mm): ---:-^ ------ 1T ------ ^ I (please first Read the notes on the back and fill in this page) A7 B7_ printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs: 5. Description of Invention (//), 1500 to 2500 Angstroms. In Fig. 9, a relatively thick fourth insulating layer 48 is then deposited on the fourth polycrystalline silicon layer 46. The film layer 48 is preferably composed of SiO 2. For example, TEOS can be deposited via LPCVD. The insulating layer 48 is approximately 8000 to 12,000 Angstroms thick and can be planarized by, for example, chemical / mechanical polishing. Alternatively, a low tempering oxide such as BPSG can be used and then flattened by thermal tempering. The photoresist mask 50 of FIG. 9 is formed by a conventional lithography technique, and a part of the photoresist mask 50 is located above the node contact window 9 to define a region where a bottom electrode is to be formed. Now, as shown in FIG. 10, a pattern of the insulating layer 48 is formed by using a photoresist 50 and anisotropic etching. This anisotropic etching is preferably performed in a reactive ion etching machine or other high plasma density etching machine, and uses a fluorine-containing gas such as carbon tetrafluoride (CF4). The photoresist layer is then removed in a conventional manner, leaving the non-etched film layer 48 above the node contacts 9 and forming a second recessed area 11 in other parts of the film layer 48. The depth of the recessed area 11 is preferably between about 2500 and 4000 Angstroms. The process continues. On the established fourth insulating layer 48 having a recessed area U, a conformal fifth polycrystalline silicon layer 52 is deposited, and after anisotropic etchback, the recessed area is shown in FIG. H). On the side wall of 11 is formed a polycrystalline silicon spacer 52 ° film debris 52 is deposited by LPCVD, preferably without doping. The thickness of the film layer 52 needs to be selected so as to ensure that the width of the side wall spacer 52 formed after the etching is between 500 and 1000 angstroms. Then, in FIG. The slurry is etched until the surface of the fourth polycrystalline silicon layer 46 located in the non-recessed area (Figure ⑴). Because of the shielding of the polysilicon sidewall spacers 52, a narrow vertical region 54 is formed as a result of the etching. This anisotropic plasma etching is an important step of the present invention. In the implementation, the etching selectivity between the polycrystalline sand and the fourth insulating layer should be 丨: 1. For example, if the fourth must -----: --- ^-Society ------ ΪΤ ------ 后 '(Please read the precautions on the back before filling this page) This Paper size applies Chinese National Standard (CNS) A4 specification (210: < 297 mm) Printed by A7 B7, Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (/ y) \ The marginal layer is silicon oxide. Achieved: Selectivity of 1, it is best to etch in a reactive ion etcher or high-density plasma etcher, and use a low-pressure CHF3 or CF4 or other mixed etching gas. When the uranium etched film layer 48 reaches the surface of the film layer 46 of the non-recessed area 10, the polycrystalline silicon layer 46 in the recessed area 11 will be etched away to a considerable thickness, so that the polycrystalline silicon layer in the recessed area in FIG. 46 is thinner. This is very important for the present invention, because if the depth of the recessed region is approximately equal to the thickness of the fourth polycrystalline silicon layer 46, the film layer 46 in the recessed region 11 can be completely removed by using an etching ratio of 1: 1. In this way, a bottom electrode array electrically isolated from each other can be formed, which can be seen more clearly from FIG. 12. In FIG. 12, the remaining part of the polycrystalline silicon space element 52 is removed by plasma etching (see FIG. 11), and the polycrystalline silicon layer 46 in the non-recessed region 10 is slightly etched to ensure any residue in the recessed region 11 The polycrystalline silicon layer 46 is completely removed until the surface of the _Si3N4 layer 40. As a result, the adjacent bottom electrodes on the DRAM cell formed by the remaining polycrystalline silicon layer 46 can be electrically isolated. The most ideal plasma etching for removing the spacers 52 has extremely high contact selectivity between polycrystalline silicon and silicon nitride. For example, this etching can be performed in a reactive ion etching machine, and a mixed gas of chlorine gas (cy and hydrogen bromide (HBr)) is used as an etching gas. In FIG. 13, a layer of conformal sixth polycrystal is deposited The silicon layer 56 begins to produce the double crown portion of the bottom electrode of the capacitor. The conformal polycrystalline silicon layer is evenly coated on the narrow vertical insulating structure 54. The sixth polycrystalline silicon layer 56 is preferably deposited by LPCVD. And, for example, silane (SiH4) can be used as the reaction gas, and simultaneous thick doping by adding phosphine (PH4) while depositing. The impurity concentration in the film layer 56 is preferably about 1.0X 101QSU ) X 102 Lizi / cubic centimeter. The thickness of the film layer 56 is preferably between about 50 U and 10 UU, and most preferably 50 Å. In FIG. W, after the sixth polycrystalline silicon layer 56 is etched back anisotropically, the top surface of the narrow vertical insulating structure 54 is exposed, and the film layer in the recessed area 11 is also removed: (Please read the notes on the back before filling out this page)
、1T 本纸張尺度適用中國國家祿準（CNS ) Α4規格（210 X 297公釐） 經濟部中夬標準局員工消費合作社印裝 A7 B7 ι __________________ " _ 1 —" — 五、發明説明（/^>) 56，直到露出氮化矽層40，因此確保底部電極陣列彼此仍然維持電 性隔離。這道蝕刻最好在反應離子蝕刻機中進行，或者在高電漿密 度的蝕刻機中進形行，並使用含氯的氣體作爲蝕刻氣體。 現在要對複晶矽層46，選擇性地去除由Si02等類材料組成的狭 窄的垂直絕緣結構54。最理想的蝕刻，舉例來說，可以用氫氟酸水 溶液(HF/H20)進行，可以幾乎完全不蝕刻露出的複晶矽層54與 56，也不蝕刻露出的Si3N4層4():這樣就完成了具有雙皇冠型儲存 電容器的底部電極的陣列。 現在圖15要說明完成DRAM細胞元的雙皇冠儲存電容器的步 驟。其中電容器的底部電極是由複晶矽層56與複晶矽層(空間子)54 形成之雙皇冠部份所組成的，現在繼續以上的步驟，先在底部電極 的表面上形成一層電容器電極間的介電層60。這層介電層60最好是 由氮化矽與氧化矽(Si,乂/SiCg所組成，或者由氧化矽、氮化矽與 氧化矽(ΟΝΟ)等膜層組成。舉例來說，介電層60如果是由氮化矽與 氧化矽組成，可以先用LPCVD，利用氨氣(ΝΗ3)與二氯矽烷 (SiH2Cl2%〗混合氣體作爲反應氣體，沉積氮化矽層，然後在溫度約 850°C的濕氧氣中，對氮化矽進行氧化約10分鐘。這層電極間的介 電層60的總厚度最好約在30至100埃之間。此外，也可以使用其他 常用的方法來進一步提高電容値，例如使電極表面粗糙化，並使用 五氧化組(Ta205)之類介電常數更高的介電材料。 同樣在圖15中，電極間的介電層60上沉積了一層第七複晶矽 層62。膜層62可以保型地塗佈在表面上具有電極間介電層的底部電 極上，形成儲存電容器的頂部電極。膜層62最好是由LPCVD沉積 而成，並以N型雜質加以同歩摻雜。膜層62最好厚約1000至2000埃 之間，並以磷(P)之類的N型雜質加以摻雜。膜層62中磷的濃度最好 -------：--装------訂 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29?公釐） A7 B7 五、發明説明（//) 約在5.0X 101°至1 0X 1〇21離子立方公分之間。然後以傳統的微影 技術與電漿蝕刻制定複晶矽層62的圖案’形成頂部電極’完成了雙 皇冠型的儲存電容器陣列。在圖中畫出了電容器陣列中兩個相鄰 的電容器。 圖16的示意圖中是較傳統堆疊式電容器，而圖17則是本發明 雙皇冠型電容器80，與圖16中的電容器具有相同的外圍大小，經由 兩個示意圖的比較，更可看出本發明的優點。在圖16與圖17中，傳 統的堆疊式電容器與雙皇冠型堆疊式電容器厚0.8微米，長度與寬 度分別爲1.2微米與0 6微米。以圖16的尺寸，總表面積爲3.6平方微 米。圖1’中雙皇冠型電容器的皇冠區域厚0.05微米，並且相間0.05 微米，表面面積爲I) 9平方微米，使表面面積提高爲傳統堆疊式電 容器的2.75倍。 以上的說明雖然是藉著最佳實施例加以仔細闡述，但熟習本技 藝的人士都瞭解，在不離開本發明的範圍與精神底下，仍有許多形 式上、細節上不同的變化存在。 11 I I —I I ' n II 訂 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央樣準局員工消費合作社印裝、 1T This paper size is applicable to China National Standards (CNS) A4 (210 X 297 mm) Printed on A7 B7 by the Consumer Cooperatives of the China Standards Bureau of the Ministry of Economic Affairs __________________ " _ 1 — " — V. Description of the invention (/ ^ ≫) 56 until the silicon nitride layer 40 is exposed, thus ensuring that the bottom electrode arrays remain electrically isolated from each other. This etching is preferably performed in a reactive ion etching machine or a high plasma density etching machine, and a chlorine-containing gas is used as an etching gas. Now, it is necessary to selectively remove the narrow vertical insulating structure 54 composed of a material such as SiO2 for the polycrystalline silicon layer 46. The most ideal etching, for example, can be performed with a hydrofluoric acid aqueous solution (HF / H20). The exposed polycrystalline silicon layers 54 and 56 can be hardly etched, and the exposed Si3N4 layer 4 () is not etched. An array with bottom electrodes of a double crown type storage capacitor was completed. Figure 15 now illustrates the steps to complete a dual crown storage capacitor for a DRAM cell. The bottom electrode of the capacitor is composed of a double crown formed by the polycrystalline silicon layer 56 and the polycrystalline silicon layer (spacer) 54. Now continue the above steps, and first form a layer of capacitor electrodes on the surface of the bottom electrode.的 硅 层 60。 The dielectric layer 60. This dielectric layer 60 is preferably composed of silicon nitride and silicon oxide (Si, hafnium / SiCg), or a film layer of silicon oxide, silicon nitride, and silicon oxide (ONO). For example, dielectric If the layer 60 is composed of silicon nitride and silicon oxide, LPCVD can be used first to deposit a silicon nitride layer by using a mixed gas of ammonia (ΝΗ3) and dichlorosilane (SiH2Cl2%) as a reaction gas, and then the temperature is about 850 ° In wet oxygen of C, the silicon nitride is oxidized for about 10 minutes. The total thickness of the dielectric layer 60 between the electrodes is preferably about 30 to 100 angstroms. In addition, other commonly used methods can be used to further Increase the capacitance 値, such as roughening the electrode surface, and use a dielectric material with a higher dielectric constant such as pentoxide group (Ta205). Also in FIG. 15, a seventh layer is deposited on the dielectric layer 60 between the electrodes. The polycrystalline silicon layer 62. The film layer 62 can be conformally coated on the bottom electrode having an inter-electrode dielectric layer on the surface to form the top electrode of the storage capacitor. The film layer 62 is preferably deposited by LPCVD and is formed by N-type impurities are doped with holmium. The film layer 62 is preferably about 1000 to 2000 angstroms thick. And doped with N-type impurities such as phosphorus (P). The concentration of phosphorus in the film layer 62 is the best ---------------------------- (please read the first Note: Please fill in this page again.) This paper size applies Chinese National Standard (CNS) A4 specification (210X29? Mm) A7 B7 V. Description of the invention (//) About 5.0X 101 ° to 1 0X 1〇21 ionic cubic centimeters Then, using a traditional lithography technique and plasma etching, the pattern of the polycrystalline silicon layer 62 is formed to form a top electrode to complete a double crown type storage capacitor array. In the figure, two adjacent capacitor arrays are drawn in the figure. The capacitor in Figure 16 is a more traditional stacked capacitor, while Figure 17 is a double-crown capacitor 80 according to the present invention, which has the same outer size as the capacitor in Figure 16, and can be seen by comparing the two diagrams. The advantages of the present invention are shown. In FIGS. 16 and 17, the conventional stacked capacitor and the double crown type stacked capacitor are 0.8 μm thick, and the length and width are 1.2 μm and 0.6 μm, respectively. With the size of FIG. 16, the total surface area Is 3.6 square microns. Figure 1 'Crown area of the double crown capacitor The thickness is 0.05 micron, and the interphase is 0.05 micron. The surface area is 9 square micrometers, which increases the surface area to 2.75 times that of the traditional stacked capacitor. Although the above description is explained in detail through the best embodiment, familiar with this technology Those of you understand that, without departing from the scope and spirit of the present invention, there are still many changes in form and detail. 11 II —II 'n II Order (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Central Sample Bureau of the Ministry of Economic Affairs
本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐）This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)