A7 B7 五、發明説明（） 經濟部中央標準局貝工消費合作社印装 1. 發明之技術領域 本發明是關於積體電路之動態隨機存取記憶體（DRAM)的製造方法，特別是 關於高密度堆疊式動態隨機存取記憶體（stackDRAM)的製造方法。 2. 發明背景 臺灣目前已經成爲積體電路王國，1995年新竹科學工業園區之積體電路產値超 過新臺幣1000億，而新竹科學工業園區主要的積體電路產品是數位金氧半場效電晶 體積體電路（digital MOSFET 1C)。傳統製造金氧半場效電晶體積體電路之方法是 在矽半導體晶圓上形成隔離金氧半場效電晶體所需要的場氧化層，然後，再製造金 氧半場效電晶體（MOSFET)，金氧半場效電晶體並可分爲p通道金氧半場效電晶 體（PMOSFET)、N通道金氧半場效電晶體（NMOSF£T)和互補式金氧半場效電 晶體（CMOSFET)。 但隨著臺灣積體電路硏究發展能力的突飛猛進，臺灣最近幾年已經開始生產製 造高技術層次的動態隨機存取記憶體。例如，在政府策略性零組件工業之政策下所 輔導成立的位於新竹科學工業園區的世界先進積體電路公司（VanguardInternational Semiconductor Corporation ) ’便在1995年開始八吋晶圓之四佰萬位元堆疊式動態 隨機存取記憶體的生產行銷。另一方面，國內企業鑑於世界先進積體電路公司成功 的開發出八吋晶圓之四佰萬位元堆疊式動態隨機存取記億體，也開始如火如荼的跟 美國、曰本的知名積體電路公司進行策略聯盟，開發八吋晶圓之動態隨機存取記憶 體產品，例如，南亞集團跟日本沖電氣（OKI)進行策略聯盟在觀音工業區設廠生產 動態隨機存取記憶體，力捷電腦集團跟曰本三菱公司（mitsubishi)進行策略聯盟成 立力晶半導體公司（Powerchip Semiconductor Corporation)在新竹科學工業園區設廠 生產動態隨機存取記憶體，華邦電子（winbcmd)跟日本東芝公司（toshiba)進行策 略聯盟在新竹科學工業園區設廠生產動態隨機存取記憶體，宏碁電腦公司（acer)跟 美國德州儀器公司（TI)進行策略聯盟成立德碁半導體公司（TI-Acer)，而國內規 模最大的臺灣積體電路製造公司（tsmc)和聯華電子（UMC)也擴廠生產動態隨機 存取記憶體。由於動態隨機存取記憶體在各種積體電路的需求量最大，是半導體產 業之稻米，因此，在不久的未來，動態隨機存取記憶體將締造新竹科學工業園區最 大的產値，其重要性不言可喻。新竹科學工業園區之各大積體電路公司之技術層次 已經進入設計準則0.4到0.35微米之一仟六佰萬位元動態隨機存取記憶體的量產階 段，例如，世界先進積體電路公司、茂矽電子、臺灣積體電路製造公司和德碁半導 體公司都已經具備這種能力。 典型的動態隨機存取記億體是在矽半導體晶圓上製造一個金氧半場效電晶體與 電容器’並利用所述金氧半場效電晶體的源極（source)來連接電容器的電荷儲存電 極（storage node)以形成動態隨機存取記憶體的記憶元。數目龐大的記憶元聚集成 爲記億元陣列。另一方面，在記憶元陣列的附近則有其它電路圍繞，例如感測放大 器（sense amplifier)等電路，這些外部電路，稱爲週邊電路區域（peripheral circuit)。因此，要達到動態隨機存取記憶體之高積集密度的目的，必需縮小記憶體 ----------裝 I 訂 (请先閲讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS ) A4現格（210X297公釐） A7 B7 經濟部中央標李局員工消f合作社印装 五、發明説明（） 之記憶元的尺寸，然而電容器尺寸的縮小會降低電容値，使得記憶體電路的訊號/雜 訊（SignalNoise ; S/N)比例降低，造成電路誤判或電路不穩定等缺點。職是之故， 爲了達成高積集密度的動態隨機存取記憶體，必需尋找更尖端的製程技術，以在降 低記憶元之平面電路佈局面積之同時，能夠維持或增加電容器之電容値。 電容的公式是C = ε A/T，其中，ε是電容器介電層（capacitor dielectric )之介 電常數，A是電容器下層電極之表面積，T是電容器下層電極之厚度，因此，要增加 電容器之電容可以從兩個方向著手，第一個方向是採用高介電常數的材料作爲電容 器介電層，例如，Ta205、Ti02和SrTi03材料都具有非常高的介電常數，可惜， 由於這些高介電常數的材料之薄膜品質不佳，存在有絕緣唐的奔潰電壓等可靠性問 題，因此到目前爲止還無法應用到動態隨機存取記憶體。 使用高介電常數的電容器介電層既然不甚可行，吾人由電容的公式C= eA/T 可知電容的大小跟電容器下層電極之表面積成正比，因此，增加電容器下層電極之 表面積是增加電容器之電容的另一個方向，而目前最普遍的是所謂三度空間電容器 (3-D capacitor )。所述三度空間電容器是在所述轉移閘電晶體之上方或下方的第三 度空間形成電容器，以在有限的平面電路佈局面積內增加電容器之電容値。電容器 製造在所述轉移閘電晶體之上方時，稱爲堆疊式電容器（stackcapacitor)，而電容 器製造在所述轉移閘電晶體之下方時稱爲凹溝式電容器（trenchcapacitor)。目前， 動態隨機存取記憶體工業主要是使用堆疊式電容器結構，例如，日本和韓國的半導 體公司主要是採用堆疊式電容器結構。 Watanabe 等人於 IEDM 1988 年第 600 頁所發表之「stacked capacitor cells for high density dynamic RAMs」與 Wakamiya 等人於 VLSI Technology 1989 第 69 頁所發表之 「novel stacked capacitor cell for 64 Mb DRAM」均揭露了堆叠式電容器結構。S. Kimura等人的美國專利第4742018號和T.Ema美國專利4977102號亦揭露堆疊式電 容器以增加電容器電容。日本富士通公司的Masao Taguchi等人在美國專利第 5021357號更揭露了改良的堆疊式電容器結構，稱爲鰭型電容器結構（fin capacitor)，大幅增加電容器電容，提高動態隨機存取記憶體之集積密度。曰本 Hitachi公司的T. Kaga等人更在1994年IEDM第927頁之一篇題目爲「A 0.29 um2 ΜΙΜ-CROWN cell and process technology for 1-Gigabit DRAMs」的論文，揭露了一種 更爲先進的稱爲「MIM-CROWN結構」的堆疊式電容器，這些電容器結構均能大幅 增加電容器的電容値，提高動態隨機存取記億體元件之集積密度。 本發明揭露了一種新穎的堆疊式電容器的製造方法，可以大幅縮小電容器之平 面電路佈局面積和大幅提高電容器的電容，因此能應用在超高集積密度之堆疊式動 態隨機存取記憶體產品的製造。 ^—1T (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4说格（2!0X297公釐） A7 B7 五、發明説明（） 3.發明之簡要說明 本發明的主要目的是提供一種高電容之堆疊式電容器的製造方法。 本發明的另一個目的是提供一種高集積密度之堆疊式動態隨機存取記憶體的製 造方法。 本發明之主要方法如下。首先，以標準製程在砂半導體晶圓上形成隔離金氧半 場效電晶體所需要的場氧化層，接著，形成金氧半場效電晶體，而在形成金氧半場 效電晶體複晶砂閘極（polysilicon gate electrode)之同時也形成複晶砂字語線 (polysilicon wordline ) 〇 接著，沈積一層第一介電層、第二介電層和非晶砂（amorphous silicon)，並平 坦化所述第二介電層。然後，利用微影技術和電漿蝕刻技術在電容器區域（capacitor region)蝕去所述第一介電層、第二介電層和非晶矽以形成記憶元接觸窗（cell contact)。未來，堆疊式電容器之電荷儲存電極將透過所述記憶元接觸窗跟金氧半 場效電晶體之源極作電性接觸。 接著，形成一層很薄的複晶砂半球型晶粒（polysilicon Hemi-Spherical Grain ; HSG)，所述「薄的複晶矽半球型晶粒」沒有塡滿所述記憶元接觸窗。接著，利用 微影技術和電紫触刻技術触刻電容器區域以外的所述「薄的複晶矽半球型晶粒」和 「非晶矽」。然後，去除所述非晶矽表面之自然氧化層，在大於1〇·6 tori的高眞空 的情況下，對所述非晶矽進行回火處理，以在所述非晶矽的側表面形成粗糖表面。 所述「薄的複晶矽半球型晶粒」、「非晶矽」和「粗糖表面」構成電容器的電荷儲 存電極，由於所述電荷儲存電極表面粗糖不平，故能增加電荷儲存電極表面積，大 幅提高電容器的電容，提高動態隨機存取記憶體的集積密度。 最後，在所述電荷儲存電極的表面形成一層電容器介電層（capacitor dielectric)和複晶矽，再利用微影技術和飽刻技術触刻所述電容器介電層和複晶矽， 以形成電谷的上層電極（plate electrode )，一種具有筒電谷和筒集積密度之堆疊式 經濟部中央標準局員工消費合作社印装 ----------裝 訂 (請先閲讀背面之注意事項再填寫本頁) 動態隨機存取記憶體於焉完成。 本纸張尺度適用中國國家樣準（CNS ) A4現格（210X297公釐） A7 B7 經濟部中央樣準局員工消費合作社印聚 五、發明説明（） 4. 圖示的簡要說明 圖一到圖九是本發明之實施例的製程剖面示意圖》 圖一是在矽半導體晶圓上形成轉移閘電晶體和字語線後的製程剖面示意圖； 圖二是沈積一層第一介電層與第二介電層，並平坦化所述第二介電層後的製程剖面 示意圖； 圖三是沈積一層非晶矽並利用微影技術形成光阻圖案後的製程剖面示意圖； 圖四_是利用電獎蝕刻技術在電容器區域（capacitorregion)触去所述第一介電層、 第二介電層和非晶砂以形成記憶元接^窗（cell contact)後的製程剖面示意 圖； 圖五是去除所述光阻圖案後的製程剖面示意圖； 圖六是形成一層很薄的複晶砂半球型晶粒（polysilicon Hemi-Spherical Grain ; HSG)後的製程剖面示意圖； 圖七是利用微影技術和電漿蝕刻技術蝕刻電容器區域以外的所述「薄的複晶矽半球 型晶粒」和「非晶矽」後的製程剖面示意圖； 圖八是對所述「非晶矽」進行回火處理後的製程剖面示意圖； 圖九是對所述「非晶矽」進行回火處理，以在所述非晶矽的側表面形成粗糙表面後 的製程剖面示意圖。 5. 發明之實施例 現在請參考圖一。首先，在電阻値約2.5 ohm-cm、晶格方向（Ί00)之P型砂_ 半導體晶圓〗〇上形成場氧化層12，所述場氧化層12通常是利用傳統的局部^氧^、 化技術（LOCQS)氧化所述Ρ型嫂^導體基板10而形成，其厚度介於J500埃到 埃之間，作爲隔離金氧半場效重晶體之用。當然，也可以利用傳統的淺凹溝隔 離技術（ShallowTrench Isolation ; STi)來形成隔離金氧半場效電晶體所需之場氧化 層12。然後，在所述P型矽半導體晶圓10之表面形成金氧半場效電晶體，所述金 氧半場效電晶體包含有聞氣化厣、聞極16A、覆蓋氧化層18 (cappedoxide)、 淡摻雜源極/汲極20A/20B '二氧化矽側壁子22和N+源極/汲極24A/24B，如 圖一所示。另外，在形成閘極16A之同時也形成字語線16B，如圖一所示。 請再參考圖一。所述閘氧化層14是在含乾氧的高溫環境中熱氧化所述P型矽 半導體晶圓10之表面之矽原子而成，其氧化溫度介於M0到〗〇〇〇 °C之間，其厚 度介於.50到2Q0埃之間。所述閘極16A則一般是由低壓化學氣相沉積法 (LPCVD)形成之複晶砂16或鎢複晶砂化物所構成(polycide )，若由複晶砂構 成’其厚度介於2〇〇〇到4〇〇〇埃之間，若由鎢複晶矽化物構成，則下層複晶矽之 厚度介於1000到2000埃之間，上層矽化鎢之厚度介於1000到2000埃之間， 其總厚度也是介於2000到4000埃之間。所述覆蓋氧化層18是利用低壓化學氣相 沉積法形成夕無摻雜的二氬化砂，其厚度介於800到1600埃之間。然後，利用微 影技術與雷漿鈾刻技術鈾刻所沭覆蓋氧化層18和複晶矽16或鎢複晶矽化物，以形 成所述轉移閘電晶體之閘極結構14/16A/18 (gate structure)，如圖一所示。 本纸張尺度適用中國國家標準（CNS ) A4说格（210><297公釐） n n II ^ i 111 訂 (請先閲讀背面之注意事項再填寫本頁) A7 B7 蛵濟部中央標準局員工消費合作社印衮 五、發明説明（） 形成所述複晶矽16之反應溫度介於500到700 °C之間，而形成之複晶矽16 可以未經摻雜，然後再利用離子佈植技術予以摻雜使具導電性，其離子佈植劑量介 於1E】3到1E16原子/平方公分之間，離子佈植能量則介於3〇到80 Kev之間，以 完成對所述複晶矽16之摻雜。當然，也能利用同击磷離土遽麗方兹(in-situ d〇Ded )以完成對所述複晶矽16之摻雜，其反應氣體是PH3、SiH4與N2的混合氣 體或AsH3、SiH4與N2的混合氣體，最後的磷離子濃度介於1E20到1E21原子/立 方公分之間，而較理想的磷離子濃度是5E20原子/立方公分之間。對所述複晶矽16 之電發蝕刻，杲利用磁場增強式活件離子式雷漿飩刻枝術（MERIE) ’其反應氣體 則是由六氟化硫、氯氣和溴化氫組成之混合氣體，能提供效果相當理想的里面性触 刻、蝕刻率和蝕刻均勻度，所述複晶矽16對所述閘氧化層14之電獎鈾刻選擇率大 於邛，非苗高。 請再參考圖一。接著，利用磷離子佈植技術來形成所述轉移閘電晶體之N-淡 摻雜源極/汲極20A/20B，其離子佈植劑量介於1E13到3F.14原子/平方公分之 間，離子佈植能量則介於20到50 Kev之間，如圖一所示，所述N-淡摻雜源極/汲 極是爲了降低熱載子效應，以提高所述轉移閘電晶體之可靠性。接著，沉 積一層二氧化矽22，並利用磁場增強式活性離子式電獎触刻技術對所述二氧化矽 22進行垂直單向性的回蝕刻，以在所述閘極16之二側形成二氧化砂側壁子22。 而所述二氧化矽22通常是利用低壓化學氣相沉積法形成之無提雜的二氧化砂，其反 應氣體是矽甲烷或祖已基政酸鹽（Si(C2H5〇)4)和氧氣，反應溫度介於600到800 °C之間，反應壓力介於0.2到0.4托爾之間，厚度介於1000到2500埃之間。最 後，利用離子砷佈植技術形成N+源極24A/汲極24B，其離子佈植劑量介於1E15到 止原子/平方公分之間，離子佈植能量則介於剞80 Kev之間，以提供良好的歐 姆接觸，如圖一所示。 現在請參考圖二、圖三、圖四與圖五。完成所述轉移閘電晶體和字語線16B的 製造後，接著，沈積一層第一介電層26與第二介電層_之8，並利用化學機械式琢磨 技術（Chemical Mechanical Polishing ： CMP )平坦化所述第二介電層28，如圖二所 示。接著，沈積一層非晶砂30 ( amorphous silicon )，並利用微影技術在IP.電容器 區域上方形成光阻圖案32，如圖三所示。所述非晶矽30是利用低壓化學氣相沉穑 法形成，反應氣體是矽甲烷，反應溫度介於500 °C到55Q；C之間，反應壓力介於 150 mtorr到250 mtorr之間，厚度介於3000到8000埃之齒。接著，以所述光阻圖 案2_2作爲蝕刻護罩，利用電漿蝕刻技術触刻所述五 +源極24A上方之所述第一介 電層26與第二介電層28和非晶矽30，以露出所述N+源極24A，使所述非晶矽 30成爲非晶矽30A，以在所述N+源極24A區域形成記憶元接觸窗33 (node contact)，如圖四所示，去除所述光阻圖案32後，如圖五所示。未來，堆疊式電容 器之電荷儲存電極將透過所述記憶元接觸窗3心跟所述轉移閘電晶體之N+源極 24A作電性接觸。 & 本纸張尺度適用中國國家標準（CNS ) Α4現格（210Χ297公釐） (請先閲讀背面之注意事項再填寫本頁) •裝. 訂 A7 B7 經濟部中央標华局員工消费合作杜印裝 五、發明説明（） 一所述第一介電層26可以是利用低壓化學氣相沉積法（LPCVD)形成之無攙雜 的二氧化矽，其反應溫度介於330到37〇。(：之間，其反應氣體是四已基矽酸鹽 (TEOS)與氧化氮（N2〇)或甲烷（silane)與氧化氮（N2〇)，其厚度介於皿 埃到之間。所述第二介電層28則是利用化學氣相沉積法形成之二氧化砂， 其厚度介於2〇α〇到卯00埃之間。對所述第一介電層26與第二介電層28之電漿 蝕刻以形成所述記憶元接觸窗33，可以利用磁場增強式活性離子式電發餓刻技術 (MERIE)或電子迴旋共振電漿蝕刻技術或俥統的活件離$忒雷骄鈾刻捋 ^ (㈣，而通常是利用磁場增強式活性離子式電漿蝕刻技術，其電漿反應氣體是 三氟氫化碳和氬氣，例如，日本電氣公司（TEL)所製造型號DRM之蝕刻機或美 國應用材料公司（appliedmaterials)所製造型號DPS之蝕刻機，其蝕刻原理均屬於 磁場增強式活性離子式電漿蝕刻技術，能提供效果相営珲想的單向件帥刻'蝕刻率 和蝕刻均勻度，且對所述P型矽半導體基板10之電漿蝕刻選擇率也非常高。對所述 非晶矽30之電漿蝕刻，也是利用磁場增強式活件離子式雷锻軸刻抟術或雷子洇掄社 振璽蜜触刻技術或傳紘韵活性離子式電漿蝕刻技術，其電漿反應氣體是六氟化硫、 氧、氯和溴化氫之混合氣體’均能提供效果相當理想的餘刻宰和蝕刻均勻度，並 且’所述非晶矽所述第二介電層28之蝕刻選擇率非常高，介於25到35之 間。 現在參考圖六和圖七。接著，形成一層摻雜的、很薄的複晶矽半球型晶粒40 (polysilicon Hemi-Spherical Grain ; HSG )，所述「薄的複晶砂半球型晶粒 40 j 沒 有塡滿所述記憶元接觸窗33，如圖六所示。所述「複晶矽半球型晶粒40」是利用 低壓化學氣相沉積法形成，其反應溫度介於500到750 °C之間，其直徑介於200到 800埃之間。接著，利用邀影技術和重漿触刻技術蝕刻電容器區域以外的所述「薄的 複晶矽半球型晶粒40」和「非晶矽30A」，使所述非晶矽30A成爲非晶矽30B， 如圖七所示。對所述「薄的複晶矽半球型晶粒40」和「非晶矽30A」之電紫触刻， 是利用磁場增強式活性離子式電漿蝕刻，其電漿反應氣體是六氟化硫、氧氣和溴化 氫之混合氣體，均能提供效果相當理想的鈾刻率和鈾刻均勻度，並且，所述「薄的 複晶矽半球型晶粒40」和[非晶矽30A」對所述第二介電層28之蝕刻選擇率非常 高，介於25到35之間。 現在參考圖八和圖九。接著，利用稀釋氫氟酸溶液或蒸氣氫氟酸（vaporHF) 去除所述「非晶矽30A」表面之自然氧化層，再在大於10·6ίΟΓΓ的高眞空的情況 下，對所述「非晶矽30Β」進行回火處理88，回火溫度介於550 °C到650 °C之 間，如圖八所示，以在所述「非晶矽30B」的側表面形成粗糙表面50，其直徑介 於100到500埃之間，使所述「非晶矽30B」成爲所述「非晶矽30C」，如圖九所 示。所述「薄的複晶矽半球型晶粒40 ,、「非晶矽30C」和「粗糙表面50」構成 電容器的電荷儲存電極30C/40/50，由於所述電荷儲存電極30C/40/50表面粗糙不 平，故能增加電荷儲存電極30C/40/50表面積，大幅提高電容器的電容，提高動態 隨機在取記憶體的集積密度》 完成電荷儲存電極30C/40/50的製造後，接著，以標準製程在所述電容器的電 荷儲存電極30C/40/50表面形成一層厚度極薄的電容器介電層，接著，形成一層複 (請先W讀背面之注意事項再填寫本頁) -裝· 訂 本紙張尺度適用中國國家標準（CNS > A4洗格（210X 297公釐） 3iS ㈣ 3 A7 B7 五、發明説明（） 晶矽。最後，利用微影技術與磁場增強式活性離子式電漿蝕刻技術蝕刻所述薄的電 容器介電層和複晶矽，以形成電容器的上層電極（topelectrode)，一種具備高電容 電容器和高集積密度之堆疊式動態隨機存取記憶體於焉完成。 所沭雷容器介電層通常是由氣化氮化砂(Oxynitride)、氮化矽(Nitride)和二 氧化矽（〇2dd£)藉由下述方法形成。首先，在溫度介於800°C到950°C之間時熱氧 化由複晶政構成之所述電荷儲存電極30C/40/50，以形成厚度介於40埃到200埃 之間的氧化矽。接著，在溫度介於650°C到750°C之間時以低壓化學氣相沉積法形 成厚度介於40埃到60埃之間的氮化矽。最後，在溫度介於800°C到950°C之間時 氧化所述氮化矽，以形成厚度介於20埃到50埃之間的氧化氮化矽。自然，所述電 容器介電層亦可由其它高介電常數材料組成，例如五氧二鉬（Ta205 )，或由Ti02 和SrTi03等高介電常數材料所組成。 所述複晶矽之形成方法是利用同步擔雜之低壓化學氣相沉積法形成，其反應氣 體是PH3 ' SiH4與N2或AsH3、SiH4與N2的混合氣體，攙雜有磷和砷等雜質原 子，其反應溫度介於m到650 °C之間，其厚度介於1000到2000埃之間，所述第 二複晶矽也必需具値導電性，其雜質離子濃度介於1_^0到1E21原子/立方公分之 間，而較理想的濃度是5Ε20原子/立方公分。而形成電容器的上層電極之電漿蝕 刻’可以利用磁場增強式活性離子式電漿蝕刻技術（MERIE)，其電漿反應氣體是 六氟化硫、氧氫和溴化氫之混合氣體》 以上係以最佳實施例來闡述本發明，而非限制本發明，並且，熟知半導體技藝 之人士皆能明瞭，適當而作些微的改變及調整，仍將不失本發明之要義所在，亦不 脫離本發明之精神和範圍。 ----------裝 訂 (請先閲讀背面之注^•項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本纸張Μ適用中國國家椟準（CNS ) (2丨〇χ297公麓）A7 B7 V. Description of the invention () Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy 1. Technical Field of the Invention The present invention relates to a method for manufacturing dynamic random access memory (DRAM) of integrated circuits, especially high-tech Manufacturing method of density stacked dynamic random access memory (stackDRAM). 2. Background of the invention Taiwan has now become the kingdom of integrated circuits. In 1995, the output of integrated circuits in Hsinchu Science Industrial Park exceeded NT $ 100 billion, and the main integrated circuit products in Hsinchu Science Industrial Park were digital gold-oxygen half-effect electric power. Crystal volume circuit (digital MOSFET 1C). The traditional method of manufacturing a metal oxide semiconductor field volume circuit is to form a field oxide layer on a silicon semiconductor wafer that is required to isolate the metal oxide semiconductor field effect transistor, and then to manufacture a metal oxide semiconductor field effect transistor (MOSFET), gold Oxygen half-field transistors can be divided into p-channel gold-oxide half-field transistors (PMOSFET), N-channel gold-oxide half-field transistors (NMOSF £ T) and complementary gold-oxide half-field transistors (CMOSFET). However, with the rapid development of Taiwan's integrated circuit research and development capabilities, Taiwan has begun to produce high-tech dynamic random access memory in recent years. For example, the world advanced integrated circuit company (Vanguard International Semiconductor Corporation) located in Hsinchu Science Industrial Park under the guidance of the government ’s strategic component industry policy began to stack four-megabit 8-inch wafers in 1995 -Style dynamic random access memory production marketing. On the other hand, in view of the success of the world's advanced integrated circuit companies in the development of four-megabit stacked dynamic random access memory devices with 8-inch wafers, they have begun to follow the well-known integrated products of the United States and Japan. Circuit companies conduct strategic alliances to develop eight-inch wafer dynamic random access memory products. For example, Nanya Group and Japan's OKI (OKI) have strategic alliances to set up factories in Guanyin Industrial Zone to produce dynamic random access memory. The Computer Group and Mitsubishi entered into a strategic alliance to establish Powerchip Semiconductor Corporation to set up a factory in the Hsinchu Science Industrial Park to produce dynamic random access memory. Winbcmd and Toshiba ) A strategic alliance was established in the Hsinchu Science Industrial Park to produce dynamic random access memory. Acer Computer Corporation (acer) and Texas Instruments Inc. (TI) entered into a strategic alliance to establish TI-Acer, and the domestic scale The largest Taiwan Semiconductor Manufacturing Company (tsmc) and Lianhua Electronics (UMC) also expanded their production activities Random Access Memory. Since dynamic random access memory has the largest demand for various integrated circuits and is the rice of the semiconductor industry, therefore, in the near future, dynamic random access memory will create the largest output value of the Hsinchu Science Industrial Park, and its importance It goes without saying. The technology level of the major integrated circuit companies in the Hsinchu Science Industrial Park has entered the mass production stage of the design guidelines of 0.4 to 0.35 micrometers, 16 million bits of dynamic random access memory. For example, the world ’s advanced integrated circuit companies, MoSi Electronics, Taiwan Semiconductor Manufacturing Co., and Deqi Semiconductor have all possessed this capability. A typical dynamic random access memory device is to fabricate a metal oxide semiconductor field effect transistor and a capacitor on a silicon semiconductor wafer and use the source of the metal oxide semiconductor field effect transistor to connect the charge storage electrode of the capacitor (Storage node) to form memory cells of dynamic random access memory. A huge number of memory cells are aggregated into an array of 100 million yuan. On the other hand, there are other circuits around the memory cell array, such as sense amplifiers. These external circuits are called peripheral circuits. Therefore, in order to achieve the purpose of high accumulation density of dynamic random access memory, it is necessary to shrink the memory ---------- I order (please read the precautions on the back before filling this page) This paper The Zhang scale applies to the Chinese National Standard (CNS) A4 (210X297mm) A7 B7 The size of the memory cell printed by the Ministry of Economic Affairs, Central Standardization Bureau of the Ministry of Economic Affairs, printed by the cooperative, but the capacitor size will be reduced The capacitance value reduces the signal / noise (S / N) ratio of the memory circuit, resulting in shortcomings such as circuit misjudgment or circuit instability. For this reason, in order to achieve a high accumulation density of dynamic random access memory, it is necessary to find more advanced process technology to reduce the planar circuit layout area of the memory cell while maintaining or increasing the capacitance value of the capacitor. The formula for capacitance is C = ε A / T, where ε is the dielectric constant of the capacitor dielectric layer, A is the surface area of the lower electrode of the capacitor, and T is the thickness of the lower electrode of the capacitor. Therefore, increase the capacitor Capacitors can be started from two directions. The first direction is to use high dielectric constant materials as capacitor dielectric layers. For example, Ta205, Ti02 and SrTi03 materials all have very high dielectric constants. Unfortunately, due to these high dielectric The film quality of the constant material is not good, and there are reliability problems such as insulation breakdown voltage, so it has not been applied to dynamic random access memory so far. Since the use of a high dielectric constant capacitor dielectric layer is not feasible, we can see from the formula of capacitance C = eA / T that the size of the capacitor is proportional to the surface area of the lower electrode of the capacitor. Therefore, increasing the surface area of the lower electrode of the capacitor is to increase the capacitor. The other direction of capacitance, and the most common at present is the so-called 3-D capacitor. The three-dimensional space capacitor forms a capacitor in the third-degree space above or below the transfer gate transistor to increase the capacitance value of the capacitor within a limited planar circuit layout area. When the capacitor is fabricated above the transfer gate transistor, it is called a stack capacitor, and when the capacitor is fabricated below the transfer gate transistor, it is called a trench capacitor. At present, the dynamic random access memory industry mainly uses stacked capacitor structures. For example, semiconductor companies in Japan and South Korea mainly use stacked capacitor structures. The "stacked capacitor cells for high density dynamic RAMs" published by Watanabe et al. On page 600 in IEDM 1988 and the "novel stacked capacitor cells for 64 Mb DRAM" published by Wakamiya et al. On page 69 of VLSI Technology 1989 were both revealed Stacked capacitor structure. U.S. Patent No. 4742018 of S. Kimura et al. And U.S. Patent No. 4977102 of T. Ema also disclose stacked capacitors to increase capacitor capacitance. Masao Taguchi and others of Fujitsu Corporation of Japan disclosed an improved stacked capacitor structure in US Patent No. 5021357, called a fin capacitor structure, which greatly increases the capacitor capacitance and improves the accumulation density of dynamic random access memory. . T. Kaga et al. Of Hitachi, Inc., published a paper titled "A 0.29 um2 ΜΙΜ-CROWN cell and process technology for 1-Gigabit DRAMs" on page 927 of 1994 IEDM, which revealed a more advanced Known as the "MIM-CROWN structure" stacked capacitors, these capacitor structures can greatly increase the capacitance value of the capacitor and increase the accumulation density of dynamic random access memory devices. The invention discloses a novel method for manufacturing a stacked capacitor, which can greatly reduce the planar circuit layout area of the capacitor and greatly increase the capacitance of the capacitor, so it can be applied to the manufacture of stacked dynamic random access memory products with ultra-high accumulation density . ^ —1T (Please read the precautions on the back before filling in this page) This paper size is applicable to the Chinese National Standard (CNS) A4 said grid (2! 0X297mm) A7 B7 5. Description of the invention () 3. Brief description of the invention The main object of the present invention is to provide a method for manufacturing a high-capacity stacked capacitor. Another object of the present invention is to provide a method for manufacturing a stacked dynamic random access memory with high packing density. The main method of the present invention is as follows. First, a standard process is used to form the field oxide layer required for isolating the metal oxide semi-field effect transistor on the sand semiconductor wafer, then, the metal oxide semi-field effect transistor is formed, and then the metal oxide semi-field effect transistor polycrystalline sand gate is formed (Polysilicon gate electrode) at the same time polysilicon wordline (polysilicon wordline) is also formed. Then, a layer of first dielectric layer, second dielectric layer and amorphous silicon are deposited, and the first Two dielectric layers. Then, the first dielectric layer, the second dielectric layer and the amorphous silicon are etched away in the capacitor region by using lithography technology and plasma etching technology to form a cell contact. In the future, the charge storage electrode of the stacked capacitor will make electrical contact with the source electrode of the metal oxide semi-field effect transistor through the memory cell contact window. Next, a very thin layer of polysilicon Hemi-Spherical Grain (HSG) is formed. The "thin polysilicon Hemi-Spherical Grain" (HSG) does not fill the memory cell contact window. Next, the "thin polycrystalline silicon hemispherical crystal grains" and "amorphous silicon" outside the capacitor area are etched using lithography and electroviolet etching techniques. Then, the natural oxide layer on the surface of the amorphous silicon is removed, and in the case of high voids greater than 10 · 6 tori, the amorphous silicon is tempered to form on the side surface of the amorphous silicon Raw sugar surface. The "thin polycrystalline silicon hemispherical crystal grains", "amorphous silicon" and "raw sugar surface" constitute the charge storage electrode of the capacitor. Since the surface of the charge storage electrode is rough and uneven, it can increase the surface area of the charge storage electrode Increase the capacitance of the capacitor and increase the accumulation density of dynamic random access memory. Finally, a capacitor dielectric layer and polycrystalline silicon are formed on the surface of the charge storage electrode, and then the capacitor dielectric layer and polycrystalline silicon are etched using lithography technology and saturation etching technology to form an electrical circuit The upper electrode of the valley (plate electrode), a kind of stacking type with the electric valley and the accumulation density of the cylinder, is printed and printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs-binding (please read the notes on the back first (Fill in this page again) The dynamic random access memory is completed in Yan. This paper standard applies to China National Standards (CNS) A4 format (210X297 mm) A7 B7 Central Sample Bureau of the Ministry of Economic Affairs Employee Consumer Cooperative Printed Poly. 5. Description of invention () 4. Brief illustration of the figure 1 to figure Nine is a schematic cross-sectional view of the manufacturing process according to an embodiment of the present invention. FIG. 1 is a schematic cross-sectional view of the manufacturing process after forming a transfer gate transistor and word lines on a silicon semiconductor wafer; FIG. 2 is a deposition of a first dielectric layer and a second dielectric layer The schematic diagram of the cross-sectional view of the electrical layer after the second dielectric layer is planarized; FIG. 3 is the schematic cross-sectional view of the process after depositing a layer of amorphous silicon and forming a photoresist pattern using lithography; FIG. 4_ is the etching using electric award Technology is a schematic cross-sectional view of a process after a capacitor region touches the first dielectric layer, the second dielectric layer, and the amorphous sand to form a memory cell contact; FIG. 5 is the removal of the light Schematic cross-sectional view of the process after resist pattern; Figure 6 is a schematic cross-sectional view of the process after forming a thin layer of polysilicon Hemi-Spherical Grain (HSG); Figure 7 is the use of lithography technology and electrical Etching technology is used to etch the "thin polycrystalline silicon hemispherical grains" and "amorphous silicon" outside the capacitor area; Figure 8 is the process after tempering the "amorphous silicon" Figure 9 is a schematic cross-sectional view of the process after tempering the "amorphous silicon" to form a rough surface on the side surface of the amorphous silicon. 5. Embodiments of the invention Please refer to Figure 1 now. First, a field oxide layer 12 is formed on a P-type sand with a resistance value of about 2.5 ohm-cm and a lattice direction (Ί00) _semiconductor wafers. The field oxide layer 12 is usually made using conventional local oxygen Technology (LOCQS) is formed by oxidizing the P-type conductive substrate 10, and its thickness is between J500 angstroms and angstroms, which is used for isolating metal oxide half-field effect heavy crystals. Of course, the traditional shallow trench isolation technology (ShallowTrench Isolation; STi) can also be used to form the field oxide layer 12 required for isolating the metal oxide half field effect transistor. Then, a metal-oxygen half-field transistor is formed on the surface of the P-type silicon semiconductor wafer 10, and the metal-oxygen half-field transistor includes a gasification switch, a gas electrode 16A, a capped oxide layer 18 (cappedoxide), and a light Doped source / drain 20A / 20B 'silicon dioxide sidewall spacer 22 and N + source / drain 24A / 24B, as shown in FIG. In addition, the word line 16B is formed at the same time as the gate 16A is formed, as shown in FIG. Please refer to Figure 1 again. The gate oxide layer 14 is formed by thermally oxidizing silicon atoms on the surface of the P-type silicon semiconductor wafer 10 in a high-temperature environment containing dry oxygen, and its oxidation temperature is between M0 and 10000 ° C. Its thickness is between .50 and 2Q0 Angstroms. The gate electrode 16A is generally made of polycrystalline sand 16 or tungsten polycrystalline sand (polycide) formed by low pressure chemical vapor deposition (LPCVD). If it is made of polycrystalline sand, its thickness is between 200. Between 4,000 and 400 Angstroms, if it consists of tungsten polycrystalline silicide, the thickness of the lower polycrystalline silicon is between 1000 and 2000 Angstroms, and the thickness of the upper tungsten silicide is between 1000 and 2000 Angstroms The total thickness is also between 2000 and 4000 Angstroms. The covering oxide layer 18 is formed by using low-pressure chemical vapor deposition to form undoped diargonated sand, and its thickness is between 800 and 1600 angstroms. Then, the photolithography technology and thunder plasma uranium etching technology are used to cover the oxide layer 18 and the polysilicon 16 or tungsten polysilicide to form the gate structure 14 / 16A / 18 of the transfer gate transistor ( gate structure), as shown in Figure 1. This paper scale is applicable to the Chinese National Standard (CNS) A4 format (210 > < 297mm) nn II ^ i 111 (please read the precautions on the back before filling this page) A7 B7 Central Standards Bureau of Ministry of Economy Employee's Consumer Cooperative Imprint V. Description of the invention () The reaction temperature for forming the polycrystalline silicon 16 is between 500 and 700 ° C, and the formed polycrystalline silicon 16 can be undoped and then implanted with ions The technology is doped to make it conductive, the ion implantation dose is between 1E] 3 to 1E16 atoms / cm 2, and the ion implantation energy is between 30 to 80 Kev to complete the complex crystal Doping of silicon 16. Of course, in-situ doped (in-situ doped) can also be used to dope the polycrystalline silicon 16, the reaction gas is PH3, SiH4 and N2 mixed gas or AsH3, For the mixed gas of SiH4 and N2, the final phosphorus ion concentration is between 1E20 and 1E21 atoms / cubic centimeter, while the ideal phosphorus ion concentration is between 5E20 atoms / cubic centimeter. For the electro-etching of the polycrystalline silicon 16, the magnetic field-enhanced active ion ion thunderbolt engraving technique (MERIE) 'The reaction gas is a mixture of sulfur hexafluoride, chlorine and hydrogen bromide The gas can provide the internal contact etching, etching rate and etching uniformity with a quite ideal effect. The selectivity of the polysilicon 16 to the gate oxide layer 14 is greater than that of Qiong and not high. Please refer to Figure 1 again. Next, phosphorus ion implantation technology is used to form the N-lightly doped source / drain 20A / 20B of the transfer gate transistor, and the ion implantation dose is between 1E13 to 3F.14 atoms / cm 2, The ion implantation energy is between 20 and 50 Kev. As shown in Fig. 1, the N-lightly doped source / drain is to reduce the hot carrier effect and improve the reliability of the transfer gate transistor Sex. Next, a layer of silicon dioxide 22 is deposited, and a vertical unidirectional etch back is performed on the silicon dioxide 22 using a magnetic field-enhanced active ion type electro-etching etching technology to form two on the two sides of the gate 16 Oxidized sand sidewall sub22. The silicon dioxide 22 is usually non-impurity-formed sand formed by low-pressure chemical vapor deposition, and the reaction gas is silicon methane or Zuzuji political salt (Si (C2H5〇) 4) and oxygen. The reaction temperature is between 600 and 800 ° C, the reaction pressure is between 0.2 and 0.4 Torr, and the thickness is between 1000 and 2500 Angstroms. Finally, using ion arsenic implantation technology to form N + source 24A / drain 24B, the ion implantation dose is between 1E15 and only atoms / cm2, and the ion implantation energy is between 80 Kev to provide Good ohmic contact, as shown in Figure 1. Now please refer to Figure 2, Figure 3, Figure 4 and Figure 5. After the manufacture of the transfer gate transistor and word line 16B is completed, a first dielectric layer 26 and a second dielectric layer # 8 are deposited, and chemical mechanical polishing is used (Chemical Mechanical Polishing: CMP) Plane the second dielectric layer 28 as shown in FIG. 2. Next, a layer of amorphous silicon 30 (amorphous silicon) is deposited, and a photoresist pattern 32 is formed over the IP. Capacitor area using lithography, as shown in FIG. The amorphous silicon 30 is formed by a low-pressure chemical vapor deposition method, the reaction gas is silane, the reaction temperature is between 500 ° C and 55Q; between C, the reaction pressure is between 150 mtorr and 250 mtorr, and the thickness Between 3000 and 8000 angstroms. Next, using the photoresist pattern 2_2 as an etching shield, the first dielectric layer 26 and the second dielectric layer 28 and the amorphous silicon 30 above the five + source electrode 24A are etched using a plasma etching technique To expose the N + source electrode 24A, so that the amorphous silicon 30 becomes an amorphous silicon 30A, to form a memory cell contact 33 (node contact) in the N + source electrode 24A region, as shown in FIG. 4, remove After the photoresist pattern 32, as shown in FIG. In the future, the charge storage electrode of the stacked capacitor will make electrical contact with the N + source 24A of the transfer gate transistor through the memory cell contact window. & This paper standard is applicable to the Chinese National Standard (CNS) Α4 present format (210Χ297mm) (please read the precautions on the back before filling out this page) • Installed. Order A7 B7 Ministry of Economic Affairs Central Standardization Bureau Staff Consumer Cooperation Du Printing 5. Description of the invention (1) The first dielectric layer 26 may be a doped silicon dioxide formed by low pressure chemical vapor deposition (LPCVD) with a reaction temperature ranging from 330 to 37 °. (: Between, the reaction gas is tetrahexyl silicate (TEOS) and nitric oxide (N2〇) or methane (silane) and nitric oxide (N2〇), the thickness is between Angstrom and Angstrom. The second dielectric layer 28 is formed by chemical vapor deposition, and its thickness is between 20α and 90 angstroms. For the first dielectric layer 26 and the second dielectric layer 28. Plasma etching to form the memory cell contact window 33. Magnetic field enhanced active ion electro-etching technology (MERIE) or electron cyclotron resonance plasma etching technology or traditional living parts can be used. Uranium engraving ^ (㈣, and usually uses magnetic field enhanced active ion plasma etching technology, the plasma reaction gas is trifluorohydrocarbon and argon gas, for example, the type DRM etching made by Japan Electric Company (TEL) The etching principle of the DPS type etching machine manufactured by the machine or applied materials of the United States belongs to the field-enhanced active ion plasma etching technology, which can provide a one-way piece handsome engraving effect with similar effects. Etching uniformity, and the plasma of the P-type silicon semiconductor substrate 10 The etching selectivity is also very high. The plasma etching of the amorphous silicon 30 is also using magnetic field-enhanced movable ion ion forging shaft engraving or Lei Zizhuo's Zhenxi honey engraving technology or Chuanyun Reactive ion plasma etching technology, the plasma reaction gas is a mixed gas of sulfur hexafluoride, oxygen, chlorine and hydrogen bromide, all of which can provide quite satisfactory residual etching and etching uniformity. The etch selectivity of the second dielectric layer 28 of crystalline silicon is very high, ranging from 25 to 35. Now refer to FIGS. 6 and 7. Then, a layer of doped, thin polycrystalline silicon hemispherical crystal is formed 40 (polysilicon Hemi-Spherical Grain; HSG), the "thin polycrystalline sand hemispherical grain 40 j does not fill the memory cell contact window 33, as shown in FIG. 6. The" polycrystalline silicon hemisphere " The "type crystal grain 40" is formed by low-pressure chemical vapor deposition, its reaction temperature is between 500 and 750 ° C, and its diameter is between 200 and 800 Angstroms. Then, the use of invitation technology and heavy paste etching Technology to etch the "thin polycrystalline silicon hemispherical die 40" outside the capacitor area and "Amorphous silicon 30A", making the amorphous silicon 30A into an amorphous silicon 30B, as shown in FIG. 7. For the "thin polycrystalline silicon hemispherical crystal grain 40" and "amorphous silicon 30A" electric purple Engraving is the use of magnetic field enhanced active ion plasma etching. The plasma reaction gas is a mixed gas of sulfur hexafluoride, oxygen and hydrogen bromide, which can provide a very ideal uranium engraving rate and uniformity of uranium engraving. And, the "thin polycrystalline silicon hemispherical crystal grains 40" and [amorphous silicon 30A "have a very high etching selectivity to the second dielectric layer 28, ranging from 25 to 35. Reference now Figure 8 and Figure 9. Next, use a diluted hydrofluoric acid solution or vapor hydrofluoric acid (vaporHF) to remove the natural oxide layer on the surface of the "amorphous silicon 30A", and then in the case of high voids greater than 10.6ίΟΓΓ, Tempering the "Amorphous Silicon 30B" 88 with a tempering temperature between 550 ° C and 650 ° C, as shown in Figure 8, to form on the side surface of the "Amorphous Silicon 30B" The rough surface 50, whose diameter is between 100 and 500 angstroms, makes the "amorphous silicon 30B" into the "amorphous silicon 30C", such as Nine shows. The "thin polycrystalline silicon hemispherical crystal grains 40", "amorphous silicon 30C" and "rough surface 50" constitute the charge storage electrode 30C / 40/50 of the capacitor, since the charge storage electrode 30C / 40/50 The surface is rough and rough, so it can increase the surface area of the charge storage electrode 30C / 40/50, greatly increase the capacitance of the capacitor, and increase the random density of the memory. After completing the manufacture of the charge storage electrode 30C / 40/50, then, to The standard process is to form a very thin capacitor dielectric layer on the surface of the charge storage electrode 30C / 40/50 of the capacitor, and then form a layer (please read the precautions on the back side before filling out this page). This paper scale is applicable to the Chinese national standard (CNS > A4 wash grid (210X 297mm) 3iS ㈣ 3 A7 B7 V. Description of invention () Crystal silicon. Finally, using lithography technology and magnetic field enhanced active ion plasma etching Technology to etch the thin capacitor dielectric layer and polycrystalline silicon to form the top electrode of the capacitor (topelectrode), a stacked dynamic random access memory with high capacitance capacitor and high packing density in Yan Completed. The dielectric layer of the mine container is usually made of gasified nitride sand (Oxynitride), silicon nitride (Nitride) and silicon dioxide (〇2dd £) by the following method. First, at a temperature between 800 The charge storage electrode 30C / 40/50 composed of polycrystals is thermally oxidized between ° C and 950 ° C to form silicon oxide with a thickness between 40 angstroms and 200 angstroms. Then, at a temperature between Low-pressure chemical vapor deposition is used to form silicon nitride with a thickness between 40 Angstroms and 60 Angstroms between 650 ° C and 750 ° C. Finally, it is oxidized when the temperature is between 800 ° C and 950 ° C The silicon nitride is used to form silicon oxide nitride with a thickness between 20 angstroms and 50 angstroms. Naturally, the capacitor dielectric layer may also be composed of other high dielectric constant materials, such as molybdenum pentaoxide (Ta205) , Or composed of high dielectric constant materials such as Ti02 and SrTi03. The formation method of the polycrystalline silicon is formed by low-pressure chemical vapor deposition method of simultaneous loading, and the reaction gas is PH3 'SiH4 and N2 or AsH3, SiH4 The mixed gas with N2 is doped with impurity atoms such as phosphorus and arsenic. Its reaction temperature is between m and 650 ° C. Its thickness Between 1000 and 2000 angstroms, the second polycrystalline silicon must also have high conductivity, and its impurity ion concentration is between 1_ ^ 0 and 1E21 atoms / cubic centimeter, while the ideal concentration is 5E20 atoms / Cubic centimeter. The plasma etching of the upper electrode forming the capacitor can use magnetic field enhanced active ion plasma etching technology (MERIE), the plasma reaction gas is a mixed gas of sulfur hexafluoride, oxyhydrogen and hydrogen bromide 》 The above is a description of the present invention with the preferred embodiments, rather than limiting the present invention, and anyone familiar with semiconductor technology can understand that appropriate and slight changes and adjustments will still not lose the essence of the present invention. Without departing from the spirit and scope of the present invention. ---------- Binding (please read the note on the back ^ • item before filling out this page) This paper printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is suitable for China National Standards (CNS) (2丨 〇χ297 foot)