316327 A7 B7 五、發明説明（） 經濟部中央標準局貝工消費合作社印製 1. 發明之技術領域 本發明是關於積體電路之動態隨機存取記憶體之電容器的的製造方法，特別是 關於堆疊式動態隨機存取記憶體之電容器的的製造方法。 2. 發明背景 典型的動態隨機存取記憶體是在矽半導體晶圓上製造一個金氧半場效電晶體與 電容器，並利用所述金氧半場效電晶體的源極來連接電容器的下層電極以形成動態 隨機存取記憶體的記憶元。數目龐大的記憶元聚集成爲記憶元陣列。另一方面，在 記憶元陣列的附近則有其它電路圍繞，例如感測放大器等電路，這些外部電路，稱 爲週邊電路區域（peripheral circuit)。因此，要達到動態隨機存取記憶體之髙積集密 度的目的，必需縮小記憶體之記憶元的尺寸，然而電容器尺寸的縮小會降低電容 値，使得記憶體電路的訊號/雜訊（SignalNoise ; S/N)比例降低，造成電路靈判或 電路不穩定等缺點。職是之故，爲了達成高積集密度的動態隨機存取記憶體，必需 尋找更尖端的製程技術，以在降低記憶元之平面電路佈局面稹之同時，能夠維持或 增加電容器之電容値。 電容器由下層電極、電容器介電層和上層電極組成，電容器之電容的公式是C = £A/T，其中，ε是電容器介電層（capacitor dielectric)之介電常數，A是電容器下 層電極之表面積，T是電容器介電層之厚度，因此，要增加電容器之電容可以從兩 個方向著手，第一個方向是採用高介電常數的材料作爲電容器介電層，例如， Ta205、Ti〇2和SrTi03材料都具有非常數，可惜，由於這些高介電常 數的材料之薄膜品質不佳，存在有絕緣#奔#壓等可靠性問題，因此到目前爲 止還無法應用到動態隨機存取記憶體。方向是增加電容器下層電極之表面 積，而最進新崛起的增加電容器下層電極乏^面積之方法是所謂的半球型晶粒技術 (Hemi-Spherical Grain ; HSG)，所述「半球型晶粒技術」是沉積一層具有半球型晶 粒之複晶矽以作爲電容器之下層電極，所述「半球型晶粒」提供了粗糙的表面 (rugged surface)，可以增加電容器下層電極之表面積，故能增加電容器之電容， 問題是，到目前爲止，上還無法控制半球g晶粒製程之表面積。 本發明揭露了一種新穎的堆疊式電容器的製造方法，可以:¾隔縮4、電容器之平 面電路佈局面積和大幅提高電容器的電容，因此能應用在超高集積密度之堆疊式動 態隨機存取記憶體產品的製造。. 3. 發明之簡要說明 本發明的主要目的是提供一種具有高電容之堆疊式電容器的製造方法。 本發明的另一個目的是提供一種髙集積密度之堆叠式動態隨機存取記億體的製 造方法。 (请先閱讀背面之注^^項再填寫本頁) —裝. 訂 '^^ 本紙张尺度遄用中國國家橾準（CNS ) A4規格（2丨〇 X 297公釐） 316327 經濟部中央揉準局負工消费合作社印策 A7 B7 五、發明説明（） 兹簡述本發明之主要方法如下。首先，在矽半導體晶圓上形成場氧化層·、複晶 砂字語線和轉移閘電晶體（transferred gate transistor)，所述轉移閘電晶體通常是由 金氧半場效電晶體構成，包含有閘氧化層、閘極、與源極/汲極。接著，沈積~層第 一絕緣層，並平坦化所述第一絕緣層，再利用微影技術與電漿蝕刻技術蝕刻所述第 一絕緣層以形成記憶元接觸窗（cellcontact)，然後，沈積一層第一複晶矽。 接著，沈積一層由第一介電層、第二介電層、第三介電層、第四介電層和第 五介電層組成之交替層結構（alternating layers structure)，然後’利用微影技術與触 刻技術蝕刻所述交替層結構，以形成一對由所述第一介電層、第二介電層、第三介 電層、第四介電層和第五介電層構成之圖案，而在圖案之間形成間隙。利用熱分解 化學氣相沉積法形成之所述第二介電層與第四介電層在稀釋氫氟酸溶液中的蝕刻率 遠大於利用低壓化學氣相沉積法形成之所述第第一介電層、第三介電層和第第五介 電層。 接著，利用稀釋氫氟酸蝕刻由所述第一介電層、第二介電層、第三介i曹、第 四介電層和第五介電層構成之一對交替層結構圖案，以在所述第一介電層跟第三介 電層之間、第三介電層跟第五介電層之間形成側向的凹陷（lateralrecess)。接著， 沈積一層第二複晶矽，所述第二複晶矽塡滿所述一對交替層結構圖案之間隙。 利用電漿蝕刻技術對所述第二複晶矽進行垂直單向性的回蝕刻，以在由所述第 一介電層、第二介電層、第三介電層、第四介電層和第五介電層構成之一對交替層 結構圖案之二側形成第二複晶矽側壁物' 在所述間隙內形成第二複晶矽側插塞物。 接著，利用稀釋氫氟酸去除所述第一介電層、第二介電層、第三介電層、第四介電 層和第五介電層構成之一對交替層結構圖案，所述第一複晶矽、第二複晶矽側壁物 和第二複晶矽側插塞物構成電容器之下層電極（bottomelectrode)。最後，形成一層 電容器介電層（capacitordielectric)和上層電極（topelectrode)，一種具有高電容和 高集積密度之堆叠式動態隨機存取記憶體於焉完成。 4.圖示的簡要說明 圖一是先前技藝的製程剖面示意圖，其各層次編號跟圖十相同。 圖二到圖十是本發明之實施例的製程剖面示意圖。 圖二是在矽半導體晶圓上形成全氧半場效電晶體後的製程剖面示意圖； 圖三是沈積一層第一絕緣層，利用微影技術與電漿蝕刻技術蝕刻所述第一絕緣層以 形成記憶元接觸窗後的製程剖面示意圖； 圖四是沈積一層第一複晶矽後的製程剖面示意圖： 圖五是沈積由第一介電層、第二介電層、第三介電層、第四介電層和第五介電層組 成之交替層結構（alternating layers structure)後的製程剖面不意圖； 圖六是利用微影技術與電漿蝕刻技術蝕刻所述第一介電層、第二介電層、第三介電 層、第四介電層和第五介電層交替層結構，以形成一對由所述第一介電層、 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐） i—HL----nr‘裝------訂！—AJ. (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局爲工消費合作社印製 A7 B7 五、發明説明（） 第二介電層、第三介電層、第四介電層和第五介電層構成之交替層結構圖 案，而在交替層結構圖案之間形成間隙後的製程剖面示意圖； 圖七是利用稀釋氫氟酸蝕刻由所述第一介電層、第二介電層、第三介電層、第四介 電層和第五介電層構成之一對交替層結構圖案，以在所述第一介電層跟第三 介電層之間、第三介電層跟第五介電層之間形成側向的凹陷後的製捏剖面示 意圖， 圖八是沈積一層第二複晶矽’後的製程剖面示意圖，所述第二複晶矽塡滿所述間 隙； 圖九是對所述第二複晶矽進行垂直單向性的回蝕刻，以在由所述第一介電層、第二 介電層、第三介電層、第四介電層和第五介電層構成之一對圖案之二側形成 第二複晶矽側壁物、在所述間隙內形成第二複晶矽側插塞物（Stud)後的製程 剖面示意圖； 圖十是利用稀釋氫氟酸去除所述第一介電層、第二介電層、第三介電層、第四介電 層和第五介電層構成之一對圖案後的製程剖面示意圖，所述第一複晶矽、第 二複晶矽側壁物和第二複晶矽側插塞物構成電容器之下層電極（Gttom electrode) 0316327 A7 B7 V. Description of the invention () Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 1. Technical Field of the Invention The present invention relates to a method of manufacturing capacitors for dynamic random access memory of integrated circuits, particularly regarding Manufacturing method of stacked dynamic random access memory capacitors. 2. BACKGROUND OF THE INVENTION A typical dynamic random access memory is to fabricate a metal oxide semi-field transistor and a capacitor on a silicon semiconductor wafer, and use the source of the metal oxide semi-field transistor to connect the lower electrode of the capacitor to Memory cells that form dynamic random access memory. A large number of memory cells are gathered into a memory cell array. On the other hand, there are other circuits around the memory cell array, such as sense amplifier circuits. These external circuits are called peripheral circuits. Therefore, in order to achieve the purpose of high random density of dynamic random access memory, it is necessary to reduce the size of the memory cell. However, the reduction in the size of the capacitor will reduce the capacitance value, making the signal / noise of the memory circuit (SignalNoise; S / N) ratio is reduced, resulting in shortcomings such as circuit judgment or circuit instability. For this reason, in order to achieve a high accumulation density of dynamic random access memory, it is necessary to look for more advanced process technology to reduce or maintain the planar circuit layout of the memory cell while maintaining or increasing the capacitance of the capacitor. A capacitor consists of a lower electrode, a capacitor dielectric layer and an upper electrode. The formula for the capacitance of a capacitor is C = £ A / T, where ε is the dielectric constant of the capacitor dielectric and A is the lower electrode of the capacitor Surface area, T is the thickness of the dielectric layer of the capacitor, therefore, to increase the capacitance of the capacitor can be started from two directions, the first direction is to use a high dielectric constant material as the capacitor dielectric layer, for example, Ta205, Ti〇2 Both SrTi03 and SrTi03 have a very large number. Unfortunately, due to the poor quality of these high dielectric constant materials, there are reliability issues such as insulation # 奔 # 压, so they have not been applied to dynamic random access memory so far . The direction is to increase the surface area of the lower electrode of the capacitor, and the most recent method to increase the area of the lower electrode of the capacitor is the so-called hemispherical grain technology (Hemi-Spherical Grain; HSG), the "hemispherical grain technology" It is to deposit a layer of polycrystalline silicon with hemispherical grains as the lower electrode of the capacitor. The "hemispherical grain" provides a rough surface, which can increase the surface area of the lower electrode of the capacitor, so it can increase the capacitance of the capacitor. The problem with capacitors is that, so far, the surface area of the hemispherical g-die process cannot be controlled. The present invention discloses a novel method for manufacturing stacked capacitors, which can: ¾ shrinkage 4, the planar circuit layout area of the capacitor and greatly improve the capacitance of the capacitor, so it can be applied to ultra-high accumulation density stacked dynamic random access memory Manufacturing of body products. 3. Brief description of the invention The main object of the present invention is to provide a method for manufacturing a stacked capacitor with high capacitance. Another object of the present invention is to provide a method for manufacturing stacked dynamic random access memory devices with high accumulation density. (Please read the note ^^ item on the back and then fill in this page) — Binding. Order '^^ This paper size adopts the Chinese National Standard (CNS) A4 specification (2 丨 〇X 297mm) 316327 The quasi-bureau of negative work consumer cooperatives printed A7 B7 V. Description of the invention () The main methods of the present invention are briefly described as follows. First, a field oxide layer, a polycrystalline sand word line, and a transferred gate transistor are formed on the silicon semiconductor wafer. The transfer gate transistor is usually composed of a gold-oxygen half-field effect transistor, including Gate oxide, gate, and source / drain. Next, a first insulating layer is deposited, and the first insulating layer is planarized, and then the first insulating layer is etched using photolithography technology and plasma etching technology to form a cell contact, and then deposited A layer of first polycrystalline silicon. Next, deposit an alternating layer structure composed of the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer, and then use the lithography Technology and contact etching technology to etch the alternating layer structure to form a pair of the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer and the fifth dielectric layer Pattern, and a gap is formed between the patterns. The etching rate of the second dielectric layer and the fourth dielectric layer formed by thermal decomposition chemical vapor deposition in diluted hydrofluoric acid solution is much greater than that of the first dielectric formed by low pressure chemical vapor deposition The electric layer, the third dielectric layer and the fifth dielectric layer. Next, a pair of alternating layer structure patterns composed of the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer and the fifth dielectric layer are etched using diluted hydrofluoric acid to A lateral recess is formed between the first dielectric layer and the third dielectric layer, and between the third dielectric layer and the fifth dielectric layer. Next, a layer of second polycrystalline silicon is deposited, and the second polycrystalline silicon fills the gap between the pair of alternating layer structure patterns. Performing a vertical unidirectional etch-back on the second polycrystalline silicon using a plasma etching technique, so that the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer Form a pair of alternating layer structure patterns with the fifth dielectric layer to form a second polycrystalline silicon sidewall object on both sides of the alternating layer structure pattern. A second polycrystalline silicon side plug is formed in the gap. Then, using diluted hydrofluoric acid to remove the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer to form a pair of alternating layer structure patterns, the The first polycrystalline silicon, the second polycrystalline silicon sidewall object, and the second polycrystalline silicon side plug form a bottom electrode of the capacitor. Finally, a capacitor dielectric layer and a top electrode are formed. A stacked dynamic random access memory with high capacitance and high packing density is completed. 4. Brief description of the figures Figure 1 is a schematic cross-sectional view of the manufacturing process of the prior art, and the numbering of each level is the same as that of Figure 10. Figures 2 to 10 are schematic cross-sectional views of the manufacturing process of an embodiment of the present invention. Figure 2 is a schematic cross-sectional view of the process after forming a full-oxygen half field effect transistor on a silicon semiconductor wafer; Figure 3 is a layer of a first insulating layer deposited, and the first insulating layer is etched using lithography and plasma etching techniques to form Schematic cross-sectional view of the process behind the memory cell contact window; Figure 4 is a schematic cross-sectional view of the process after depositing a layer of first polycrystalline silicon: Figure 5 is a deposition of the first dielectric layer, the second dielectric layer, the third dielectric layer, the first The process cross-section after the alternating layers structure composed of the four dielectric layers and the fifth dielectric layer is not intended; FIG. 6 is the etching of the first dielectric layer and the second by using photolithography technology and plasma etching technology The dielectric layer, the third dielectric layer, the fourth dielectric layer and the fifth dielectric layer alternate layer structure to form a pair of the first dielectric layer, this paper standard is applicable to China National Standard (CNS) A4 Specifications (210X297mm) i-HL ---- nr 'loaded ------ ordered! —AJ. (Please read the precautions on the back before filling out this page) The Central Bureau of Standards of the Ministry of Economy prints A7 B7 for industrial and consumer cooperatives. V. Description of invention () Second dielectric layer, third dielectric layer, fourth media Alternating layer structure pattern composed of the electric layer and the fifth dielectric layer, and a schematic cross-sectional view of the manufacturing process after forming a gap between the alternating layer structure patterns; FIG. 7 is the use of diluted hydrofluoric acid etching to form the first dielectric layer, the first The second dielectric layer, the third dielectric layer, the fourth dielectric layer and the fifth dielectric layer constitute a pair of alternating layer structure patterns so that between the first dielectric layer and the third dielectric layer, the first FIG. 8 is a schematic cross-sectional view of the process after depositing a layer of second polycrystalline silicon, and the second polycrystalline silicon is full The gap; FIG. 9 is a vertical unidirectional etch-back of the second polycrystalline silicon, so that the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric An electrical layer and a fifth dielectric layer constitute a pair of patterns, a second polysilicon sidewall object is formed on both sides of the pattern, A schematic cross-sectional view of the process after forming a second polycrystalline silicon side plug (Stud) in the gap; FIG. 10 is the use of diluted hydrofluoric acid to remove the first dielectric layer, the second dielectric layer, and the third dielectric layer, The fourth dielectric layer and the fifth dielectric layer constitute a pair of patterned cross-sectional schematic diagrams of the manufacturing process, the first polycrystalline silicon, the second polycrystalline silicon sidewall object and the second polycrystalline silicon side plug constitute a capacitor Lower electrode (Gttom electrode) 0
5. 發明之實施例I 現在請參考圖二。首先’在在電阻値約2·5 ohm-cm、晶格方向（100)之P型 矽半導體晶圓2上形成場氧化層4，所述場氧化層4通常是利用利用習知的局部矽 氧化技術形成（LOCOS)，其厚度介於3500到6500埃之間，作爲隔離金氧半場 效電晶體之用。當然’也可以利用傳統的淺凹溝隔離技術（Shallow Trench Isolation ; STI)來形成隔離金氧半場效電晶體所需之場氧化層4。然後，在所述場 氧化層4以外的所述P型矽半導體晶圓2表面形成轉移閘電晶體（transferred gate transistor)，所述轉移閘電晶體通常是由金氧半場效電晶體構成，包含有閘氧化層 6、 閘極8、N-源極/汲極12、覆蓋氧化層10 (capped oxide)、二氧化矽側壁子14 與N+源極16A/汲極16B，如圖二所示。另外，在形成閘極8之同時也形成複晶矽 字語線，所述複晶矽字語線未顯示於圖示。 請再參考圖二。所述閘氧化層6是在含乾氧的高溫環境中熱氧化所述P型矽半 導體基板2之表面之矽原子而成，其氧化溫度介於850到1000 °C之間，其厚度介 於50到200埃之間。所述閘極8則一般是由低壓化學氣相沉積法（LPCVD)形 成之複晶矽8或鶴複晶矽化物所構成，若由複晶矽構成，其厚度介於2000到4000 埃之間，若由鎢複晶矽化物構成，則下層複晶矽之厚度介於1000到2000埃之 間，上層矽化鎢之厚度介於1000到2000埃之間，其總厚度也是介於2000到 4000埃之間。所述覆蓋氧化層_ 10是利用低壓化學氣相沉積法形成之無摻雜的二氧 化矽，其厚度介於800到1600埃之間。然後，利用微影技術與電漿蝕刻技術餓亥$ 所述覆蓋氧化層10和複晶矽8或鎢複晶矽化物，以形成所述轉移閘電晶體之閘極結 構（gate structure)，如圖二所示》 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） - - - . - =· n^i fcm H HI m I n 一h —I— (n ΙΓΙ (請先閏讀背面之注意事項再填寫本頁) 316327 A7 B7 經濟部中央標準局員工消費合作社印装 五、發明説明（） 形成所述複晶矽8之反應溫度介於500到700 °c之間’而形成之複晶砂8可 以未經摻雜，然後再利用離子佈植技術予以摻雜使具導電性’其離子佈植劑量介於 1E13到1E16原子/平方公分之間’離子佈植能量則介於3〇到80 Kev之間，以完 成對所述複晶矽8之摻雜。當然’也能利用同步磷離子攙雜方法O-situ doped)以 完成對所述複晶矽8之摻雜，其反應氣體是PH3、SiH4與N2的混合氣體或 AsH3、SiH4與N2的混合氣體，最後的磷離子濃度介於1E20到1E21原子/立方公 分之間，而較理想的磷離子濃度是5E20原子/立方公分之間。對所述複晶矽8之電 漿蝕刻，其反應氣體則是由SF6、Cl2和HBr組成之混合氣體。 請再參考圖二。接著，利用磷離子佈植技術來形成所述轉移閘電晶體之N•源 極/汲極12，其離子佈植劑量介於1E13到3E14原子/平方公分之間’離子佈植能 量則介於20到50 Kev之間，如圖一所示，所述N·源極/汲極12是爲了降低熱載 子效應，以提髙所述轉移閘電晶體之可靠性。接著，沉積一層二氧化矽14，並利用 磁場增強式活性離子式電漿蝕刻技術對所述二氧化矽14進行垂直單向性的回蝕 刻，以在所述閘極8之二側形成二氧化矽側壁子14。而所述二氧化矽14通常是利 用低壓化學氣相沉積法形成之無攙雜的二氧化矽，其反應氣體是矽甲烷或四已基矽 酸鹽（Si(C2H50)4)和氧氣，反應溫度約720 °C，反應壓力介於0.2到0.4托爾之 間，厚度介於500到1500埃之間。最後，利用離子砷佈植技術形成N+源極16A/ 汲極16B，其離子佈植劑董介於1E15到5E16原子/平方公分之間，離子佈植能量則 介於30到80 Kev之間，以提供良好的歐姆接觸，如圖二所示。 現在請參考圖三與圖四。完成所述轉移閘電晶體和字語線的製造後，接著，沈 積一層第一絕緣層20，並利用化學機械式琢磨技術（Chemical Mechanical Polishing ; CMP)平坦化所述第一絕緣層20，再接著利用微影技術與電漿蝕刻技術 蝕刻N+源極16A上方之所述第一絕緣層20以露出所述N+源極16A，以在所 述N+源極16A區域形成記憶元接觸窗22 (cell contact)，如圖三所示，未來，堆 疊式電容器之下層電極將透過所述記憶元接觸窗22跟所述轉移閘電晶體之N+源 極16A作電性接觸。然後，沈積一層第一複晶矽24，如圖四所示。 所述第一絕緣層20通常是利用低壓化學氣相沉積法形成之攙雜的或無攙雜的 二氧化矽，其厚度介於3000到8000埃之間。對所述第一絕緣層20之電漿蝕刻 以形成所述記憶元接觸窗22，可以利用磁場增強式活性離子式電漿蝕刻技術 (MERIE)或電子迴旋共振電漿蝕刻技術（ECR)或傳統的活性離子式電漿蝕刻技 術（RIE) ’而通常是利用磁場增強式活性離子式電獎触刻技術，其電獎反應氣體是 三氟氫化碳和氬氣，例如，曰本電氣公司（TEL)所製造型號TEL8500之蝕刻機或 美國應用材料公司（appliedmaterials)所製造型號PR5000E'之触刻機，其蝕刻原理 均屬於磁場增強式活性離子式電漿蝕刻技術。所述第一複晶矽24通常是利用同步 磷原子攙雜之低壓化學氣相沉積法形成，其反應氣體是PH3、SiH4與N2的混合氣 體’反應溫度介於500到650 °C之間，其厚度介於1000到3000埃之間，其磷離子 (錆先閱讀背面之注^項再填寫本頁) .裝· 訂 .-- - - . 本紙張尺度適用中國國家橾準（CNS ) Α4規格（210X297公釐） 經濟部中央橾準局具工消費合作社印製 A7 B7 五、發明説明（） 濃度介於1E20到1E21原子/立方公分之間，而較理想的濃度是5E20原子/立方公 分。 , 現在請參考圖五與圖六。接著，沈積一層第一介電層30、第二介電層32、第 三介電層34、第四介電層36和第五介電層38，如圖五所示。然後，利用微影技術 與電漿蝕刻技術蝕刻所述第一介電層30、第二介電層32 '第三介電層34、第四介 電層36和第五介電層38，以形成一對由所述第一介電層30、第二介電層32、第 三介電層34、第四介電層36和第五介電層38構成之圖案，而在圖案之間形成間 隙39，蝕刻停止在所述第一複晶矽24表面，如圖六所示。 , 所介電層30、第三介電層34 介電層38是利用低壓化學氣 / 相沉積法（Low Pressure Chemical Vapor Depositi^if^LPCVD)形成之無攙雜的二氧 化矽，其反應溫度介於600到800 °C之間，其反應氣體是只利用四已基矽酸鹽 (TE0S)，其厚度是介於200埃到500埃之間。所述第二介電層32與寒@介電 層36則是利用熱分解化學氣相沉積法（thermal Chemical Vapor DeposSTon ; thCVD)形成之二氧化矽，其反應溫度介於330到370 °C之間，其反應氣體是四已 基矽酸鹽（TEOS)與臭氧（03)，其厚度介於200埃到500埃之間。例如，美國 應用材料公司（appliedmaterials)曾製造利用熱分解化學氣相沉積法形成之二氧化矽 的機器。 請特別注意，利用熱分解化學氣相沉積法形成之所述第二介電層32與第四介 €6在稀釋氫氟酸溶液中的蝕刻大於利用低壓化學氣相沉積法形成之所述 介電層.30、第三介電層34 _第>介電層38，這是因爲以四已基矽酸鹽與 :爲反應氣體之熱分解化學氣沉#法形成之二氧化矽薄膜的特性相當鬆散 (porous)，例如，以美國應用材料公司所製造之熱分解化學氣相沉稹法機^^ 所述第二介電層32與第四介電在稀釋氫氟酸溶液中的蝕刻率大於所述^^ 介電層30 '第三介電層34 介電層38的十倍以上。 形成一對由所述第一介電層30、第二介電層32、第三介電層34、第四介電 層36和第五介電層38構成之圖案之電漿蝕刻，可以利用磁場增強式活性離子式電 漿蝕刻技術（MERIE)或電子迴旋共振電漿蝕刻技術（ECR)或傳統的活性離子式 電漿蝕刻技術（RIE)，通常也是利用磁場增強式活性離子式電漿蝕刻技術，其電漿 反應氣體是CHF3、〇2和Ar等氣體。 現在請參考圖七與圖八。^著，利用稀釋氫氟酸蝕刻由所述第一介電層30 ' 第二介電層32、第三介電層34、第四介電層36和第五介電層38構成之一對圖 案，以在所述第一介電層30踉第三介電層34之間、第三介電層34跟第五介電層 38之間形成側向的凹陷（laterairecess )，使圖案之間的間隙39成爲間隙40，而間 40的表面積大於藺隙39的表面積，去除該光阻圖案後，如圖七所示。之所以能 (形成側向的凹陷（lateralrecess)，使圖案之間的間隙39成爲間隙40，是因爲所述 k第二介電層32與第四介電層36在稀釋氫氟酸溶液中的蝕刻率遠大於所述第第一介 本纸張尺度逍用中國國家樣準（CNS > A4规格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) _裝· 訂 經濟部中央揉準局貝工消費合作社印製 A7 B7 五、發明説明（） /電層30、第三介電層34 介電層38 ,這是本發明關鍵之一。接著’沈積一 \層第二複晶矽42，所述第二複^矽42塡滿所述間隙40，如圖八所示。 所述第二複晶矽42通常是利用同步磷原子攙雜之低壓化學氣相沉積法形成’ 其反應氣體是PH3、SiH4與N2的混合氣體，反應溫度介於500到650 °C之間， 其厚度介於1〇〇〇到3000埃之間，其碟離子濃度介於1E20到1E21原子/立方公分之 間，而較理想的濃度是5E20原子/立方公分》 現在請參考圖九與圖十。接著，利用磁場增強式活性離子式電漿蝕刻技術對所 述第二複晶矽42進行垂直單向性的回触刻，以在由所述第一介電層30、第二介電 層32、第三介電層34、第四介電層36和第五介電層38構成之一對圖案之二側形 成第二複晶矽側壁物42A、在所述間隙40內形成第二複晶矽側插塞物42B ’如圖 九所示。對所述第二複晶矽42之垂直單向性的回蝕刻，是利用磁場增強式活性離 子式電漿蝕刻技術，其反應氣體是六氟化硫和溴化氫氣體。接著，利用稀樓£截酸 去除所述第一介電層30、第二介電層32、第三介電層34、第四介電層36和第五 介電層38構成之一對圖案，所述第一複晶矽24、第二複晶矽側壁物42A和第二複 晶矽側插塞物42B構成電容器之下層電極（bottom electrode)，如圖十所示。由所 述第一複晶矽24、第二複晶矽側壁物42A和第二複晶矽側插塞物42B構成之電容 器之下層電極具有起伏不平的的表面，起伏不平的的表面提供了較大的表面積’故 能提供較大的電容器電容。 最後，在所述下層電極的表面形成一層電容器介電層（capacitor dielectric)和 第三複晶矽，再利用微影技術和電漿蝕刻技術蝕去電容器區域以外之所述電容器介 電層和第三複晶矽，以形成電容器的上層電極（top eiectrode)，一種具有髙電容和 高集積密度之堆疊式動態隨機存取記憶體於焉完成。 所述電容器介電層通常是由氧化氮化矽（Oxynitride)、氮化矽（Nitride)和氧 化矽（Oxide)藉由下述方法形成。首先，在溫度介於850°C到950°C之間時熱氧化 由複晶矽構成之所述下層電極，以形成厚度介於40埃到200埃之間的氧化矽。接 著，在溫度介於650°C到750°C之間時以低壓化學氣相沉積法形成厚度介於40埃 到60埃之間的氮化矽。最後，在溫度介於850°C到950°C之間時氧化該氮化矽，以 形成厚度介於20埃到50埃之間的氧化氮化矽。自然，所述電容器介電層亦可由其 它高介電常數材料組成，例如五氧二钽（Ta205 )，或由Ta205、Ti02和SrTi03 等材料所組成》 · 所述第三複晶矽之形成方法跟所述第一複晶矽24相同，通常是利用同步碟原 子攙雜之低壓化學氣相沉積法形成，其反應氣體是PH3、SiH4與N2的混合氣體， 反應溫度介於500到650 °C之間，其厚度介於1〇〇〇到2000埃之間，其磷離子濃度 介於1E20到1E21原子/立方公分之間，而較理想的濃度是5E20原子/立方公分。所 述該成電容器的上層電極之電漿蝕刻，也是利用磁場增強式活性離子式電漿蝕刻技 術，其反應氣體是由SF6、Cl2和HBr組成之混合氣體。 本紙張尺度適用中國國家梂率（CNS ) A4规格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝.5. Embodiment I of the Invention Please refer to FIG. 2 now. First, a field oxide layer 4 is formed on a P-type silicon semiconductor wafer 2 with a resistance value of about 2.5 ohm-cm and a lattice direction (100). The field oxide layer 4 is usually made of local silicon Oxidation technology formation (LOCOS), whose thickness is between 3500 and 6500 Angstroms, is used to isolate the metal oxide half field effect transistor. Of course, the traditional shallow trench isolation technology (Shallow Trench Isolation; STI) can also be used to form the field oxide layer 4 required for isolating the metal oxide half field effect transistor. Then, a transferred gate transistor is formed on the surface of the P-type silicon semiconductor wafer 2 other than the field oxide layer 4. The transferred gate transistor is usually composed of a metal oxide half-field effect transistor, including There are gate oxide layer 6, gate electrode 8, N-source / drain 12, capped oxide 10, capped oxide, silicon dioxide sidewall 14 and N + source 16A / drain 16B, as shown in FIG. In addition, the polysilicon word line is also formed at the same time as the gate electrode 8 is formed, which is not shown in the figure. Please refer to Figure 2 again. The gate oxide layer 6 is formed by thermally oxidizing silicon atoms on the surface of the P-type silicon semiconductor substrate 2 in a high-temperature environment containing dry oxygen. Its oxidation temperature is between 850 and 1000 ° C, and its thickness is between Between 50 and 200 Angstroms. The gate electrode 8 is generally composed of polycrystalline silicon 8 or crane polycrystalline silicide formed by low pressure chemical vapor deposition (LPCVD). If it is composed of polycrystalline silicon, its thickness is between 2000 and 4000 angstroms If made of tungsten polycrystalline silicide, the thickness of the lower polycrystalline silicon is between 1000 and 2000 Angstroms, the thickness of the upper layer of tungsten silicide is between 1000 and 2000 Angstroms, and the total thickness is also between 2000 and 4000 Angstroms between. The covering oxide layer-10 is an undoped silicon dioxide formed by low-pressure chemical vapor deposition, and has a thickness between 800 and 1600 angstroms. Then, the photolithography technology and the plasma etching technology are used to form the gate structure of the transfer gate transistor, such as the cover oxide layer 10 and the polysilicon 8 or tungsten polysilicide. Figure 2 shows this paper scale is applicable to China National Standard (CNS) A4 specifications (210X297mm)---. Leap read the precautions on the back and fill in this page) 316327 A7 B7 Printed by the Employees ’Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Fifth, the description of the invention () The reaction temperature for forming the polycrystalline silicon 8 is between 500 and 700 ° C ' The formed polycrystalline sand 8 can be undoped, and then doped using ion implantation technology to make it conductive. The ion implantation dose is between 1E13 and 1E16 atoms / cm2. The ion implantation energy is Between 30 and 80 Kev, to complete the doping of the polycrystalline silicon 8. Of course, the synchronous phosphorus ion doping method (O-situ doped) can also be used to complete the doping of the polycrystalline silicon 8. , The reaction gas is PH3, SiH4 and N2 mixed gas or AsH3, SiH4 and N2 mixed gas, the most The concentration of phosphorus ions is between 1E20 to 1E21 atoms / cubic known points, while the ideal ion concentration is between 5E20 phosphorous atoms / cc. For the plasma etching of the polycrystalline silicon 8, the reaction gas is a mixed gas composed of SF6, Cl2 and HBr. Please refer to Figure 2 again. Next, using phosphorous ion implantation technology to form the N • source / drain electrode 12 of the transfer gate transistor, the ion implantation dose is between 1E13 and 3E14 atoms / cm 2 'the ion implantation energy is between Between 20 and 50 Kev, as shown in Fig. 1, the N · source / drain 12 is to reduce the hot carrier effect and improve the reliability of the transfer gate transistor. Next, a layer of silicon dioxide 14 is deposited, and the magnetic field enhanced active ion plasma etching technique is used to perform a vertical unidirectional etch back on the silicon dioxide 14 to form dioxide on both sides of the gate 8 Silicon side wall 14. The silicon dioxide 14 is usually a doped silicon dioxide formed by low-pressure chemical vapor deposition. The reaction gas is silicon methane or tetrahexyl silicate (Si (C2H50) 4) and oxygen. The reaction temperature At about 720 ° C, the reaction pressure is between 0.2 and 0.4 Torr, and the thickness is between 500 and 1500 Angstroms. Finally, using ion arsenic implantation technology to form N + source 16A / drain 16B, the ion implantation agent is between 1E15 to 5E16 atoms / cm2, and the ion implantation energy is between 30 and 80 Kev. To provide good ohmic contact, as shown in Figure 2. Now please refer to Figure 3 and Figure 4. After the manufacture of the transfer gate transistor and the word line is completed, then a layer of first insulating layer 20 is deposited, and the first insulating layer 20 is planarized using chemical mechanical polishing (CMP), and then Next, the first insulating layer 20 above the N + source 16A is etched by using lithography and plasma etching techniques to expose the N + source 16A, so as to form a memory cell contact window 22 (cell) in the N + source 16A region contact), as shown in FIG. 3, in the future, the lower electrode of the stacked capacitor will make electrical contact with the N + source electrode 16A of the transfer gate transistor through the memory cell contact window 22. Then, a layer of first polycrystalline silicon 24 is deposited, as shown in FIG. 4. The first insulating layer 20 is usually doped or undoped silicon dioxide formed by low-pressure chemical vapor deposition, and its thickness is between 3000 and 8000 angstroms. Plasma etching of the first insulating layer 20 to form the memory cell contact window 22 may use magnetic field enhanced active ion plasma etching technology (MERIE) or electron cyclotron resonance plasma etching technology (ECR) or traditional The active ion plasma etching technology (RIE) 'is usually the use of magnetic field enhanced active ion electric award contact etching technology, the electric award reaction gas is carbon trifluoride and argon, for example, Japan Electric Company (TEL ) The etching machine made by TEL8500 or the PR5000E 'made by American Applied Materials, the etching principle belongs to the magnetic field enhanced active ion plasma etching technology. The first polycrystalline silicon 24 is usually formed by low-pressure chemical vapor deposition doped with synchronous phosphorus atoms. The reaction gas is a mixed gas of PH3, SiH4 and N2. The reaction temperature is between 500 and 650 ° C. The thickness is between 1000 and 3000 angstroms, and its phosphor ions (read the note ^ on the back before filling in this page). Packing and ordering.---. This paper size is suitable for China National Standards (CNS) Α4 specifications (210X297mm) A7 B7 printed by the Central Industry Bureau of the Ministry of Economic Affairs of the Ministry of Economic Affairs. 5. Description of invention () The concentration is between 1E20 and 1E21 atoms / cubic centimeter, while the ideal concentration is 5E20 atoms / cubic centimeter. , Please refer to Figure 5 and Figure 6 now. Next, a first dielectric layer 30, a second dielectric layer 32, a third dielectric layer 34, a fourth dielectric layer 36, and a fifth dielectric layer 38 are deposited, as shown in FIG. Then, the first dielectric layer 30, the second dielectric layer 32 ', the third dielectric layer 34, the fourth dielectric layer 36, and the fifth dielectric layer 38 are etched using lithography and plasma etching techniques, to Forming a pair of patterns composed of the first dielectric layer 30, the second dielectric layer 32, the third dielectric layer 34, the fourth dielectric layer 36 and the fifth dielectric layer 38, and forming between the patterns In the gap 39, etching stops on the surface of the first polycrystalline silicon 24, as shown in FIG. , The dielectric layer 30, the third dielectric layer 34, the dielectric layer 38 is a non-doped silicon dioxide formed by low pressure chemical vapor / phase deposition method (Low Pressure Chemical Vapor Depositi ^ if ^ LPCVD), the reaction temperature is Between 600 and 800 ° C, the reaction gas only uses tetrahexyl silicate (TEOS), and its thickness is between 200 angstroms and 500 angstroms. The second dielectric layer 32 and the cold @ dielectric layer 36 are silicon dioxide formed by thermal chemical vapor deposition (thermal chemical vapor deposition) (thCVD), and the reaction temperature is between 330 and 370 ° C The reaction gas is tetrahexyl silicate (TEOS) and ozone (03), and its thickness is between 200 angstroms and 500 angstroms. For example, American Applied Materials has manufactured silicon dioxide machines formed by thermal decomposition chemical vapor deposition. Please particularly note that the etching of the second dielectric layer 32 and the fourth dielectric layer formed by the thermal decomposition chemical vapor deposition method in the diluted hydrofluoric acid solution is greater than that of the dielectric layer formed by the low pressure chemical vapor deposition method Electrical layer .30, the third dielectric layer 34 _ 第> dielectric layer 38, this is because of the silicon dioxide film formed by the tetrahexyl silicate and the thermal decomposition of the reaction gas by chemical gas deposition # method The characteristics are quite porous, for example, the second dielectric layer 32 and the fourth dielectric are etched in a dilute hydrofluoric acid solution by a thermal decomposition chemical vapor deposition method manufactured by American Applied Materials Co., Ltd. ^^ The rate is more than ten times that of the dielectric layer 30 ', the third dielectric layer 34, and the dielectric layer 38. Plasma etching to form a pattern composed of the first dielectric layer 30, the second dielectric layer 32, the third dielectric layer 34, the fourth dielectric layer 36, and the fifth dielectric layer 38 can be used Magnetic field enhanced active ion plasma etching technology (MERIE) or electron cyclotron resonance plasma etching technology (ECR) or traditional active ion plasma etching technology (RIE), usually using magnetic field enhanced active ion plasma etching Technology, the plasma reaction gas is CHF3, 〇2 and Ar gas. Now please refer to Figure 7 and Figure 8. ^ A pair of first dielectric layer 30 ', second dielectric layer 32, third dielectric layer 34, fourth dielectric layer 36 and fifth dielectric layer 38 is formed by dilute hydrofluoric acid etching A pattern to form a lateral recess between the first dielectric layer 30 and the third dielectric layer 34, and between the third dielectric layer 34 and the fifth dielectric layer 38, so that the pattern The gap 39 becomes the gap 40, and the surface area of the gap 40 is larger than the surface area of the gap 39. After removing the photoresist pattern, as shown in FIG. The reason why (a lateral recession is formed so that the gap 39 between the patterns becomes the gap 40 is because the second dielectric layer 32 and the fourth dielectric layer 36 in the diluted hydrofluoric acid solution Etching rate is much greater than the paper size of the first media, the Chinese National Standard (CNS &A; A4 specification (210X 297mm) (please read the precautions on the back before filling out this page) _ 装 · Order economy A7 B7 printed by Beigong Consumer Cooperative of Ministry of Central Development and Customs. V. Description of invention () / electric layer 30, third dielectric layer 34 dielectric layer 38, which is one of the key points of the present invention. Then 'deposit one layer Two polysilicon 42, the second polysilicon 42 fills the gap 40, as shown in Figure 8. The second polysilicon 42 is usually formed by low-pressure chemical vapor deposition method of synchronous phosphorus atom doping 'The reaction gas is a mixed gas of PH3, SiH4 and N2, the reaction temperature is between 500 and 650 ° C, its thickness is between 1000 and 3000 angstroms, and its dish ion concentration is between 1E20 and 1E21 atoms / Cubic centimeters, and the ideal concentration is 5E20 atoms / cubic centimeters. ”Now please refer to Figure 9 and Figure 10. Next, a magnetic field-enhanced active ion plasma etching technique is used to perform a vertical unidirectional back-etching on the second polycrystalline silicon 42 so that the first dielectric layer 30 and the second dielectric The layer 32, the third dielectric layer 34, the fourth dielectric layer 36, and the fifth dielectric layer 38 constitute a pair of patterns forming a second polycrystalline silicon sidewall object 42A on both sides of the pattern, forming a second in the gap 40 The polysilicon side plug 42B 'is shown in Fig. 9. The vertical unidirectional etch back of the second polysilicon 42 is a magnetic field enhanced active ion plasma etching technology, and the reaction gas is Sulfur hexafluoride and hydrogen bromide gas. Then, the first dielectric layer 30, the second dielectric layer 32, the third dielectric layer 34, the fourth dielectric layer 36 and the first The five dielectric layers 38 constitute a pair of patterns, and the first polycrystalline silicon 24, the second polycrystalline silicon sidewall 42A and the second polycrystalline silicon side plug 42B constitute a capacitor bottom electrode, such as Fig. 10. Under the capacitor formed by the first polycrystalline silicon 24, the second polycrystalline silicon sidewall object 42A and the second polycrystalline silicon side plug 42B The electrode has an uneven surface, and the uneven surface provides a larger surface area, so it can provide a larger capacitor capacitance. Finally, a capacitor dielectric layer (capacitor dielectric) and the first layer are formed on the surface of the lower electrode Three polycrystalline silicon, and then use the photolithography technology and plasma etching technology to etch the capacitor dielectric layer and the third polycrystalline silicon outside the capacitor area to form the top electrode of the capacitor (top eiectrode), a type with high capacitance and A high-density stacked dynamic random access memory is completed in Yan. The capacitor dielectric layer is usually composed of Oxynitride, Nitride, and Oxide by the following methods form. First, the lower electrode composed of polycrystalline silicon is thermally oxidized at a temperature between 850 ° C and 950 ° C to form silicon oxide with a thickness between 40 angstroms and 200 angstroms. Next, silicon nitride with a thickness between 40 Angstroms and 60 Angstroms is formed by low-pressure chemical vapor deposition at a temperature between 650 ° C and 750 ° C. Finally, the silicon nitride is oxidized at a temperature between 850 ° C and 950 ° C to form a silicon oxide nitride with a thickness between 20 Angstroms and 50 Angstroms. Naturally, the capacitor dielectric layer may also be composed of other materials with high dielectric constant, such as tantalum pentoxide (Ta205), or composed of materials such as Ta205, Ti02, and SrTi03. The method for forming the third polycrystalline silicon The same as the first polycrystalline silicon 24, usually formed by low-pressure chemical vapor deposition method of synchronous disc atom doping, the reaction gas is a mixed gas of PH3, SiH4 and N2, the reaction temperature is between 500 and 650 ° C Its thickness is between 1000 and 2000 angstroms, its phosphorus ion concentration is between 1E20 and 1E21 atoms / cubic centimeter, and the ideal concentration is 5E20 atoms / cubic centimeter. The plasma etching of the upper electrode of the capacitor is also a magnetic field enhanced active ion plasma etching technology, and the reaction gas is a mixed gas composed of SF6, Cl2 and HBr. This paper scale is suitable for China National Frame Rate (CNS) A4 specification (210X 297mm) (please read the precautions on the back before filling this page).
、1T B7 五、發明説明（） 以上係以最佳實施例來闡述本發明，而非限制本發明，並且，熟知半導體技藝 之人士皆能明瞭，適當而作些微的改變及調整，仍將不失本發明之要義所在，亦不 脫離本發明之精神和範圍。 經濟部中央標準局工消费合作社印製 (請先W讀背面之注意Ϋ項再填寫本頁) 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐）、 1T B7 V. Description of the invention () The above is the best embodiment to explain the present invention, not to limit the invention, and the person skilled in the semiconductor technology will be able to understand, appropriate and slight changes and adjustments will still not Without losing the essence of the present invention, it does not depart from the spirit and scope of the present invention. Printed by the Industrial and Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the note Ϋ on the back before filling in this page) This paper size is applicable to China National Standard (CNS) A4 (210X297 mm)