經濟部中央樣準扃員工消費合作社印装 A7 _B7__ 五、發明説明（/ ) 1. 發明之技術領域 本發明是關於積體電路之動態隨機存取記憶體的製造方 法（Method)。 2. 發明背景 典型的堆疊式動態隨機存取記憶體是在矽半導體基板上 製造一個金氧半場效電晶體（MOSFET)與電容器 (capacitor)，並利用所述場效電晶體的源極來連接電容器 的下層電極（storagenode)以形成動態隨機存取記憶體的記 憶元（memory cell)，數眄龐大的記憶元聚集成爲記憶體積 體電路。 最近幾年，動態隨機存取記憶體的集積密度（packing density)快速增加，目前已進入記憶元尺寸1.5平方微米 (um2)之六仟四佰萬位元的量產，日本半導體公司NEC更 在1995年宣稱已經有十億位元動態隨機存取記憶體（1GB DRAM)的原型樣品問世（Prototype)。另一方面，國內的 新竹科學工業園區（Science-Based Industrial Park)的某些積 體電路公司也已經進入設計準則0.4〜0.45微米之一仟六佰萬 位元動態隨機存取記憶體的量產階段，例如，茂矽電子公司 (Mosel_Vitelic)和德碁半導體公司（TI-Acer)。 要達到動態隨機存取記憶體高度積集化的目的，必需縮 小記憶元的尺寸，亦即，必需縮小場效電晶體與電容器的尺 寸，然而電容器尺寸的縮少將降低電容値，使得記憶電路的 訊號/雜訊（Signal Noise ; S/N )比例降低，造成電路誤判或 電路不穩定等缺點。 爲了在縮小降低電容器的尺寸時能維持或增加電容器的 本紙張尺度適用中國國家標準（CMS ) A4規格（210X297公釐） 1^~~--一----裝------訂--；----点 (請先閲讀背面之注意事項再.^寫本頁) 經濟部中央標準局貝工消費合作社印製 A7 ______B7 五、發明説明（2) 電容値，以日本的富士通公司（Fujitsu)的MasaoTaguchi等 人在美國專利第5〇21357號所揭露之鰭型電容器結構（fin structure)最具代表性，另外，H.Watanabe等人在EEDM 1992也揭露了一種新穎的電容器結構。 3·發明之簡要說明 本發明之主要目的是提供一種具有高電容之堆疊式電容 器（StackCapacitor)的製造方痒。 本發明之另一個目的是提供一種高集積密度之堆疊式動 態隨機存取記憶體的製造方法。 本發明之主要製程方法如下。首先，在矽半導體基板 (Silicon Semiconductor Substrate )上利用習知的淺凹溝隔離 技術（Shallow Trench Isolation ; STI)或局部砂氧化隔離技術 形成隔離場效電晶體之氧化層。然後，利用標準製程形成場 效電晶體與字語線，所述場效電晶體包含有閘氧化層（gate oxide)、閘極（gate electrode)與源極/汲極（source/ drain) ° 接著，沈積第一介電層和第二介電層，並利用習知的化 學機械式磨光技術（Chemical Mechanical Polishing ; CMP ) 平坦化所述第一介電層，再利用微影技術與電漿蝕刻技術蝕 去所述第一介電層和第二介電層以露出所述場效電晶體之源 極，以形成場效電晶體之記憶元接觸窗（cell contact)。接 著，形成一層第一複晶砂，所述「第一複晶砂」塡滿所述 「記憶元接觸窗」。未來，電所述「第一複晶矽」將透過所 述「記憶元接觸窗」跟所述場效電晶體之源極作電性接觸。 接著’形成一層氮化矽，然後，利用熱化學氣相沉積法 (請先閱讀背面之注意事項再續寫本頁) .裝. 訂 本紙張尺度適用中國國家橾準（CNS > A4規格（210X297公釐） A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（3) (Thermal Chemical Vapor Deposition )形成一層第一熱化學 ' 氣相沉積二氧化砂（First Thermal CVD Oxide )，再利用電獎 增強式化學氣相沉積法（Plasma Enhanced Chemical Vaipor Deposition ; PECVD)形成一層第一電漿二氧化砂（First PE-Oxide)，接著，連續形成一層第二熱化學氣相沉積二氧化 矽、第二電漿二氧化砂、第三熱化學氣相沉積二氧化矽、第 三電漿二氧化矽和第四熱化學氣相沉積二氧化矽，以形成由 「熱化學氣相沉積二氧化矽」由「電漿二氧化矽」組成之交 替複層結構（altematiing layers ) ° 接著，利用微影技術和電漿蝕刻技術蝕去電容器區域 (capacitorregion)以外之所述「交替複層結構」，所述電槳 蝕亥(I終止於所述氮化矽表面。然後，利用氫氟酸溶液側向的 餓去（lateral etch ) —部份的所述「父替複層結構」’由於所 述「電漿二氧化矽」之蝕刻率遠大於所述「熱化學氣相沉積 二氧化矽」，因此’在所述「第一熱化學氣相沉積二氧化 矽」跟「第二熱化學氣相沉積二氧化砂」之間、所述「第二 熱化學氣相沉積二氧化矽」跟「第三熱化學氣相沉積二氧化 矽」之間、所述「第三熱化學氣相沉積二氧化政」跟「第四 熱化學氣相沉積二氧化矽」之間會形成空腔（cavity) ’使所 述「交替複層結構」表面具有雛紋（com^atedsurface)。 接著，沈積一層第二複晶矽’然後’利用電槳蝕刻技術 對所述「第二複晶矽」進行垂直單向性的回蝕刻’以去除所 述「第四熱化學氣相沉積二氧化砂」上方之所述「第二複晶 砂」和「第二介電層」上方之所述「第二複晶政」和「第一 複晶矽」’以在所述「交替複層結構」的旁側形成「第二複 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I ： ------^------1τ--------旅 (請先閱讀背面之注意事項再$寫本頁) 經濟部中央橾準局員工消费合作杜印装 A7 __B7_ 五、發明説明（+ ) 晶砂側壁物」（second polysilicon spacer )。 接著，去除表面具有皺紋之所述「交替複層結構」’以 形成由所述「第一複晶矽」和「第二複晶矽側壁物」構成之 電容器的下層電極（storagenode) ’由於所述「交替複層結 構」表面具有皴紋，故所述「第二複晶矽側壁物」之內側表 面也具有皴紋，故增加了電容器的下層電極之表面積。然 後，沈積電容器介電層和第三複晶矽層，並利用微影技術與 電漿蝕刻技術蝕去所述「第三複晶矽層」和「電容器介電 層」，以形成電容器的上層電極（plateelectrode) ° 4·圖示的簡要說明 圖一到圖十是本發明之實施例的製程剖面示意圖。 5·發明之實施例 此部份將配合圖示說明，圖示部份只畫出一個單元之記 憶元，並省略井區結構，對此發明而言可爲N井區或P井 區’且此製程可延伸到與CMOS製程相結合。 現在請參考圖一。首先，利用標準製程在P型矽半導體 基板10上利用習知的淺凹溝隔離技術（Shallow Trench Isolation ; ST1)或局部矽氧化隔離技術（LOCOS)形成隔離 場效電晶體之氧化層，所述場氧化層厚度介於3000埃到 6000埃之間，然後，再形成場效電晶體與字語線’所述場效 電晶體包含有閘氧化層（Sate oxide )、閘極（gate electrode)與源極 12/汲極 12 (source/drain)，請注意， 爲方便說明，圖一僅顯示源極12 ’而所述氧化層、閘氧化 層、閘極、汲極與字語線均未顯示於圖示。 所述閘氧化層是熱氧化「P型矽半導體基板2」而成，其 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐了 —-：----..----裝------訂------泉 (請先閱讀背面之注意事項再填寫本頁) A7 B7 經濟部中央標準局員工消費合作社印装 五、發明説明（ί:) 厚度介於80到200埃之間。所述閘極則是由低壓化學氣相沉 積法（LPCVD)形成之複晶砂或複晶砂化物（Polycide)所 構成，其厚度介於2000到3500埃之間。所述「源極12/汲 極12」則是利用砷離子（As75)進行離子佈値來形成，其離 子佈値劑量介於2E15到5E16原子/平方公分之間，離子佈値 能量則介於30到80 kev之間。 請再參考圖一。完成場效電晶體的製造後，接著，沈積 第一介電層14和第二介電層16，並利用微影技術與電獎触 刻技術蝕去所述第一介電層14和第二介電層16以露出所述 場效電晶體之源極12，以形成場效電晶體之記憶元接觸窗17 (cellcontact)，如圖一所示。未來，電容器的下層電極將透 過所述「記憶元接觸窗Π」跟所述場效電晶體之源極12作 電性接觸。 所述「第一介電層14」通常是利用大氣壓化學氣相沉積 法（APCVD)形成之硼磷攙雜玻璃膜（BPSG)，其反應壓 力爲1.0 torr，反應溫度大約400 °C，反應氣體是 Si(C2H50)4、TMB與N2組成之混合氣體，其厚度介於3000 到8000埃之間，並利用熱流整（Thermal Flow)或回蝕刻 (Etchback)或化學機械式琢磨技術（Chemical Mechanical Polishing ; CMP)平坦化所述「第一介電層14」。所述「第 二介電層16」貝嗵常是利用低壓化學氣相沉積法形成之無攙 雜的二氧化砂，其反應氣體是Si(C2H50)4、N20和02組成之 混合氣體，其反應溫度大約720 °C，反應壓力大約0.25 torr，其厚度介於500到1500埃之間。對所述第一介電層14 和第二介電層16之電漿蝕刻，可以利用磁場增強式活性離 ^ -----^ — (請先閱讀背面之注意事項再v寫本頁) 訂 本紙張尺度適用中國國家標準（0阳）戍4規格（21(^297公|) 經濟部中央樣準局貝工消费合作社印製 A7 B7 五、發明説明（1?) 子式電獎餓刻技術（MERIE)或電子迴旋共振電漿蝕刻技術 (ECR)或傳統的活性離子式電漿蝕刻技術（RE)予以完 成，其反應氣體通常是CF4、CHF3和Ar。 現在請參考圖二。接著，形成一層第一複晶矽18，所述 「第一複晶矽18」塡滿所述「記憶元接觸窗17」’如圖二所 示。所述「第一複晶砂18」通常是利用同步碟攙雜（h-situ phophorus doped )之低壓化學氣相沉積法形成’其反應热體 是（15%PH3/85%SiH4)與（5%PH3/95%N2)的混合氣體， 反應溫度大約550°C，其厚度介於1〇〇〇到4000埃之間，視 所述「記憶元接觸窗17」之尺寸而定。 現在請參考圓三。接著，形成一層氮化矽2〇，然後’利 用熱化學氣相沉積法（Thermal Chemical Vapor Deposition ) 形成一層第一熱化學氣相沉積二氧化矽22 ( First Thermal CVD Oxide )，再利用電漿增強式化學氣相沉積法 (PECVD)形成一層第一電漿二氧化矽24 (FirstPE-Qxide) ， 接著 ，連續形成 一層第二熱化學氣相沉積二氧化矽 26、第二電漿二氧化矽28、第三熱化學氣相沉積二氧化矽 30、第三電漿二氧化矽32和第四熱化學氣相沉積二氧化矽 34，以形成由「熱化學氣相沉積二氧化矽」由「電漿二氧化 砂」組成之交替複層結構（altematiinglayers)，如圖三所 示。 所述氮化矽20是利用低壓化學氣相沉積法形成，其反應 氣體是SiH2Cl2和ΝΉ3，其反應溫度約720 °C，反應壓力介 於0.2到0.4 torr之間，其厚度介於500到1500埃之間。所 述「熱化學氣相沉積二氧化矽」是利用低壓化學氣相沉積法 I-------¾------訂！-----^ (請先閲讀背面之注意事項再本頁) 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐} 經濟部中央樣準局員工消费合作社印裂 A7 __B7_ 五、發明説明（7 ) 形成，其反應氣體是SiH2Cl2和N20或是SiH4和02，其反應 溫度則介於750到900 °C之間。所述「電漿二氧化矽」是利' 用電漿增強式化學氣相沉積法形成’其反應氣體是SiH4和 〇2，反應溫度介於300到400 °C之間。所述「第一熱化學氣 相沉積二氧化矽22」、「第一電漿二氧化矽24」、「第二熱 化學氣相沉積二氧化矽26」、「第二電漿二氧化矽28」、 「第三熱化學氣相沉積二氧化矽3〇」、「第三電漿二氧化矽 32」和「第四熱化學氣相沉積二氧化矽34」各層的厚度介於 200到400埃之間。另外，除了利用低壓化學氣相沉積法以 外，也可以利用大氣壓化學氣相沉積法（APCVD)或是次大 氣壓化學氣相沉積法（Sub-Atomsphere Chemical Vapor Deposition ; SACVD )等各種化學氣相沉積法形成所述「熱 化學氣相沉積二氧化矽」。 請注意，在氫氟酸溶液中，所述「電漿二氧化矽」對 「熱化學氣相沉積二氧化矽」之蝕刻選擇比（etch selectivity )大約是4比1，也就是說，所述「電獎一氧化 矽」蝕刻率比所述「熱化學氣相沉積二氧化矽」快。通常’ 藉著調整電漿沉積反應室之電極間隔、反應壓力和射頻功 率，吾人可以改變所述「電漿二氧化砂」薄膜之特性’進而 改變其在氫氟酸溶液內之蝕刻率。 現在請參考圖四與圖五。接著，利用微影技術和電獎鈾 亥fJ技術餓去電容器區域（capacitorregion)以外之所述「交替 複層結構」，所述電漿蝕刻終止於所述氮化矽20表面，如圖 四所示。然後，利用氫氟酸溶液側向的蝕去（lateraletch) — 部份的所述「交替複層結構」，由於所述「電漿二氧化矽」 II----^----裝------訂—-----康 (請先閲讀背面之注意事項再灰寫本頁) 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） 經濟部中央標準局貝工消費合作社印装 Μ ________Β7 五、大表所述「熱化學氣相沉積二氧化矽」，因此， 在所述「第一熱化學氣相沉積二氧化矽22」跟「第二熱化學 氣相沉積二氧化矽26」之間、所述「第二熱化學氣相沉積二， 氧化矽26」跟「第三熱化學氣相沉積二氧化砂30」之間、所 述「第三熱化學氣相沉積二氧化矽30」跟「第四熱化學氣相 沉積二氧化矽34」之間會形成空腔35 ( cavity )，使所述 「父替複層結構」表面具有雛紋（corrugatedsurface)，如圖 五所示。對所述「交替複層結構」之電漿蝕刻，也是利用磁 場增強式活性離子式電漿蝕刻技術，其反應氣體也是CF4、 CHF3和Ar的混合氣體。 現在請參考圖六與圖七。接著，沈積一層第二複晶矽 36 ’如圖六所示。然後，電獎飽刻技術對所述「第二複 晶矽36」進行垂直單向性的回蝕刻，以去除所述「第四熱化 學氣相沉積二氧化矽34」上方之所述「第二複晶矽36」和 「第二介電層16」上方之所述「第二複晶矽36」和「第一複 晶矽18」’以在所述「交替複層結構」的旁側形成「第二複 晶砍側壁物36A」（second polysilicon spacer )，如圖七所 示。所述「第二複晶矽36」之形成方式跟「第一複晶矽18」 相同，其厚度介於1000到2500埃之間。對所述「第二複晶 矽36」之垂直單向性的回蝕刻，可以利用前述之磁場增強式 活性離子式電漿蝕刻技術或電子迴旋共振電漿蝕刻技術或傳 統的活性離子式電漿蝕刻技術，而在次微米積體電路技術領 域，通常是利用「磁場增強式活性離子式電漿蝕刻技術」， 且其電漿反應氣體通常是Cl2、SF6和HBr的混合氣體。 現在請參考圖八與圖九。接著，利用氫氟酸溶液（HF) — "I----------裝------訂 ir-----缞 (請先閲讀背面之注意事項再^^本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消费合作社印«. A7 ____B7 五、發明説明（1 ) 蝕刻去除表面具有皺紋之所述「交替複層結構」，所述蝕刻 終止於所述氮化矽20之表面，以形成由所述「第一複晶砂 18」和「第二複晶矽側壁物36A」構成之電容器的下層電極 (storage node )，由於所述「交替複層結構」表面具有駿 紋，故所述「第二複晶矽側壁物36A」之內側表面也具有雛 紋，如圖八所示，故增加了電容器的下層電極之表面積。完 成電容器的下層電極後，接著，利用標準製程形成「電容器 介電層38」，如圖九所示。 現在請參考圖十。接著，形成一層「第三複晶矽40」， 並利用微影技術與電漿蝕刻技術蝕去所述「電容器介電層 38」和「第三複晶矽40」，以形成電容器的上層電極（plate electrode)，如圖十所示，一種具有高電容之堆疊式電容器 和高集積密度之堆疊式動態隨機存取記憶體於焉完成。 所述「電容器介電層38」通常是由氮化矽（Nitride ; N)和氧化氮化砍（Oxynitride ; 0 )所組成。所述氮化砂是 以低壓化學氣相沉積法形成，其厚度介於40埃到60埃之 間；所述氧化氮化矽是氧化所述氮化矽而成，其厚度介於20 埃到50埃之間。所述「第三複晶矽40」之形成方式跟「第 一複晶矽18」相同，其厚度介於1000到2000埃之間。另 外’所述「電容器介電層38」亦可由五氧二鉅材料組成 (Τ〇2〇5)。 I-M --------裝------訂丨----涑 (請先閲讀背面之注意事項再矿.%本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐）Central sample of the Ministry of Economic Affairs, printed by employee consumer cooperatives A7 _B7__ V. Description of Invention (/) 1. Field of Invention The present invention relates to a method for manufacturing a dynamic random access memory of integrated circuits. 2. Background of the Invention A typical stacked dynamic random access memory is to manufacture a metal-oxide-semiconductor field-effect transistor (MOSFET) and a capacitor on a silicon semiconductor substrate, and use the source of the field-effect transistor to connect A storage node of a capacitor forms a memory cell of a dynamic random access memory, and a large number of memory cells are aggregated into a memory volume circuit. In recent years, the packing density of dynamic random access memory has increased rapidly. At present, it has entered mass production of 64 million bits with a memory cell size of 1.5 square micrometers (um2). Japanese semiconductor company NEC is even more In 1995, it was announced that a prototype of a billion-bit dynamic random access memory (1GB DRAM) had come out (Prototype). On the other hand, some integrated circuit companies in the Hsinchu Science-Based Industrial Park in China have also entered the mass production of 4.6 million bits of dynamic random access memory, one of the design guidelines of 0.4 to 0.45 microns. Phase, for example, Mosel_Vitelic and TI-Acer. To achieve the purpose of highly accumulating the dynamic random access memory, the size of the memory cells must be reduced, that is, the size of the field effect transistor and the capacitor must be reduced. However, the reduction in the size of the capacitor will reduce the capacitance 使得, making the memory circuit The signal / noise (Signal Noise; S / N) ratio decreases, causing shortcomings such as misjudgment or instability of the circuit. In order to maintain or increase the size of the capacitor when reducing and reducing the size of the capacitor, the Chinese National Standard (CMS) A4 specification (210X297 mm) is applicable. 1 ^ ~~ ---------------------- Order -; ---- points (please read the notes on the back first. ^ Write this page) A7 ______B7 printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (2) Capacitor 値, Fujitsu from Japan The fin structure disclosed by Masao Taguchi et al. Of Fujitsu in U.S. Patent No. 5,021,357 is the most representative. In addition, H. Watanabe et al. Also disclosed a novel capacitor structure in EEDM 1992. . 3. Brief Description of the Invention The main object of the present invention is to provide a manufacturing method for a stacked capacitor (StackCapacitor) having a high capacitance. Another object of the present invention is to provide a method for manufacturing a stacked dynamic random access memory with a high accumulation density. The main process method of the present invention is as follows. First, an oxide layer of an isolated field effect transistor is formed on a silicon semiconductor substrate (Silicon Semiconductor Substrate) using a conventional shallow trench isolation technology (STI) or a local sand oxidation isolation technology. Then, a standard process is used to form a field effect transistor and a word line. The field effect transistor includes a gate oxide, a gate electrode, and a source / drain. ° Then , Depositing a first dielectric layer and a second dielectric layer, and planarizing the first dielectric layer using a conventional chemical mechanical polishing technology (CMP), and then using lithography technology and plasma The etching technique removes the first dielectric layer and the second dielectric layer to expose the source of the field effect transistor to form a cell contact of the field effect transistor. Next, a layer of first polycrystalline sand is formed, and the "first polycrystalline sand" is filled with the "memory cell contact window". In the future, the "first polycrystalline silicon" will be in electrical contact with the source of the field effect transistor through the "memory cell contact window". Then 'form a layer of silicon nitride, and then use the thermal chemical vapor deposition method (please read the precautions on the back before continuing on this page). Install. The size of the paper is applicable to China National Standards (CNS > A4 specifications ( 210X297 mm) A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (3) (Thermal Chemical Vapor Deposition) to form a layer of first thermal CVD oxide sand (First Thermal CVD Oxide), and then A layer of First PE-Oxide was formed using the Plasma Enhanced Chemical Vapor Deposition (PECVD) method, and then a second layer of thermal chemical vapor deposition silicon dioxide was continuously formed , The second plasma sand, the third thermochemical vapor deposition silicon dioxide, the third plasma silicon dioxide and the fourth thermochemical vapor deposition silicon dioxide to form the "thermochemical vapor deposition dioxide" Alternating layers composed of "silicon dioxide" silicon "° Then, the capacitor area (capacitorregi) is etched away using lithography and plasma etching technology On the other than the "alternative multi-layer structure", the electric paddle etching (I ends on the silicon nitride surface. Then, using a hydrofluoric acid solution for lateral etch-part of The "parent replacement multi-layer structure" 'because the etching rate of the "plasma silicon dioxide" is much larger than that of the "thermochemical vapor deposition silicon dioxide", Between "deposited silicon dioxide" and "second thermal chemical vapor deposition sand", between said "second thermal chemical vapor deposited silicon dioxide" and "third thermal chemical vapor deposited silicon dioxide" 2. A cavity will be formed between the "third thermal chemical vapor deposition dioxide" and the "fourth thermal chemical vapor deposition silicon dioxide", so that the surface of the "alternating multilayer structure" has a cavity. Com ^ ated surface. Next, a layer of second polycrystalline silicon is deposited, and then the "second polycrystalline silicon" is subjected to vertical unidirectional etchback using an electric paddle etching technique to remove the "fourth "Second Polycrystalline Sand" and "Thermochemical Vapor Deposition Sand" The "second dielectric layer" and "first polycrystalline silicon" above the "dielectric layer" are formed beside the "alternative multilayer structure" to form a "second replica paper size applicable to Chinese national standards ( CNS) A4 specification (210X297 mm) I: ------ ^ ------ 1τ -------- Travel (please read the precautions on the back before writing this page) The consumer cooperation of the Central Provincial Bureau of Standards, Du Duanzhuang A7 __B7_ V. Description of the invention (+) second polysilicon spacer. Next, the "alternating multi-layered structure" with wrinkles on its surface is removed to form a lower layer electrode (storagenode) of the capacitor composed of the "first poly-silicon" and "second poly-silicon side wall" The surface of the "alternative multi-layer structure" has ridges, so the inner surface of the "second polycrystalline silicon sidewall" also has ridges, which increases the surface area of the lower electrode of the capacitor. Then, a capacitor dielectric layer and a third polycrystalline silicon layer are deposited, and the "third polycrystalline silicon layer" and the "capacitor dielectric layer" are etched away using lithography technology and plasma etching technology to form an upper layer of the capacitor. Electrode (plateelectrode) ° 4. Brief description of the drawings Figures 1 to 10 are schematic cross-sectional views of the manufacturing process according to the embodiment of the present invention. 5. Example of the invention This section will be illustrated with illustrations. The illustrated section only draws the memory elements of a unit, and the well area structure is omitted. For this invention, it can be N well area or P well area. This process can be extended to be combined with the CMOS process. Please refer to Figure 1. First, an oxide layer of an isolated field effect transistor is formed on a P-type silicon semiconductor substrate 10 by using a conventional process using a conventional shallow trench isolation technology (Shallow Trench Isolation; ST1) or a local silicon oxide isolation technology (LOCOS). The thickness of the field oxide layer is between 3000 angstroms and 6000 angstroms, and then a field effect transistor and a word line are formed. The field effect transistor includes a gate oxide layer, a gate electrode, and a gate electrode. Source 12 / drain 12 (please note that for the convenience of illustration, Figure 1 only shows source 12 'and the oxide layer, gate oxide layer, gate electrode, drain electrode and word line are not shown)于 图。 In the icon. The gate oxide layer is formed by thermally oxidizing the "P-type silicon semiconductor substrate 2", and the paper size of the gate oxide layer is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm —-: ----..---- Packing ------ Order ------ Quan (Please read the notes on the back before filling out this page) A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (ί :) Between 80 and 200 angstroms. The gate is composed of polycrystalline sand or polycide formed by low pressure chemical vapor deposition (LPCVD), and its thickness is between 2000 and 3500 angstroms The "source 12 / drain 12" is formed by using arsenic ions (As75) for ion cloth, and the ion cloth dose is between 2E15 and 5E16 atoms / cm2, and the energy of the ion cloth is described Between 30 and 80 kev. Please refer to Figure 1 again. After the fabrication of the field effect transistor is completed, the first dielectric layer 14 and the second dielectric layer 16 are then deposited, and the lithography technique and the electric award are used for the etching. Technology etches away the first dielectric layer 14 and the second dielectric layer 16 to expose the source 12 of the field effect transistor to form a memory of the field effect transistor. The contact window 17 (cellcontact) is shown in Fig. 1. In the future, the lower electrode of the capacitor will make electrical contact with the source 12 of the field effect transistor through the "memory cell contact window Π". A dielectric layer 14 "is usually a boron-phosphorus doped glass film (BPSG) formed by atmospheric pressure chemical vapor deposition (APCVD). The reaction pressure is 1.0 torr, the reaction temperature is about 400 ° C, and the reaction gas is Si (C2H50). 4. The mixed gas composed of TMB and N2 has a thickness between 3000 and 8000 Angstroms, and is flattened by using Thermal Flow or Etchback or Chemical Mechanical Polishing (CMP). The “first dielectric layer 14” and the “second dielectric layer 16” are often non-doped sand dioxide formed by a low pressure chemical vapor deposition method, and the reaction gas is Si (C2H50) 4. A mixed gas consisting of N2, N20 and 02 has a reaction temperature of about 720 ° C, a reaction pressure of about 0.25 torr, and a thickness between 500 and 1500 angstroms. For the first dielectric layer 14 and the second dielectric layer 16 Plasma etching, magnetic field enhanced activity From ^ ----- ^ — (Please read the notes on the back before v write this page) The size of the paper used in this edition applies to the Chinese national standard (0yang) 戍 4 (21 (^ 297 公 |) Central Ministry of Economics Printed by the Zhuhai Bureau Pui Gong Consumer Cooperative A7 B7 V. Description of the invention (1?) Sub-electron award engraving technology (MERIE) or electron cyclotron resonance plasma etching technology (ECR) or traditional reactive ion plasma etching technology ( RE). The reaction gases are usually CF4, CHF3 and Ar. Please refer to Figure 2 now. Then, a layer of first polycrystalline silicon 18 is formed, and the "first polycrystalline silicon 18" is filled with the "memory cell contact window 17" 'as shown in FIG. The "first polycrystalline sand 18" is usually formed by a low pressure chemical vapor deposition method using h-situ phophorus doped. Its reaction heat is (15% PH3 / 85% SiH4) and (5% PH3 / 95% N2) mixed gas, the reaction temperature is about 550 ° C, and its thickness is between 1000 and 4000 angstroms, depending on the size of the "memory cell contact window 17". Please refer to circle three now. Next, a layer of silicon nitride 20 is formed, and then a layer of First Thermal CVD Oxide 22 is formed using Thermal Chemical Vapor Deposition, and then enhanced by a plasma. A first chemical vapor deposition (PECVD) method is used to form a layer of first plasma silicon dioxide 24 (FirstPE-Qxide), and then a second layer of thermal chemical vapor deposition silicon dioxide 26 and second plasma silicon dioxide 28 are formed continuously. , The third thermochemical vapor deposition silicon dioxide 30, the third plasma silicon dioxide 32, and the fourth thermochemical vapor deposition silicon dioxide 34 to form a "thermochemical vapor deposition silicon dioxide" Alternate layering structures composed of "slurry sand" are shown in Figure 3. The silicon nitride 20 is formed by using a low-pressure chemical vapor deposition method. The reaction gases are SiH2Cl2 and ΝΉ3. The reaction temperature is about 720 ° C, the reaction pressure is between 0.2 and 0.4 torr, and the thickness is between 500 and 1500. Between Egypt. The "Thermochemical Vapor Deposition Silicon Dioxide" is made by the low pressure chemical vapor deposition method I ------- ¾ ------ Order! ----- ^ (Please read the precautions on the back before this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). The Central Consumers' Bureau of the Ministry of Economic Affairs's Consumer Cooperatives printed A7 __B7_ V. Description of the invention (7) Formation, the reaction gas is SiH2Cl2 and N20 or SiH4 and 02, and the reaction temperature is between 750 and 900 ° C. The "plasma silicon dioxide" is used to enhance the plasma The chemical vapor deposition method is used to form 'the reaction gas is SiH4 and 〇2, and the reaction temperature is between 300 and 400 ° C. The "first thermochemical vapor deposition silicon dioxide 22", "the first plasma "Silicon dioxide 24", "Second thermochemical vapor deposition silicon dioxide 26", "Second plasma silicon dioxide 28", "Third thermal chemical vapor deposition silicon dioxide 30", "Third electrical The thickness of each layer of the “Silicon Dioxide 32” and “Fourth Thermal Chemical Vapor Deposition Silicon Dioxide 34” is between 200 and 400 angstroms. In addition to the low-pressure chemical vapor deposition method, atmospheric pressure chemical gas can also be used Phase Deposition (APCVD) or Sub-Atomsphe re Chemical Vapor Deposition; SACVD) and other chemical vapor deposition methods to form the "thermochemical vapor deposition silicon dioxide". Please note that in a hydrofluoric acid solution, the "plasma silicon dioxide" The etch selectivity of "Chemical Vapor Deposition Silicon Dioxide" is about 4 to 1. That is, the etching rate of "Electric Award Silicon Oxide" is higher than that of "Thermochemical Vapor Deposition Silicon Dioxide" Quickly. 'Usually, by adjusting the electrode interval, reaction pressure and RF power of the plasma deposition reaction chamber, we can change the characteristics of the "plasma sand dioxide" film' to change its etching rate in the hydrofluoric acid solution. Please refer to FIG. 4 and FIG. 5. Then, using the lithography technology and the electric award uranium fJ technology to remove the "alternative multi-layer structure" outside the capacitor region, the plasma etching ends at the The surface of the silicon nitride 20 is shown in Fig. 4. Then, a portion of the "alternating multi-layer structure" is etched laterally using a hydrofluoric acid solution, because of the "plasma silicon dioxide" II ---- ^- --- Installation ------ Order ------- Kang (Please read the notes on the back before graying out this page) This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) Printed by the Ministry of Economic Affairs, Central Standards Bureau, Shellfish Consumer Cooperatives. ________B7 5. The "thermochemical vapor deposition silicon dioxide" described in the big table, therefore, the "first thermochemical vapor deposition silicon dioxide 22" and " Between the second thermal chemical vapor deposition silicon dioxide 26 ", between the" second thermal chemical vapor deposition silicon II, silicon oxide 26 "and" the third thermal chemical vapor deposition silicon dioxide 30 ", A cavity 35 will be formed between the "third thermal chemical vapor deposition silicon dioxide 30" and the "fourth thermal chemical vapor deposition silicon dioxide 34", so that the surface of the "parent replacement multilayer structure" has Corrugated surface, as shown in Figure 5. The plasma etching of the "alternative multi-layer structure" also uses a magnetic field enhanced active ion plasma etching technique, and the reaction gas is also a mixed gas of CF4, CHF3 and Ar. Please refer to Figure 6 and Figure 7. Next, a layer of second polycrystalline silicon 36 'is deposited as shown in FIG. Then, the electro-saturation etching technology performs a vertical unidirectional etch-back on the "second polycrystalline silicon 36" to remove the "first" on the "fourth thermal chemical vapor deposition silicon dioxide 34". The “secondary polycrystalline silicon 36” and the “second dielectric layer 16” above the “secondary polycrystalline silicon 36” and the “first polycrystalline silicon 18” are placed beside the “alternating multilayer structure” A “second polysilicon spacer 36A” is formed, as shown in FIG. 7. The formation method of the "second polycrystalline silicon 36" is the same as that of the "first polycrystalline silicon 18", and its thickness is between 1000 and 2500 Angstroms. For the vertical unidirectional etchback of the “second polycrystalline silicon 36”, the aforementioned magnetic field enhanced active ion plasma etching technology or electron cyclotron resonance plasma etching technology or traditional active ion plasma can be used. Etching technology. In the field of sub-micron integrated circuit technology, "magnetic field enhanced active ion plasma etching technology" is usually used, and the plasma reaction gas is usually a mixture of Cl2, SF6 and HBr. Please refer to Figure 8 and Figure 9. Next, use the hydrofluoric acid solution (HF) — " I ---------- install -------- order ir ----- 缞 (Please read the precautions on the back before ^^ (This page) This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs «. A7 ____B7 V. Description of the invention (1) The surface with wrinkles is removed by etching "Multilayer structure", the etching is terminated on the surface of the silicon nitride 20 to form the lower electrode of the capacitor composed of the "first polycrystalline sand 18" and "second polycrystalline silicon sidewall 36A" ( storage node), because the surface of the "alternative multi-layer structure" has grains, the inner surface of the "second polycrystalline silicon sidewall 36A" also has embossing, as shown in Figure 8, so the capacitor's Surface area of the lower electrode. After completing the lower electrode of the capacitor, the "capacitor dielectric layer 38" is then formed using a standard process, as shown in Figure IX. Please refer to Figure X now. Next, a layer of "third polycrystalline silicon 40" is formed, and the "capacitor dielectric layer 38" and "third polycrystalline silicon 40" are etched away using lithography technology and plasma etching technology to form an upper electrode of the capacitor (Plate electrode), as shown in FIG. 10, a stacked capacitor with a high capacitance and a stacked dynamic random access memory with a high accumulation density are completed in 焉. The "capacitor dielectric layer 38" is generally composed of silicon nitride (Nitride; N) and oxynitride (Oxynitride; 0). The nitrided sand is formed by a low-pressure chemical vapor deposition method and has a thickness between 40 angstroms and 60 angstroms. The silicon nitride oxide is formed by oxidizing the silicon nitride and has a thickness between 20 angstroms and 60 angstroms. Between 50 Angstroms. The formation method of the "third polycrystalline silicon 40" is the same as that of the "first polycrystalline silicon 18", and its thickness is between 1000 and 2000 Angstroms. In addition, the "capacitor dielectric layer 38" may be composed of a pentoxide material (TO205). IM -------- install ------ order 丨 ---- 涑 (Please read the precautions on the back before re-mineralizing.% Page) This paper size applies to China National Standard (CNS) Α4 specifications (210X297 mm)