TW411549B - A method for shrinking memory cell size - Google Patents

Abstract

The invention relates to a manufacturing method for stack dynamic random access memory (Stack DRAM). The well-known chemical mechanical polishing (CMP) technique and photoresist erosion are employed. The production processes of depositing polysilicon and dielectric layers followed by etchback are carried out. The charge-storage node of a capacitor has trenches on the surface, making a substantial reduction of the planar circuit layout area possible without reducing capacitance of the memory cell. Therefore, the stacking density of memory cells can be increased and eventually result in a super high density Stack DRAM.

Description

411549 at B7 Five 'invention description () Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative, 1. Technical Field of the Invention The present invention relates to stacked-type dynamic random access memory chip stack capacitors of integrated circuits ( Stack DRAM) Manufacturing Method β 2 · BACKGROUND OF THE INVENTION A typical r-stacked dynamic random access memory cell is a memory cell manufactured on a silicon semiconductor wafer (Silicon Semiconductor Wafer). A crystal (Metal Oxide Semiconductor Field Effect Transistor; MO $ FET) and a stacked capacitor (Stack Capacitor), and the source of the metal-oxygen half field effect transistor is used to connect the charge storage electrode (Storage) of the stacked capacitor Node) to form a dynamic random access memory of 100 million yuan (MemoiyCdl). Then, aggregate a large number of hundred million yuan to become a cell array. On the other hand, near the hundred million yuan array, There are other circuits around, such as the sense amplifier (Sense Amplifier) and other circuits, these external circuits are called peripheral circuit area (Peripheral Circuit). In recent years, the dynamic random access memory density of Onbitgrated Density has increased sharply, and now it has entered a cell size of approximately 1.5 square micrometers (um2), which is six to four million. Take note of mass production (64MBit) 'NEC Semiconductor Corporation of Japan announced in 1995 that a billion-bit dynamic random access memory prototype prototype was available (1GB DRAM Prototype). Science and Industrial Park] (Science Based Industrial Park; SIPA) 'The major integrated companies have also entered the mass production of 6 million digits of dynamic random access memory, which is one of the set guidelines 0-35-0.5 microns. For example, Taiwan Semiconductor Manufacturing Corporation (TSMC) and World Advanced Semiconductor Circuit Corporation (Vanguard InteraatioDal Semiconductor Coiporaticm; VISC) stacked dynamic random access memory billion, TI-Acer In order to achieve the purpose of dynamic random access to record the high accumulation density of 100 million yuan, it must be reduced Recording the size of the cell (Cell Size), however, the size of the internal scale of the watch is reduced and the capacitance is low. • The signal / noise (Signal Noise; S / N) ratio of the record is reduced. Disadvantages such as instability • Therefore, in order to achieve a high accumulation density of dynamic random access memory, it is necessary to find a more sickle process technology to reduce the Plannar Layout Area, which is worth hundreds of millions of dollars. Maintain or increase the capacitance of the capacitor. In order to increase the accumulation density, the traditional dynamic random access memory system is to form a capacitor (Three Dimension Capacitor) in the third degree space above or below the field effect transistor to limit the circuit size. Increase the capacitance of the capacitor within the layout area; the capacitor formed above the field effect transistor is called a stacked capacitor (Stacked Capacitor) · The capacitor formed below the field effect transistor is called a trenched capacitor (Trenched Capacitor)- The traditional way to increase the capacitance of a stacked capacitor is to increase the thickness of the electrode number below the capacitor to increase the surface area of the capacitor. As shown in Figure 1, in order to reduce the plane area (P 丨 annar Area) of 100 million yuan, while maintaining the same capacitance 値, however, when the size of 100 million yuan continues to shrink, 'only by increasing the electrode layer below the capacitor It is not practical to increase the thickness of the capacitor by 1 —- III-— ^ 1 III —- " Threading (¾Notes for reading first and back ¾Notes ¾ then fill out this page] _ This paper "J? · Degree Applicable S National Standard (CNS) A4 grid ^ T210: X297 mm) 411549 5. Invention Description () It is necessary to seek more sophisticated process technology to achieve this goal, for example, T. Kaga of Hitachi Corporation in Japan in 1994 IEDM A paper entitled [A 0.29 um2 ΜΙΜ-CROWN Cell and process Technology for 1-Gigabit DRAMs] was also published on page 927, revealing an advanced capacitor structure called [MIM-CROWN]. These stacked capacitor structures Can greatly increase the capacitance of the capacitor 値. The invention discloses a novel method for manufacturing a stacked capacitor, which can greatly reduce the planar circuit layout area of the capacitor and increase the capacitance of the capacitor at the same time. Therefore, it is applied to the scale of a super-high-density stacked dynamic random access memory . 3. Brief Description of the Invention The main object of the present invention is to provide a method for manufacturing a stacked capacitor (Stacked Capacitor) with high capacitance. Another object of the present invention is to provide a super-high packing density (PackingDensity) stacked dynamic random state memory access method. 1 The main enzyme method of the present invention is as follows. 1 1 First, a field oxide layer required for isolating an active area is formed on a semiconductor wafer (Silicon Semiconductor Wafer) using a conventional standard process. Then, in the [electricity | Active area] [metal oxide half field ^ «crystal] and word line CW—) The metal oxide half body includes gate oxide layer (GateOxide), gate electrode (GateElectrode), side wall (Spacer) and source |

Source / Drain «I

I Next, deposit a layer of [First Dielectric] and [Second Dielectric], and describe [Second Medium®], and then use Lithography to online the capacitor area ( Capacitor Region) PhotoresistPattern of source contact window, 1

Then use Plasma Etching to remove the I that is not covered by the [Photoresist Pattern] I

[Jth electrical layer] and [second dielectric layer] • to form a source contact window for metal-oxygen half field effect transistors (age I printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs nnn -nn 1 n II n · ( (Please read the notes on the back before filling in this page)

Contact). In the future, the storage node of the capacitor will make electrical contact with the source of the metal-oxide half field effect transistor through the [Source contact I window]-1

Next, a layer of [Doped Polysilicon] (First Doped Polysilicon) and

[Third Dielectric], and the [doped first polycrystalline silicon layer] is filled with the [source electrode I

Touch the window]. Then, a photoresist I pattern is formed directly above the [third dielectric layer] in the capacitor region by using the lithography technology, and then a part of the photoresist Erosion technology is used to laterally saturate a part of the solution. Description [Light 1

Resistance pattern], so that the size of the [photoresist pattern] is smaller than the [source contact window]. Then, using electricity I

Rong-Feng Engraving Technology AnisotropicaUy Etched the I that is not covered by the [Photoresistance Case] I

[Third Dielectric Layer] to form [ThirdDidectricPillar], the electric hair is engraved I

Terminated in the [doped first polycrystalline silicon layer]. I The size of this paper is near China National Standards (CNS) A4 scale (2 丨 0 X 297 Gongchu) Economic order Shenyang Municipal Bureau of Automobile Industry Co., Ltd. Printed by the Bayer Consumer Cooperative 411549 A7 B7 5. Description of the invention () Remove the description [Photoresist pattern] Afterwards, a layer of [Second Doped Polysilicon] (Second Doped Polysilicon) is deposited, and then the [Doped Second Polysilicon layer] is performed using electro-violet touch engraving technology Unidirectional etch-back] (AnisotmpicaUyEtchback), the [unidirectional etch-back] etched away the [doped second polycrystalline silicon layer] and [ The first doped polysilicon layer], that is, the "unidirectional etch-back" ends on the surface of the "second dielectric layer" so as to A second polysilicon spacer (Second Polysilicon Spacer) is formed on the side surface. Next, the [third dielectric layer thin column] is removed by using a hydrofluoric acid chemical solution or an electro-etching technique, so that the remaining [doped first polycrystalline silicon layer] and [second polycrystalline silicon layer] are left. Side wall] constitutes a capacitor charge electrode (Storage Node) of the capacitor. The surface of the [charge storage electrode] is formed with a groove, and the [source contact window] is used as an axis. Therefore, the planar circuit of the capacitor is greatly reduced. In the case of the layout area, the capacitance of the capacitor can be increased at the same time. That is, the capacitance of the capacitor can be increased at a high accumulation density. Next, a very thin Capacitor dielectric and a doped third polycrystalline silicon layer are deposited on the surface of the [charge storage electrode], and then lithography and etching techniques are used to remove the [ The capacitor dielectric layer] and the [doped third polycrystalline silicon layer] are used to form a capacitor's top plate. A stacked dynamic random access capacitor with ultra-high capacitance is recorded in a single body. 4. Brief description of the diagram FIG. 1 is a process cross-sectional schematic diagram of a prior art of the stacked dynamic random access memory (Prior Art); FIG. 2 to FIG. 12 are process cross-section schematic diagrams of an embodiment of the present invention. View) »5. Embodiments of the invention First, a field oxide layer 4 is formed on a P-type sand semiconductor wafer 2 (Silicon Semiconductor Wafer) in a lattice direction (100), and the field oxide layer 12 is usually thermal Oxidation technology (Thermal Oxidation) is formed, and its thickness is between 3000 Angstroms and 5500 Angstroms, which is used to isolate electrical components. Then, the P-type silicon semiconductor wafer 2 is formed on the surface of the lattice direction (100). [Gold Oxygen Half-Effect Transistor] * The metal oxide half field-effect transistor includes a gadolinium oxide layer 6 (Gate Oxide), a gate electrode 8 (Gate Electrode), an insulating layer sidewall 12 (Insulator Spacer), and a source / sink Pole 14 (Source /

Drain), the "source / drain 14" contains an N-lightly doped region (Lightly Doped Region) and an N + heavily doped source / drain, as shown in Figure 2. The gate oxide layer 6 is formed by thermally oxidizing the surface of the [P-type silicon semiconductor wafer 10], and the thickness is between 50 and 200 angstroms. [Alarm 8] is generally composed of Polysilicoii 8 (Low Pressure Chemical Vapor Deposition: LPCVD), and its thickness is between 1000 and 3000 Angstroms. Next, a silicon dioxide 10 (Silicon Dioxide) is formed by a low-pressure chemical vapor deposition method. The silicon dioxide 10 is usually formed by a low-pressure chemical vapor deposition method, and the reaction gas is TetraEthOxySilane. : TEOS: Si (C2H50) 4), N20 and 〇2, the reaction temperature is 720 ° C, and the reaction pressure is between 200 and 300 tnUi- The paper scale is suitable for 0 (CNS) grid (210X297 cm) ) ']! --------- install ----- Ί ---: order ------- line (please read the notes on the back * before filling this page) ______ Μ 济 也Printed by the Central Sample Rate Bureau Shellfish Consumer Cooperative Co., Ltd. 411549 A7 _____B7 V. Description of the invention () ton ·, its thickness is between 500 and 1200 angstroms, and then the lithography and etching technology (Lithography and Etching) axis is used to The [Sand Dioxide 10] and the [Crystalline Sand 8] 'form a gate structure of the [gold-oxygen half field effect transistor]. Then * Ion Implantation is used to form the N-Lightly Doped Region of "Source / Drain 14". Its ion type is disk atom (PM). Between 1E13 and 3E14 atoms / cm² • The ion cloth energy is between 20 and 50 kev, as shown in Figure 2. Next, a layer of [Insulator] is deposited, and the [Insulator layer 12] is etched back unidirectionally to form an [Insulator side wall 12] on the two sides of the [Gate 8] , And the [insulating layer 12] is usually silicon dioxide (Silicon Dioxide) formed by a low-pressure chemical vapor deposition method, and the reaction gas is tetrahexyl silicate (TetraEthOxySilane; TEOS: Si (C2H50) 4), The reaction temperature is 720 ° C, the reaction pressure is between 200 and 300 mili-torr, and the thickness is between 500 and 1500 angstroms. Then, the ion doping technique is used to form a heavily doped region (source dove region) of r source / drain 14_s. The ion species is arsenic (A #), and the ion dosing dose ranges from 1E15 to 3E16. / Cm2, the ion cloth energy is between 30 and 90 kev to complete the fabrication of metal-oxygen half field effect transistors, as shown in Figure 2. Refer now to Figure III. A layer of "first dielectric layer 18j (First Dielectric) and Γ second dielectric layer 20" (Second Dielectric) is deposited, and the second dielectric layer 20 "is planarized, as shown in FIG. The "first dielectric layer 18" is usually a silicon nitride (Silicon Nitride) formed by a low-pressure chemical vapor deposition method. The reaction gas is SiCl2H2 and NH3, and the reaction temperature is between 700 eC and 800 ° C. The reaction pressure is between 200 and 300 milUorr and its thickness is between 500 and 1500 Angstroms. The F second dielectric layer 20 ′ is generally a BoroPhosphoSilicateGlass (BPSG) or a glass film (PhosphoSiiicate Glass; PSG) formed by a chemical vapor deposition method (Chemical Vapor Deposition; CVD). Between 3000 and 10,000 Angstroms. The [flattening] treatment is usually performed by a conventional chemical mechanical polishing (CMP) technique. Next, the photoresist pattern of the source contact window is formed in the capacitor region by lithography technology, and then the Plasma Etching technology is used. The first dielectric layer I8 and the second dielectric layer 20 are covered to form the source contact window 21 (Node Contact) of the metal-oxide half field-effect transistor, as shown in FIG. 4 • Future • The storage node of the capacitor will make electrical contact with the [source / drain M] of the metal-oxide half field effect transistor through the [source contact window 21]. [Plasma Etching] for the [First Dielectric Layer 18] and the [Second Dielectric Layer 20] may be Magnetic Enhanced Reactive Ion Etching (MERIE) or electron cyclotron resonance Electron Cyclotron Resonance (ECR) or traditional Reactive Ion Etching (RIE) technology is used in the field of sub-micron integrated circuits. Etching], the plasma reaction gas is generally CF4, CHF3 and Ar and other gases. This paper ruler 71 is in use ® 囡 家 榇 牟 (CNS) 4 rules _ grid (2 丨 0 father 297 male) I ------- ί .— 装 I L .--- L-- First-order ----- line (please read the precautions on the back before filling in this page) _ 411549 A7 B7 Ministry of Economic Affairs-Central Bureau of Automotive Engineering Cooperate with Du Yinzhuang 5. Description of the invention () Then deposit [Thin First Doped Polysilicon] and [Third Dielectric] [Thin Doped Polysilicon 22] and Fill in the [source contact window 21], as shown in Figure 5. The [thin doped first polycrystalline silicon layer 22] is generally formed by a low-pressure chemical vapor deposition method using synchronous phosphorus atom doping (Phosphorus In-S1tu Doped), and the reaction gas is a mixed gas of PH3 'SiH4 and N2 * The reaction temperature is between 520 and 580 ° C, and its thickness is between 1000 and 4000 Angstroms. The third dielectric layer 24 may be doped silicon dioxide or undoped silicon dioxide formed using an atmospheric pressure chemical vapor deposition (APCVD) method. Dioxide), which can also be a spin-on-glass (SOG) or a spin-on-glass (S0G) with a thickness between Between 3000 and 8000 Angstroms, the purpose is only to provide a step with a high degree * The compactness of the material is not critical. Then, a photoresist pattern 26 is formed in the capacitor region by using a photolithography technology. The [photoresist pattern 26] can use the reverse-tone mask of the [source contact window 21] to Formation, as shown in Figure 6. Then • Use the conventional Photoresist Erosion technology to etch the [Photoresist pattern 26] in an oxygen plasma, and etch away a part of the [Photoresist pattern 26] to become [ Photoresist pattern 26A], so that the size of the photoresist pattern 26A is smaller than the source contact window, as shown in FIG. Generally, the size of the [source contact window 21] is the minimum dimension on the body circuit. It is also the Lithography Resolution Limit of the optical lithography technology. Therefore, the [Photoresist pattern 26A] The size will exceed the analytical limit of optical lithography technology, so it can form an ultra-high memory cell packing density (Packing Density), which is the key of the present invention. Next, the unidirectional etch (Anisotropical Etch) using Dianjun full-etching technology did not show the [Third Dielectric Layer 24] covered by the [Photoresist Pattern 26A] to make it a [Third Dielectric Layer Column 24A] (Tliird Dielectric Pillar), the plasma is etched and terminated at the [thin first crystalline silicon layer 22 of ytterbium], as shown in FIG. 8, after removing the photoresist pattern 26A, As shown in Figure 9. The "unidirectional etching j" of the "third dielectric layer 24" may be magnetic enhanced reactive ion plasma etching (Magnetic Enhanced Reactive Ion Etching: MERIE) or an electron cyclotron resonance electromagnetism (Electron Cyclotron Resonance) ECR) or traditional Reactive Ion Etching (RIE) technology. In the sub-micron technology field, [Magnetic field enhanced reactive ion plasma etching] is usually used. 'The plasma reaction gas is generally CF4, CHF3 and Ar. Now refer to FIG. 10. Next, a layer of [Second Doped Posilicon] is deposited, as shown in FIG. Then, using the plasma etching technology, the [doped second polycrystalline silicon layer 28] is subjected to [unidirectional etch-back], and the [unidirectional etch-back] etches away the [second dielectric Layer 20] The [doped second polycrystalline silicon layer 28] and the [doped first polycrystalline silicon layer 22] on the surface, that is, the [unidirectional etch-back] ends at the [ On the surface of the second dielectric layer 20, a second polycrystalline silicon layer sidewall 28A (Second Pdysilicon Spacer) is formed on the side of the third dielectric layer pillar 24A, as shown in FIG. 11. [Hybrid second polycrystalline silicon layer 28] is usually formed by a low-pressure chemical vapor deposition method using synchronous phosphorus atom doping (Phosphorus In-situ Doped), and the reaction gas is a mixed gas of PH3, SiH4, and N2. The reaction temperature is between 520 and 580 ° C., And its thickness is between 1000 and 3000 Angstroms. For the [doped second polycrystalline silicon layer 28], [unidirectional etchback of the paper, the scale of the paper is suitable for a country's application- (CNS) 8-4 grid (2 丨 0X: 297 mm > L —_________ Install-·, --.-- Order ------ line (锖 «read the note on the back ^ • items and then fill in the page on this page) ___ 411549 A7 B7 V. Description of the invention () Carved] , You can use the F magnetic field enhanced active ion plasma etching j or "electron cyclotron resonance plasma etching" or the traditional "active ion plasma etching technology", in the field of sub-micron integrated circuit, usually using r magnetic field enhancement Plasma reactive ion etching ", the plasma reaction gas is generally CC14, Cl2 and HBr and other halogen gases. Please pay attention to the" the second polycrystalline silicon layer sidewall 28A_ | next to the optical lithography technology Analyze the limit of the [Third Dielectric Layer Column 24A], so that the area of the memory cell can be greatly reduced, and the accumulation density of the billionth body can be greatly increased * to produce ultra-high density dynamic random access memory. Next, using hydrogen fluoride Acid chemical solution or plasma etching technology to remove the [third dielectric layer pillar 24A] ' The doped first polycrystalline silicon layer 22A] and the second polycrystalline silicon layer sidewall 28A constitute a charge storage electrode of the capacitor. The surface of the [charge storage electrode] is formed with grooves, and is formed by the grooves. The t-source contact window 21] is used as the axis, as shown in Fig. 12, so that the capacitor's capacitance can still be increased at the same time when the planar circuit layout area of the capacitor is greatly reduced, that is, at high accumulation density It can increase the capacitance of the capacitor, so that the signal / noise (S / N) ratio of the memory circuit is not reduced, and it will not cause shortcomings such as misjudgment or instability of the circuit. A very thin capacitor dielectric layer (Capacitor Dielectric) and a triple doped polysilicon layer are formed on the surface, and then the lithography and etching technology are used to remove the "capacitor dielectric layer" and the * Doped with a third compound silicon layer j to form the capacitor's top plate, a stacked dynamic random access memory with a very high accumulation density is completed in 焉 * said f The dielectric layer j of the container is usually formed of silicon oxide nitride (Oxynitride), silicon nitride and sand dioxide by the following method. First, thermal oxidation is performed at a temperature between 850 ° C and 950 ° C. The [charge storage electrode] made of polycrystalline silicon * to form [silicon dioxide] with a thickness between 40 angstroms and 200 angstroms: then, at a low pressure at a temperature between 650 ° C and 750 ° C Chemical vapor deposition forms [silicon nitride] with a thickness between 40 angstroms and 60 angstroms; finally, the [nitride nitride] is oxidized at a temperature between 850 ° C and 95 ° C to [Silicon Nitride] with a thickness between 20 and 50 angstroms is formed. The [capacitor dielectric layer] may also be composed of a Ta205 material. ----------- ^--~ (Please read the precautions on the back before filling in this page) Online Economy Chinese home car (CNS) see the grid (210X297 mm >

Claims (1)

Manganese Difficulty A8 Division B84U54S Recognition VI. Application for Patent Scope The Ministry of Economic Affairs Central Ministry of Economy and Trade Co., Ltd. Shellfish Consumer Cooperative Co., Ltd. 1-"F-Crystalline Silicon Structure of Integrated Circuits" The production method includes the following steps: [Semiconductor Wafer] forms [First Dielectric] and [Second Dielectric] and planarizes the [Second Dielectric]: A dielectric layer] and a [second dielectric layer] to form a hole. In the future, a conductor will be used as an electrical component on the "semiconductor wafer" through the [hole]. Contact; forming [First Polysilicon] and [Third Dielectric], said [S—polysilicon layer] and filling the [hole]; using Lithography technology: Photoresist pattern is formed above the [hole]; Lateral Etch — part of the [photoresist pattern] makes the size of the [photoresist pattern] Size smaller than the [hole]: unidirectional using etching technology Anisotmpical Etch The third dielectric layer not covered by the photoresist pattern to form a Third Dielectric Pillar, the unidirectional etching And terminating in the [first polycrystalline sand layer]; depositing a [second polycrystalline sand layer] (SecondPolysilicon); using etching technology to perform [unidirectional etch-back] on the [second polycrystalline silicon layer], The [unidirectional etch-back] etches away the [second polycrystalline silicon layer] and the [first polycrystalline silicon layer] on the surface of the [second dielectric layer], that is, the [second polycrystalline silicon layer] Unidirectional etch-back is terminated on the surface of the second dielectric layer to form a second polycrystalline silicon layer sidewall on the side of the third dielectric layer pillar. ); Removing the [third dielectric layer pillar]. 2 · The manufacturing method described in item 1 of the scope of patent application, wherein the [semiconductor wafer] contains electrical components. 3-The manufacturing method according to item 1 of the scope of patent application, wherein the [first dielectric layer] is composed of Silicon Nitride. 4 _ The manufacturing method described in item 1 of the scope of patent application, wherein the [second dielectric layer] is composed of silicon dioxide (Silicon Dioxide). 5 The manufacturing method according to item 1 of the scope of patent application, wherein the [third dielectric layer] is composed of sand dioxide. 6 _ The manufacturing method described in item i of the patent application range, wherein the [first polycrystalline layer] is formed by a [chemical vapor deposition method], and the thickness of tt is between 1000 angstroms and 4000 angstroms. 7. The manufacturing method according to item ^ of the patent scope, wherein the second polycrystalline silicon layer is formed by a chemical vapor deposition method, and the original degree is between 1000 Angstroms and 4000 Angstroms. Between Egypt. (Please read the precautions on the back before filling in this page) HS papers (CNS) Α4 washable (2 丨 0 > < 297 degrees) Manganese Difficulty A8 Division B84U54S for paper size application Scope of patent: The manufacturing method of the “F-Crystalline Silicon Structure of Integrated Circuits” by the Central Ministry of Economic Affairs of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives, includes the following steps: Forming a semiconductor wafer (Semiconductor Wafer) [A dielectric layer] (First Dielectric) and [second dielectric layer] (Second Dielectric), and planarizing the [second dielectric layer]: the [first dielectric layer] and the [second dielectric layer] are removed separately Dielectric layer] to form a hole. In the future, a conductor will contact the electrical components on the "semiconductor wafer" through the "hole"; Layer] (First Polysilicon) and [Third Dielectric], the [first-complex silicon layer] and filling the [hole]; using the lithography technology to [the hole] 】 Photoresist Pattern is formed on the top; Lateral Etch —Part The [photoresist pattern] makes the size of the [photoresist pattern] smaller than the size of the [hole]: unidirectional etching (Anisotmpical Etch) using etching technology is not affected by the [photoresist pattern] The [third dielectric layer] is covered to form a [Third Dielectric Pillar], and the unidirectional etching is terminated at the [first polycrystalline sand layer]; a layer is deposited [Second polycrystalline sand layer] (SecondPolysilicon); using etching technology to perform [unidirectional etchback] on the [second polycrystalline silicon layer], the [unidirectional etchback] etch away the [ [Second Dielectric Layer] The second polycrystalline silicon layer and the first polycrystalline silicon layer on the surface, that is, the unidirectional etch-back ends at the second dielectric layer. A second polycrystalline silicon layer sidewall (Second Polysilicon Spacer) on the side of the third dielectric layer pillar; and removing the third dielectric layer pillar. 2 · The manufacturing method described in item 1 of the scope of patent application, wherein the [semiconductor wafer] contains electrical components. 3-The manufacturing method according to item 1 of the scope of patent application, wherein the [first dielectric layer] is composed of Silicon Nitride. 4 _ The manufacturing method described in item 1 of the scope of patent application, wherein the [second dielectric layer] is composed of silicon dioxide (Silicon Dioxide). 5 The manufacturing method according to item 1 of the scope of patent application, wherein the [third dielectric layer] is composed of sand dioxide. 6 _ The manufacturing method described in item i of the patent application range, wherein the [first polycrystalline layer] is formed by a [chemical vapor deposition method], and the thickness of tt is between 1000 angstroms and 4000 angstroms. 7. The manufacturing method according to item ^ of the patent scope, wherein the second polycrystalline silicon layer is formed by a chemical vapor deposition method, and the original degree is between 1000 Angstroms and 4000 Angstroms. Between Egypt. (Please read the notes on the back before filling in this page) HS papers (CNS) Α4 washable (2 丨 0 > < 297 degrees) in paper size 411549 AS B8 C8 D8 VI. Patent Application Fan Yuan 8, as described in the patent application scope ^ 1 ^ production method, wherein the [unidirectional etch back] refers to Magnetic Enhanced Reactive Ion Etching (MERiE) or electronics Plasma etching techniques such as Electron Cyclotron Resonance (ECR) or traditional reactive ion plasma etching (Reactive Ion Etching; Rffi). The Ministry of Economic Affairs and Economics Bureau ’s Consumer Cooperatives ’Seal«. 9 A method for making memory cells of dynamic random access memory (DRAM), including the following steps: Forming on a Silicon Semiconductor Wafer "Metal Oxide Half Field Effect Transistor" (MOSFET) and Word Line; forming [First Dielectric] and [Second Dielectric] and planarizing the [Second Dielectric Layer]: The [First Dielectric Layer] and the [Second Dielectric Layer] are etched away to form an f-source contact window. In the future, a conductor will pass through The "source contact window" is in electrical contact with the "metal oxide half field effect transistor"; [First Polysilicon] and [Third Dielectric] are formed. A polycrystalline silicon layer] and fills the "source contact window"; a photoresist pattern is formed over the F source contact window "using lithography technology; lateral etch (Lateral Etch) — Part of the [Photoresist pattern] makes the [Photoresist pattern The size is smaller than the size of the F-source contact window; the unidirectional etching (AnisotmpicalEtch) using the etching technology is not covered by the [photoresist pattern] and the [third dielectric layer] is formed to form [ Third Dielectric Layer Pillar], the unidirectional etching ends in the [first polycrystalline silicon layer]: [second polycrystalline sand layer] (& 〇〇11 (1? 〇 丨 3 ^ 1 丨 (: 〇11); using the uranium etching technique to perform the [unidirectional etchback] on the [second polycrystalline silicon layer], and the [unidirectional etchback] [Erase the second polycrystalline sand layer] and the first polycrystalline silicon layer on the surface of the second dielectric layer, that is, the unidirectional etchback ends at Describe the surface of the [second dielectric layer] to form a second polysilicon spacer on the side of the [third dielectric layer pillar]; remove the [third dielectric layer pillar] ], Forming a charge storage electrode (StorageNode) of a capacitor composed of the remaining [first polycrystalline silicon layer] and [second polycrystalline silicon layer]; The [Charge Storage Electrode] deposits a very thin capacitor dielectric layer (Capacitor Dielectric) and [third polycrystalline silicon layer] on the surface, and then uses lithography technology and etching technology to remove the [Capacitor Dielectric Layer] and [The third polycrystalline silicon calendar] to form the upper electrode of the capacitor Γ ”〇 Plate” 10. The manufacturing method according to item 9 of the scope of patent application, wherein the “metal oxide half field effect electrical product body” 』Contains Gate Oxide, Gate Electrode, Spacer, and Source / Drain. 11 · The manufacturing method as described in item 9 of the scope of the patent application, wherein the [-dielectric chip] is composed of Silicon Nitride and the thickness is between 800 Angstroms and 1500 Angstroms. : ------ install ---: one. 丨 order ------- line (please read the precautions on the back before filling this page) This paper size is applicable to ZhongYin® Home Sample Rate (CNS > A4 * t grid (210X297 mm > 411549 g D8 VI. Patent application scope 12-The manufacturing method described in item 9 of the patent application model, wherein the [second dielectric layer] is made of dioxide It is made of Silicon Dioxide, and its thickness is between 3000 Angstroms and 9000 Angstroms. 13. The manufacturing method described in item 9 of the scope of patent application, wherein the [third dielectric layer] is made of nitride Sand composition, the thickness of which is between 1000 angstroms and 1,000 angstroms. M, the manufacturing method described in the ninth scope of the application, wherein the [first polycrystalline silicon layer] is [low pressure] Chemical Vapor Deposition] is formed with a thickness between 1000 Angstroms and 4000 Angstroms. 15-The manufacturing method described in item 9 of the scope of patent application, wherein the [Second Polycrystalline Silicon Layer] is a low pressure Chemical Vapor Deposition] is formed with a thickness between 1000 Angstroms and 4000 Angstroms. 16 · The production method described in item 9 of the scope of patent application 'wherein [The third polycrystalline silicon layer] is formed by a [low-pressure chemical vapor deposition method], and the thickness of tt is between 1000 angstroms and 3,000 angstroms. 17 · As described in item 9 of the patent scope The manufacturing method, wherein the [unidirectional holmium etching] refers to a magnetic enhanced active ion-type etch (Magnetic Enhanced Reactive on Etching; MER1E) or an electron cyclotron resonance etch (Electron Cyclotron Resonance; ECR) ) Or traditional reactive ion etching technology (Reactive Ion Etching; RIE) and other plasma etching technology-18 · $ [] application for the manufacturing method described in item 9 of the patent scope, wherein the [capacitor dielectric layer] It is composed of silicon oxide nitride (Oxynitride), silicon nitride, and silicon dioxide, or it is composed of Ta205. 19 · The manufacturing method as described in item 9 of the scope of patent application, wherein [ The third dielectric layer pillar] can also be further removed from the "second dielectric layer". ----; ---; --------------- (Please read the notes on the back and fill in this page.) This paper-foot waves and applicable in ® because the home lao rate (CNS) A4 * ll grid (210X297 mm)