經濟部中央橾Α局員工消費合作社印製 S93946 A7 B7 五、發明説明（I ) ]L .發明之技術領域 本發明是有關形成積體電路之動態隨機存取記憶體元件 之電容器（Capacitor)的方法（Method)，此方法可在較小 的電路佈局面積之下擁有較大的電容，並提高產品的良率。 2.發明背景 近年來，動態隨機存取記憶體的集積化（Packing Density)急速增加，目前已進入一仟六百萬位元的量產階 段，NEC、Hitachi與SONY等日本半導體公司並宣稱已經有 一萬萬位元動態隨機存取記憶體（1GB DRAM)的樣品問世。 典型的動態隨機存取記憶體是在半導體矽基板上製造一個場 效電晶體（Field Effect Transistor ; FET)與電容器 (Capacitor)，並利用所述場效電晶體的源極（Source)來 連接電容器的電荷儲存電極（Storage Node)以形成動態隨 機存取記憶體的記憶元（Memory Cell)。 爲了達到動態隨機存取記憶體元件高度積集化的目的， 必需縮小記憶元的尺寸’然而電容器尺寸的縮小將降低電容 値’使得記憶電路的訊號/雜訊（Signal Noise ; S/N)比例 降低，造成電路誤判或電路不穩定等缺點。所以，爲了達成 動態隨機存取記憶體的高度積集化，必需尋求更尖端的製程 技術來降低記憶元之電路佈局面積（Plannar Area)，並且 同時維持相同的電容値》 爲了增加動態隨機存取記憶體之電容器面積，一些特殊 改良型的堆疊式電谷器結構，例如，皇冠型（Crown-Shaped)等結構相繼出現’然而，形成這些結構的製程相當 複雜，製程可靠度差。以日本Mitsubishi公司Kumanoya 本紙ft尺晒家縣（CNS 祕⑺---—— (請先閲讀背面之注意事項再填寫本頁) •Λ—裝. 訂 人線 293946 ¾濟部中央噤a局員工消費合作社印策 A7 B7 五、發明説明（α) 等人的美國專利第5077688號所揭露之【Semiconductor memory device having improved memory cells provided with cylindrical type capacitors 】爲例，係以複晶矽 側壁子（Polysilicon Spacer)爲主體來形成皇冠型之電容 器的電荷儲存電極（Crown-Shaped Storage node)，雖然 提供了足夠的電容器面積，但製程方法的複雜，卻也降低了 產品的良率。 本發明揭露了一種堆鞔式動態隨機存取記憶體（Stack Dynamic Random Access Memory ; Stack DRAM)之改良型電 容器的製程方法》此方法大幅增加了電容器之電容値，使得 電容器電容値遠比傳統堆盤式電容器的電容値大，特別適用 於六仟四百萬位元以上的集積密度之動態隨機存取記憶體的 製造，同時，由於製程方法比傳統皇冠型電容器簡易，本發 明揭露之方法所製造出產品的良率也比傳統皇冠型方法高。 3·發明之簡要說明 本發明之目的是提供一種在有限電路佈局面積內提高動 態隨機存取記憶體之電容値的製程。 本發明之另一個目的是提供一種【高良率】的動態隨機 存取記憶體之電容器製程。 以電容器在位元線上方（Capacitor Over Bitline ; COB)之六仟四百萬位元(64MB)堆疊式動態隨機存取記憶體 結構爲例，本發明實施例之主要製程包括如下。 【本發明之第一個實施例】·· (1)形成隔離電性活動區（Active Area)所需的場氧化層 (Field Oxide); ；—k ( I裝 訂-----C .線 (請先閱讀背面之注意事項再填寫本頁) 本紙杀尺度適用中國國家#準（CN’S ) Λ4規格（公釐) 經濟部中央墚i局員二消费合作杜印製 A7 B7 五、發明説明（>) (2)形成場效電晶體與字語線（Word 1 ine)，所述場效電晶 t 體包含有閘介電層（Gate Dielectric)、閘電極 (Gate Electrode)，側壁子（Spacer)與源極/汲極 (Source/Drain); (4) 形成記憶體之位元線（Bit Line); (5) 形成【第一絕緣層】、【第二絕緣層】與【第三絕緣 層】，並利用微影及蝕刻技術形成源極接觸窗（Node Contact); (6) 形成一層【攙雜的第一複晶矽層】，所述攙雜的第一複 晶矽層並塡滿所述源極接觸窗（Node Contact); (7) 在所述源極接觸窗之間的上方，利用微影及蝕刻技術單 向性（Anisotropically)的触去一部份所述【撞雜的 第一複晶矽層】，以形成凹溝（Trench); (8) 形成【第四絕緣層】，並利用電漿蝕刻技術對所述第四 絕緣層進行單向性（Anisotropically)的回触刻，以 在所述凹溝之兩側形成【第一個絕緣層側壁子】 (First Spacer)； (9) 以所述【第一個絕緣層側壁子】爲蝕刻保護罩（Etch Mask)，利用電漿蝕刻技術對所述【攙雜的第一複晶 矽層】進行單向性的蝕刻，蝕去一部份所述【攙雜的第 一複晶矽層】； (10) 利用稀釋氫氟酸溶液（Diluted HF)去除所述【第一 個絕緣層側壁子】； (11) 形成【第五絕緣層】，並利用電梁蝕刻技術對所述第 五絕緣層進行單向性的回触刻，以形成【第二個絕緣 — L--Ίι-----^ *裝------訂-----(線 (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS ) A4規格(：：10 X 公釐） Μ·*部中央嘌1¾¾負二消費合作ΐ印製 293946 五、發明説明（/) 層側壁子】（Second Spacer); (12) 以所述【第二個絕綠層側壁子】爲蝕刻保護罩（Etch Mask),利用電漿蝕刻技術對所述【攙雜的第一複晶 矽層】進行單向性的蝕刻，將所述凹溝方向的【攙雜 的第一複晶矽層】蝕刻乾淨； (13) 利用稀釋氫氟酸溶液（Diluted HF)去除所述【第二 個絕緣層側壁子】，皇冠型（Crown-Shaped)之電荷 儲存電極於焉形成； (14) 形成一層厚度極薄的電容器介電層（Capacitor Dielectric); (15) 形成一層【攙雜的第二複晶矽層】’並製定電容器的 上層電極（Top Electrode) ° 【本發明之第二個實施例】： 在第一個實施例的步驟（8 )之後’續接以下步驟（30 ) 到（33)，即爲本發明之第二個實施例。 (30) 以所述【第一個絕緣層側壁子】爲蝕刻保護罩（Etch Mask)，利用電漿蝕刻技術對所述【攙雜的第一複晶 矽層】進行單向性的蝕刻’蝕去一部份所述【攙雜的第 一複晶矽層】，蝕刻終止於源極接觸窗之間之所述【第 三絕緣層】之表面； (31) 利用稀釋氫氟酸溶液（Diluted HF)去除所述【第一個 絕緣層側壁子】，皇冠型（Crown—Shaped)之電荷儲 存電極於焉形成； (32) 形成一層厚度極薄的電容器介電層（CaPacitor Dielectric); 本纸張尺度適用中國國家標準（CNS ) A4规格（公嫠、 Π—L rl·----C .裝-- (請先閲讀背面之注意事項再填寫本頁) 訂 --Γ" 娌專：部中央嘌|1局員二消费合作紅印装 A7 B7 五、發明説明（{) (33)形成一層【攙雜的第二複晶矽層】，並製定電容器的上 , 層電極（Top Electrode) 〇 令·圖示的簡要說明 / / 圖一至圖十二是本發明之第一個實施例的製程剖面圖，圖十 三至圖十四是本發明之第二個實施例的製程剖面圖》 5·發明之實施例 此部份將配合圖示說明，圖示部份只畫出一個單元之記 憶元，並省略井區結構（Well Structure)，對此發明而言 可爲N井區或P井區，且此製程可自然延伸到與CMOS製 程相結合。 圖一至圖十二是本發明之第一個實施例。 首先，在P型矽半導體基板1G上形成場氧化層12， 此場氧化層厚度約介於3000埃到5500埃之間，然後，再 形成場效電晶體，所述場效電晶體包含有閘介電層14 (Gate Dielectric)、閘電極 16 (Gate Electrode)，側壁子 18 (Spacer )與源極 / 汲極區域 22 (Source / Drain Region)。所述閘介電層14係以熱氧化方式形成，其厚度介 於50到140埃之間。所述閘電極16係以低壓化學氣相沉 積法（Low Pressure Chemical Vapor Deposition ; LPCVD)形成之複晶矽或複晶矽化物16 (Polycide) ’其厚 度介於1500到3500埃之間，接著，以低壓化學氣相沉積 法形成二氧化矽17，其厚度介於500到1200埃之間，再 利用蝕刻技術制定所述二氧化矽Π與複晶矽或複晶矽化物 16的圖案。接著，沉積介電層18並進行單向性的回蝕刻， 以在閘電極圖案16之二側產生介電層側壁子18 »所述源 ---1K----( _裝------訂-----C 線 (請先閲讀背面之注意事項再填寫本頁) 玉紙張尺度適用t國國家標準（CNS ) A4規格（210X 297公釐i 經濟部3»..,央噤準局員工消费合作社印製 A7 ____B7_ 五、發明説明（‘） 極/汲極區域汉係使用砷離子進行N+源極/汲極離子佈 値來形成，其離子佈値劑量介於2E15到1E16原子/平方公 分之間，離子佈値能量則介於20到80 kev之間，場效電 晶體的製作，於焉完成，如圖一所示。 接著，沈積第一絕緣層28、第二絕緣層32與第三絕緣 層34。所述第一絕緣層28與第二絕緣層32通常以低壓 化學氣相沉積法形成之二氧化矽，其反應氣體爲TEOS、N20 和〇2，反應溫度爲720 °C，反應壓力爲250 mtorr，厚度 介於1G00到20⑼埃之間。所述第三絕緣層34則爲以大 氣壓化學氣相沉積法（Atmosphere Pressure Chemical Vapor Deposition ; APCVD)形成之硼磷玻璃薄膜（8〇1>〇-PhosphoSilicate Glass : BPSG)，反應壓力爲 760 mtorr，反應溫度爲400 °C，反應氣體爲TEOS (TetraEthylOrthoSilicate)2056 seem ' TMB (TriMethyl Borate)46 seem 、 TMP (TriMethyl Phosphite)62 seem 與 N2 1314 seem，剛完成沉積時之厚度介於5000到10000埃 之間，如圖二所示。接著，利用微影及蝕刻技術蝕去所述第 一絕緣層28、第二絕緣層32與第三絕緣層34，以形成源 極接觸窗（Node Contact)，如圖三所示，未來，電容器的 電荷儲存電極將透過所述【源極接觸窗】跟所述場效電晶體 之源極/汲極22作電性接觸。 參考圖四。沈積一層攙雜的第一複晶矽層38 (Doped Polysilicon)，所述摄雜的第一複晶矽層38將塡滿所述 【源極接觸窗】；所述攙雜的第一複晶矽層38係以低壓化 學氣相沉積法形成，反應氣體是（15% PH3/85% SiH4)與 本紙張尺度適用中國國家標準（CNS ),A4規格（210X29?公釐) ί----C. —裝-- {請先閲讀背面之注意事項再填寫太頁) 訂 •Λ-線----- 33946 經濟部中央堞盔奇員二消費合作社印装 A7 B7 五、發明説明（γ) (5% PH3/95% N2)的混合氣體，反應溫度爲570°C，厚度介 於6000到10000埃之間。接著，利用薇影及蝕刻技術單向 性（Anisotropically)的餽去所述【携雜的第一複晶#層 38】大約1000埃左右的厚度，以形成具有凹溝（Trench)之 【攙雜的第一複晶矽層38A】，如圖五所示。 參考圖六。沈積第四絕緣層40，所述第四絕緣層40通 常是以低壓化學氣相沉積法形成之二氧化矽（Si〇2) ’其反 應氣體爲TE0S、N20和〇2，反應溫度爲720 °C ’反應壓力 爲250 mtorr，厚度介於800到1200埃之間。接著，利 用電漿蝕刻技術對所述第四絕緣層40進行單向性 (Anisotropically )的回触刻，以在所述凹溝之兩側形成 【第一個絕緣層側壁子40A】（First Spacer)，如圖七所 示。然後，以所述【第一個絕緣層側壁子40A】爲蝕刻保護 罩（Etch Mask)，利用電紫鈾刻技術單向性的蝕去所述【攙 雜的第一複晶矽層38A】大約2000埃左右的厚度，形成 【攙雜的第一複晶矽層38B】，如圖八所示。 接著，形成第五絕緣層44，如圖九所示，所述第五絕緣 層44通常是以低壓化學氣相沉積法形成之二氧化矽 (Si〇2)，厚度介於800到1200埃之間。然後，利用電漿 蝕刻技術對所述【第五絕緣層44】進行單向性的回蝕刻，以 开夕成【第二個絕緣層側壁子44A】（Second Spacer)，如圖 十所示。 接著，以所述【第二個絕緣層側壁子44A】爲蝕刻保護 罩（Etch Mask)，利用電漿蝕刻技術單向性的蝕去所述【攙 雜的第一複晶矽層38B】大約600G埃左右的厚度，將所述 本紙張尺度適用中國國家標準（CNs ) A4規格[:!0'< 297公釐） IL—1----f 裝------訂------ (請先閲讀背面之注意事項再填寫本頁) B7 經濟部中央標皋局貝工消費合作社印製 五、發明説明（牙） 凹溝方向的【攙雜的第一複晶矽層38B】蝕刻乾淨’蝕刻終 止於凹溝方向的所述【第三絕緣層’34】之表面’如圖十一 所示，然後，再利用稀釋氮氟酸溶液（Diluted HF)去除所 述【第二個絕緣層側壁子44A】，皇冠型（Crown-Shaped) 之電荷儲存電極50於焉形成，如圖十二所示。 最後，在所述電容器的電荷儲存電極50表面形成一層 厚度極薄的【電容器介電層】’並以低壓化學汽相沈積法形 成【攙雜的第二複晶矽層】，其厚度介於1G0()埃到2000 埃之間，再利用電發蝕刻技術製定電容器之上層電極圖案， 便完成了動態隨機存取記憶體之電容器的結構。 【本發明之第二個實施例】： 在第一個實施例的圖七之後’續接以下以下圖十三至圖十 四，即爲本發明之第二個實施例。 接著，以所述【第一個絕緣層側壁子4GA】爲触刻保護 罩（Etch Mask)，利用電漿蝕刻技術單向性的蝕去所述【攙 雜的第一複晶政層38A】大約5000埃左右的厚度，將所述 Hfi方向的【攙雜的第一複晶砂層38A】触刻乾淨’鈾刻終 止於凹溝方向的所述【第三絕緣層34】之表面’如圖十三 所示。 然後，再利用稀釋氫氟酸溶液（Diluted HF)去除所述 【第一個絕緣層側壁子40A】’皇冠型（Crown—ShaPed)之 電荷儲存電極88於焉形成，如圖十四所示。 最後，在所述電容器的電荷儲存電極88表面形成一層 厚度極薄的【電容器介電層】’並以低壓化學汽相沈積法形 成【攙雜的第二複晶政層】’其厚度介於10⑽埃到2000 本紙張尺度適用中國國家標準（OiS ) μ規格（210x297公慶） IL-L.----f ··裝------訂------^" (請先閱讀背面之注意事項再填寫本頁) B7 五、發明説明（了） 埃之間，再利用電獎蝕刻技術製定電容器之上層電極（Top Plate)圖案，便完成了動態隨機存取記憶體之電容器的結 構。 (请先閲讀背面之注意事項再填寫本頁) .Λ••裝______1Τ 「線--- 經濟部中央樣龛局員工消費合作钍印製 本纸張尺度適用中國國家標準（CNS ;· Α·4規格ί: ；1!0Χ：：97公釐）S93946 A7 B7 printed by the Employee Consumer Cooperative of the Central Department of Economic Affairs of the Ministry of Economy V. Description of the Invention (I)] L. Technical Field of the Invention The present invention relates to a capacitor (Capacitor) for forming a dynamic random access memory element of an integrated circuit Method (Method), this method can have a larger capacitance under a smaller circuit layout area, and improve product yield. 2. Background of the Invention In recent years, the packing density of dynamic random access memory has increased rapidly, and has now entered the mass production stage of 16 million bits. Japanese semiconductor companies such as NEC, Hitachi and SONY have declared that they have already A sample of 10,000-bit dynamic random access memory (1GB DRAM) is available. A typical dynamic random access memory is to manufacture a field effect transistor (FET) and a capacitor (Capacitor) on a semiconductor silicon substrate, and use the source of the field effect transistor to connect the capacitor The storage node of the charge is used to form a memory cell of the dynamic random access memory. In order to achieve the purpose of highly accumulating dynamic random access memory components, it is necessary to reduce the size of the memory cell. However, the reduction in the size of the capacitor will reduce the capacitance value so that the signal / noise (S / N) ratio of the memory circuit Reduce, resulting in shortcomings such as circuit misjudgment or circuit instability. Therefore, in order to achieve a high degree of integration of dynamic random access memory, it is necessary to seek more advanced process technology to reduce the circuit layout area of the memory cell (Plannar Area), and at the same time maintain the same capacitance value. In order to increase dynamic random access The area of the capacitor of the memory and some specially improved stacked electrical valley structures, such as crown-shaped (Crown-Shaped) and other structures have appeared one after another. However, the process of forming these structures is quite complicated and the reliability of the process is poor. Take Kumanoya, Japan Mitsubishi company, ft ruler, Xiajia County (CNS secret ⑺ --- (please read the precautions on the back before filling out this page) • Λ—install. Order line 293946 ¾ employees of the Central Ministry of Economic Affairs Consumer Cooperative Institution A7 B7 V. Description of Invention (α) et al. [Semiconductor memory device having improved memory cells provided with cylindrical type capacitors] disclosed in US Patent No. 5077688, taking polysilicon sidewalls (Polysilicon Spacer) is the main body to form a Crown-Shaped Storage Node (Crown-Shaped Storage Node), although it provides enough capacitor area, but the complexity of the manufacturing process, but also reduces the yield of the product. The present invention discloses a Stack Dynamic Random Access Memory (Stack Dynamic Random Access Memory; Stack DRAM) improved capacitor manufacturing method "This method greatly increases the capacitance value of the capacitor, making the capacitor capacitance value is much higher than the capacitance of the traditional stacked disc capacitor Very large, especially suitable for dynamic random access memory with an accumulation density of more than 64 million bits At the same time, because the manufacturing method is simpler than the traditional crown type capacitor, the yield rate of the product disclosed by the method of the present invention is also higher than the traditional crown type method. 3. Brief description of the invention The purpose of the present invention is to provide a A process for improving the capacitance value of a dynamic random access memory within a limited circuit layout area. Another object of the present invention is to provide a [high yield] process for a capacitor of a dynamic random access memory. With a capacitor above the bit line ( Capacitor Over Bitline (COB) 64-megabit (64MB) stacked dynamic random access memory structure as an example, the main process of the embodiment of the present invention includes the following. [The first embodiment of the present invention] · · (1) Forming the field oxide layer (Field Oxide) required to isolate the electrical active area (Active Area);; -k (I binding ----- C. Line (please read the precautions on the back before filling in this Page) The standard of this paper is applicable to China's national standard #CN (S ') Λ4 specification (mm). The Central Bureau of Economic Affairs of the Ministry of Economy II. Consumer cooperation. Du printed A7 B7. 5. Description of the invention (>) (2) Formation of field effect transistors and Word line (Word 1 ine), the field effect transistor includes gate dielectric layer (Gate Dielectric), gate electrode (Gate Electrode), side wall (Spacer) and source / drain (Source / Drain) ; (4) Form the bit line of the memory (Bit Line); (5) Form the [first insulating layer], [second insulating layer] and [third insulating layer], and use lithography and etching technology to form the source Pole contact window (Node Contact); (6) Form a layer [doped first polycrystalline silicon layer], the doped first polycrystalline silicon layer and fill the source contact window (Node Contact); (7 ) Above the source contact window, use lithography and etching technology to anisotropically (Anisotropically) part of the [impacted first polycrystalline silicon layer] to form a recess ( Trench); (8) Form [Fourth Insulation Layer], and use plasma etching technology to perform anisotropically etching back on the fourth insulation layer to form [on both sides of the trench The first insulating layer side wall] (First Spacer); (9) Using the [first insulating layer side wall] as an etch protection mask (Etch Mask), Plasma etching technology unidirectionally etched the [doped first polycrystalline silicon layer] to etch away a part of the [doped first polycrystalline silicon layer]; (10) using diluted hydrofluoric acid The solution (Diluted HF) removes the [first insulating layer side wall]; (11) forms a [fifth insulating layer], and uses a beam etching technique to unidirectionally etch back the fifth insulating layer , To form [Second Insulation-L--Ίι ----- ^ * installed ------ order ----- (line (please read the precautions on the back before filling this page) This paper The Zhang scale is applicable to the Chinese National Standard (CNS) A4 specification (: 10 X mm). The central part of the M · * 1¾¾negative consumer cooperation is printed 293946. V. Description of the invention (/) Layer side wall] (Second Spacer); (12) Using the [second green layer sidewall] as an etch protection mask (Etch Mask), using plasma etching technology to unidirectionally etch the [doped first polycrystalline silicon layer], Etch the [doped first polycrystalline silicon layer] in the direction of the groove clean; (13) remove the [second insulating layer] with a diluted hydrofluoric acid solution (Diluted HF) Side wall], crown-shaped (Crown-Shaped) charge storage electrode is formed in Yan; (14) forming a very thin capacitor dielectric layer (Capacitor Dielectric); (15) forming a layer [doped second polycrystalline silicon Layer] 'and formulate the top electrode of the capacitor (Top Electrode) ° [the second embodiment of the present invention]: After the step (8) of the first embodiment, the following steps (30) to (33) are continued, This is the second embodiment of the present invention. (30) Using the [first insulating layer sidewall] as an etch protection mask (Etch Mask), use plasma etching technology to unidirectionally etch the [doped first polycrystalline silicon layer] Remove part of the [doped first polycrystalline silicon layer], and the etching ends at the surface of the [third insulating layer] between the source contact windows; (31) Use dilute hydrofluoric acid solution (Diluted HF ) Remove the [first insulating layer side wall], the crown-shaped (Crown-Shaped) charge storage electrode is formed in Yan; (32) forming a very thin capacitor dielectric layer (CaPacitor Dielectric); this paper The standard is applicable to the Chinese National Standard (CNS) A4 specification (Gongju, Π—L rl · ---- C. Installed-(please read the precautions on the back and then fill out this page) Order --Γ " Special: Department Central Purine | 1 Bureau member 2 Consumer Cooperation Red Printing Pack A7 B7 V. Description of invention ({) (33) Form a layer of [doped second polycrystalline silicon layer], and formulate the top electrode of the capacitor (Top Electrode). Order · A brief description of the figures // Figures 1 to 12 are the process cross sections of the first embodiment of the present invention Figures 13 to 14 are process cross-sectional views of the second embodiment of the present invention. 5. Embodiments of the invention This part will be accompanied by illustrations, and only one unit of memory cell is shown in the illustration. And the well structure is omitted (Well Structure), for this invention it can be N-well area or P-well area, and this process can be naturally extended to be combined with the CMOS process. Figures 1 to 12 are the first of the present invention Example: First, a field oxide layer 12 is formed on the P-type silicon semiconductor substrate 1G, and the thickness of the field oxide layer is approximately between 3000 angstroms and 5500 angstroms, and then a field effect transistor is formed. It includes a gate dielectric layer 14 (Gate Dielectric), a gate electrode 16 (Gate Electrode), a side wall 18 (Spacer) and a source / drain region 22 (Source / Drain Region). The gate dielectric layer 14 is composed of It is formed by thermal oxidation, and its thickness is between 50 and 140 angstroms. The gate electrode 16 is polycrystalline silicon or polycrystalline silicide 16 (Low Pressure Chemical Vapor Deposition; LPCVD) formed by low pressure chemical vapor deposition (LPCVD) Polycide) 'The thickness is between 1500 and 3500 Angstroms, then The silicon dioxide 17 is formed by low-pressure chemical vapor deposition with a thickness between 500 and 1200 angstroms, and then the pattern of the silicon dioxide II and the polycrystalline silicon or polycrystalline silicide 16 is formed by etching technology. Then, The dielectric layer 18 is deposited and etched back unidirectionally to produce dielectric layer sidewalls 18 on both sides of the gate electrode pattern 16 »The source --- 1K ---- (_ 装 ----- -Subscribe ----- C line (please read the precautions on the back before filling in this page) The jade paper scale is applicable to the national standard (CNS) A4 specification (210X 297 mm i Ministry of Economic Affairs 3 ».., central government A7 printed by the Bureau of Consumers ’Cooperatives of the Bureau of Prospects V. Description of the invention (') The pole / drain area is formed by the arsenic ions in the N + source / drain ion pattern. The ion pattern dose is between 2E15 and 1E16 atoms. / Square centimeter, the energy of the ion distribution is between 20 and 80 kev, and the fabrication of the field effect transistor is completed in Yan, as shown in Figure 1. Next, the first insulating layer 28, the second insulating layer 32 and the third insulating layer 34 are deposited. The first insulating layer 28 and the second insulating layer 32 are usually silicon dioxide formed by low-pressure chemical vapor deposition, the reaction gases are TEOS, N20 and 〇2, the reaction temperature is 720 ° C, and the reaction pressure is 250 mtorr , The thickness is between 1G00 and 20⑼Angstroms. The third insulating layer 34 is a boron-phosphorus glass film (8〇1> 〇-PhosphoSilicate Glass: BPSG) formed by atmospheric pressure chemical vapor deposition (Atmosphere Pressure Chemical Vapor Deposition; APCVD), and the reaction pressure is 760 mtorr, The reaction temperature is 400 ° C, the reaction gas is TEOS (TetraEthylOrthoSilicate) 2056 seem 'TMB (TriMethyl Borate) 46 seem, TMP (TriMethyl Phosphite) 62 seem and N2 1314 seem, the thickness at the time of the completion of the deposition is between 5000 and 10000 Angstroms As shown in Figure 2. Next, the first insulating layer 28, the second insulating layer 32 and the third insulating layer 34 are etched away using lithography and etching techniques to form a source contact (Node Contact). As shown in FIG. 3, in the future, capacitors The charge storage electrode will make electrical contact with the source / drain 22 of the field effect transistor through the [source contact window]. Refer to Figure 4. Depositing a doped first polycrystalline silicon layer 38 (Doped Polysilicon), the doped first polycrystalline silicon layer 38 will fill the [source contact window]; the doped first polycrystalline silicon layer The 38 series is formed by low-pressure chemical vapor deposition, the reaction gas is (15% PH3 / 85% SiH4) and the paper size is applicable to the Chinese National Standard (CNS), A4 specification (210X29? Mm) ί ---- C. —Installation— (Please read the precautions on the back and then fill in the page) Order • Λ- 线 ----- 33946 Ministry of Economic Affairs Central Helicopter Helmet II Consumer Cooperative Printed A7 B7 V. Description of invention (γ) ( 5% PH3 / 95% N2) gas mixture with a reaction temperature of 570 ° C and a thickness between 6000 and 10000 Angstroms. Next, the isotropic (Anisotropically) feed of the [carrying first polycrystal # layer 38] thickness of about 1000 angstroms is used to form a [doped] with a trench (Trench) The first polycrystalline silicon layer 38A], as shown in Figure 5. Refer to Figure 6. A fourth insulating layer 40 is deposited. The fourth insulating layer 40 is usually silicon dioxide (Si〇2) formed by low-pressure chemical vapor deposition. The reaction gases are TEOS, N20, and 〇2, and the reaction temperature is 720 °. The C 'reaction pressure is 250 mtorr and the thickness is between 800 and 1200 angstroms. Next, the plasma etching technique is used to perform anisotropically etching on the fourth insulating layer 40 to form a [first insulating layer sidewall 40A] (First Spacer) on both sides of the groove ), As shown in Figure 7. Then, the [first insulating layer sidewall 40A] is used as an etch protection mask (Etch Mask), and the unidirectional etching is performed to remove the [doped first polycrystalline silicon layer 38A] by using electroviolet uranium etching technology. With a thickness of about 2000 angstroms, [doped first polycrystalline silicon layer 38B] is formed, as shown in FIG. 8. Next, a fifth insulating layer 44 is formed. As shown in FIG. 9, the fifth insulating layer 44 is usually silicon dioxide (SiO 2) formed by low-pressure chemical vapor deposition, with a thickness ranging from 800 to 1200 angstroms. between. Then, the plasma etching technique is used to unidirectionally etch back the [fifth insulating layer 44] to form the [second insulating layer sidewall 44A] (Second Spacer), as shown in FIG. Next, the [second insulating layer sidewall 44A] is used as an etch protection mask (Etch Mask), and the plasma is etched to unidirectionally etch the [doped first polycrystalline silicon layer 38B] about 600G For the thickness of about Angstroms, apply the paper size to the Chinese National Standard (CNs) A4 specification [:! 0 '< 297mm) IL—1——f Installed ——————— --- (Please read the precautions on the back before filling in this page) B7 Printed by the Beigong Consumer Cooperative of the Central Standardization Bureau of the Ministry of Economic Affairs V. Description of invention (teeth) [Mixed first polycrystalline silicon layer 38B in the direction of the ditch 】 Etching clean 'The surface of the [third insulating layer '34] etched in the direction of the ditch is shown in Figure 11, and then, using a diluted nitrogen fluoride solution (Diluted HF) to remove the [second An insulating layer sidewall 44A], a crown-shaped (Crown-Shaped) charge storage electrode 50 is formed in Yan, as shown in FIG. Finally, a thin layer of [capacitor dielectric layer] is formed on the surface of the charge storage electrode 50 of the capacitor, and a low-pressure chemical vapor deposition method is used to form a [doped second polycrystalline silicon layer] with a thickness of 1G0 () Between Angstroms and 2000 Angstroms, and then use electro-etching technology to formulate the upper electrode pattern of the capacitor to complete the structure of the capacitor of the dynamic random access memory. [The second embodiment of the present invention]: After FIG. 7 of the first embodiment, the following FIGS. 13 to 14 are continued, which is the second embodiment of the present invention. Next, the [first insulating layer sidewall 4GA] is used as an etching mask (Etch Mask), and the plasma is etched to unidirectionally etch the [doped first polycrystalline layer 38A] about With a thickness of about 5000 angstroms, the [doped first polycrystalline sand layer 38A] in the Hfi direction is cleanly touched, and the surface of the [third insulating layer 34] in the direction of the groove is terminated by uranium etching, as shown in FIG. As shown. Then, a diluted hydrofluoric acid solution (Diluted HF) is used to remove the [first insulating layer side wall 40A] 'Crown-Shaped charge storage electrode 88 is formed in Yan, as shown in FIG. 14. Finally, a very thin [capacitor dielectric layer] is formed on the surface of the charge storage electrode 88 of the capacitor, and a low-pressure chemical vapor deposition method is used to form the [doped second polycrystalline layer] with a thickness of 10⑽ Angstrom to 2000 This paper scale is applicable to Chinese National Standard (OiS) μ specifications (210x297 gong) IL-L .---- f ·· installation ------ order ------ ^ " (please Read the precautions on the back first and then fill out this page) B7 V. Description of the Invention (A) Between Egypt and Egypt, the top plate electrode pattern of the capacitor is formulated using the electric award etching technology to complete the dynamic random access memory. The structure of the capacitor. (Please read the precautions on the back before filling in this page). Λ •• Install ______1T "Line --- The Ministry of Economic Affairs Central Sample Alcohol Bureau Employee Consumption Cooperation Thorium Printed This paper scale applies the Chinese National Standard (CNS; · Α · 4 specifications ί:; 1! 0Χ :: 97mm)