JP2898929B2 - Manufacturing method of stacked DRAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DRA for an integrated circuit.
M (Dynamic Random Access M)
manufacturing method, in particular, a stacked DRAM
(Stack DRAM).

[0002]

2. Description of the Related Art A typical stacked DRAM includes a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor) on a silicon semiconductor wafer.
actor Field Effect Transi
MOSFET) and a capacitor, and are connected to a lower electrode (Storage Node) of the capacitor using the source electrode of the above-mentioned field effect transistor, thereby forming a DRAM memory cell (Memory C).
ell), and an enormous number of memory cells were assembled to form a memory integrated circuit.

In recent years, the integration density of DRAMs (Pac
(King Density) is increasing rapidly, and the memory cell size is already 6 to 1.5 square microns.
Those with 14 million bits are mass-produced. At NEC Corporation (NEC), a Japanese semiconductor manufacturer, 199
It has announced that it has already developed a 1 Gigabit DRAM prototype in 5 years. In addition, Hsinchu Science Industrial Park in Taiwan (Science Backed Industry)
Integrated circuit makers such as Mosel-Vitelic and TI-Acer, Inc., Parke, Calif., already have 16-million-bit DRAMs of 0.4-0.45 microns.
Has entered the mass production stage.

In order to achieve the purpose of high integration of DRAM, it is necessary to reduce the size of memory cells, which means that the size of field effect transistors and capacitors must be reduced. However, as the size of the capacitor decreases, the capacitance value decreases, and the signal-to-noise ratio (Signal Noise; S / N) of the memory circuit decreases.
This led to faults such as erroneous disconnection of the electric circuit or instability of the electric circuit.

As a structure for maintaining or increasing the capacitance value of the capacitor when reducing the size of the capacitor, Masao Taguch of Fujitsu Limited of Japan is used.
The structure of a fin type capacitor disclosed in U.S. Pat. No. 5,021,357 by Ii et al. is the most typical, but the fin type capacitor has the following disadvantages. The first is that the lower electrode has a relatively weak structure because the fins on both sides are connected to different polysilicon, and the second is that the lower electrode has a relatively sharp geometrical shape. This means that local breakdown (Breakdown) of the capacitor dielectric layer easily occurred at the edge (Edge).

[0006]

SUMMARY OF THE INVENTION The main object of the present invention is to:
Stack Capacitor (Stack Capa)
(Citor) manufacturing method.

Another object of the present invention is to provide a method of manufacturing a high density stacked DRAM.

[0008]

The invention of claim 1 is a method of manufacturing a kind of stacked DRAM (Stack DRAM), and comprises a silicon semiconductor substrate (Silicon Se).
(Micon conductor Substrate)
An oxide layer (Ox) used to isolate the field effect transistor using local silicon oxide isolation technology (LOCOS)
ide), a field effect transistor including a gate oxide layer, a gate electrode, a source electrode, and a drain electrode, a word line (Word Line), a single dielectric layer, and a thermal chemical vapor deposition. (Alternative Layer) consisting of a thermal chemical vapor deposition silicon dioxide layer deposited by a CVD method and a plasma silicon dioxide layer.
s) is formed, and the alternate multilayer structure and the dielectric layer are etched using lithography and etching techniques to expose the source electrode, thereby forming a memory cell contact (Cell Con) of the field effect transistor.
tact), side-etching, removing some of the above-mentioned plasma silicon dioxide layer and thermal chemical vapor grown silicon dioxide layer, Cavities between the silicon layers (Cavit
y) to form wrinkled sidewalls (Corr
rugged side wall), a single layer of first polysilicon is formed, the first polysilicon layer is filled with the above-mentioned cavity, the memory cell contact is straddled, and lithography and etching techniques are used. Etching the first polysilicon layer in the capacitor region, thereby forming the lower electrode (Stor) of the capacitor.
age node) and a capacitor dielectric layer (Ca
a dielectric layer), a second polysilicon layer is formed, and the above-mentioned second polysilicon layer and capacitor dielectric layer are etched using lithography and etching techniques to form an upper electrode (T) of the capacitor.
op Plate) to form a stacked DRAM.

According to a second aspect of the present invention, there is provided a method for manufacturing a stacked DRAM according to the first aspect, wherein the dielectric layer is composed of an undoped silicon oxide layer and a nitrated silicon layer. Stack DRA with a thickness between 1000 and 3000 Angstroms and a thickness of the nitrated silicon layer between 200 and 400 Angstroms
M manufacturing method.

According to a third aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein a plasma silicon dioxide layer having an alternate multilayer structure is formed by utilizing a plasma enhanced chemical vapor deposition method. , The thickness of each layer is 200 to 400
Angstrom, a method of manufacturing a stacked DRAM.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein a silicon dioxide layer having an alternating multilayer structure is formed by a low pressure chemical vapor deposition method and an atmospheric pressure chemical vapor deposition method. As a method of manufacturing a stacked DRAM, the layers are formed by using a vapor deposition method, a sub-atmospheric pressure chemical vapor deposition method or another chemical vapor deposition method, and each layer has a thickness of 200 to 400 angstroms. I have.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein a hydrofluoric acid solution is used as a method of forming a cavity.
An AM manufacturing method is used.

According to a sixth aspect of the present invention, there is provided the method of manufacturing a stacked DRAM according to the first aspect, wherein the first polysilicon layer is deposited by using a chemical vapor deposition method and the thickness thereof is reduced to 20.
The manufacturing method of the stacked DRAM is set to be between 00 and 5000 angstroms.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein the capacitor dielectric layer is composed of a silicon oxide nitrated layer, a nitrated silicon layer and a silicon dioxide layer. Alternatively, it is a method of manufacturing a stacked DRAM composed of tantalum pentoxide.

According to an eighth aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein the second polysilicon layer is formed by using a chemical vapor deposition method and the thickness thereof is reduced to 10%.
The manufacturing method of the stacked DRAM is set to be between 00 and 2000 angstroms.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein a rough polysilicon layer is formed before forming a capacitor dielectric layer. Manufacturing method.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The manufacturing method of the present invention is as follows. First, an electric field oxide layer for isolating a field effect transistor is formed on a silicon semiconductor substrate using a conventional local silicon oxide isolation technique (LOCOS). After that, a field effect transistor is formed. Subsequently, an undoped silicon oxide layer (Non-doped Silicat)
e Glass (NSG) and one thin silicon nitride layer.

Thereafter, a thermal chemical vapor deposition method (Therma)
l Chemical VaporDeposition
n) using a first thermal chemical vapor grown silicon dioxide layer (First Thermal-CVD Oxid)
e) and plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition).
A first plasma silicon dioxide layer (Fir) is formed using Vapor Deposition (PECVD).
st PE-Oxide), and sequentially forming a second thermal chemical vapor grown silicon dioxide layer, a second plasma silicon dioxide layer, a third thermal chemical vapor grown silicon dioxide layer, a third plasma silicon dioxide layer and (4) forming a thermochemical vapor-deposited silicon dioxide layer, thereby forming an alternating multilayer structure (Aoternati);
ve Layers).

Subsequently, using a lithography technique and a plasma etching technique, a capacitor region (Capaci) is formed.
etching the above-described alternating multilayer structure and the aforementioned undoped silicon oxide layer to form the memory cell contact of the field effect transistor, ie, the fourth thermochemical vapor grown silicon dioxide layer, the third Plasma silicon dioxide layer, third thermal chemical vapor deposition silicon dioxide layer, second plasma silicon dioxide layer, second thermal chemical vapor deposition silicon dioxide layer, first plasma silicon dioxide layer, first thermal chemical vapor deposition silicon dioxide layer Etching the layer, the nitrated silicon layer and the undoped silicon oxide layer, the plasma etching ending on the silicon semiconductor substrate described above. Thereafter, a lateral etching is performed using a hydrofluoric acid solution, and a part of the above-described fourth thermal chemical vapor deposition silicon dioxide layer, third plasma silicon dioxide layer, and third thermal chemical vapor deposition silicon dioxide Layer, a second plasma silicon dioxide layer, a second thermal chemical vapor deposition silicon dioxide layer, a first plasma silicon dioxide layer, a first
Etch the thermal chemical vapor deposition silicon dioxide layer. Then, since the etching rate of each plasma silicon dioxide layer is higher than that of the thermal chemical vapor deposition silicon dioxide layer, the second thermal silicon dioxide layer between the first thermal chemical vapor deposition silicon dioxide layer and the second thermal chemical vapor deposition silicon dioxide layer has a higher etching rate. Cavity between the chemical vapor grown silicon dioxide layer and the third thermal chemical vapor grown silicon dioxide layer, and between the third thermal chemical vapor grown silicon dioxide layer and the fourth thermal chemical vapor grown silicon dioxide layer Is formed. Later, the lower electrode (Storage Node) of the capacitor is electrically connected to the source electrode of the field effect transistor via the memory cell contact.

Subsequently, a first polysilicon layer (First polysilicon layer)
Polysilicon). The first polysilicon layer is doped (Dope) to have conductivity, and is provided so as to straddle the above-mentioned memory cell contact. Thereafter, the first polysilicon layer is etched in the capacitor region by using a lithography technique and a plasma etching technique to form a lower electrode (Storage Node) of the capacitor. Then, using a hydrofluoric acid solution, an excess of the fourth thermal chemical vapor grown silicon dioxide layer, the third plasma silicon dioxide layer, the third thermal chemical vapor grown silicon dioxide layer, the second plasma silicon dioxide layer, 2 Etch the thermal CVD silicon dioxide layer, the first plasma silicon dioxide layer, and the first thermal CVD silicon dioxide layer. The etching terminates at the surface of the silicon nitride layer described above. Then, a polysilicon layer (Rugged Poly) having a rough surface
silicon), followed by a capacitor dielectric layer and a second polysilicon layer. The second polysilicon layer is doped to have conductivity. Finally, the above-mentioned second polysilicon layer, capacitor dielectric layer and polysilicon layer with a rough surface are etched using lithography and plasma etching techniques, thereby forming a top plate of the capacitor.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. First, the grid direction (10
0) p-type silicon semiconductor substrate 10 (Silicon
Traditional Local Oxidation Isolation Technology (LOCOS) on Semiconductor Substrate
To form an electric field oxide layer 12 for isolating the field effect transistor. The thickness of the above-mentioned electric field oxide layer 12 is 300
From 0 Angstroms to 6000 Angstroms,
Used to isolate metal oxide field effect transistors. After that, a metal oxide field effect transistor is formed. This metal oxide field effect transistor has a gate oxide layer 14 (Gate Oxide) and a gate electrode 16 (Ga
te Electrode), gate electrode spacer 18
(Spacer) and n ^- light doped source electrode 17
A and drain electrode 17B, n ⁺ deeply doped source electrode 1
9A and a drain electrode 19B (see FIG. 1).

Local silicon oxide isolation technology (LOCOS)
About K. See U.S. Patent No. 3,970,486 to Kooi et al. The local silicon oxide isolation technique will be briefly described. First, by thermally oxidizing the p-type silicon semiconductor substrate 10 described above, one silicon dioxide pad layer (Pad Oxide) having a thickness of 2 mm is formed.
Forming between 50 and 550 Å, followed by one layer of nitrated silicon (Nitride) between 600 and 2000 Å thick,
Subsequently, the above-mentioned nitrated silicon pad layer and silicon nitride layer are etched using lithography and plasma etching techniques, and the photoresist pattern is further removed.Then, in a high-temperature environment containing oxygen gas, the above-described nitrated silicon is removed. Using the silicon layer as an oxidation protection mask, a thicker field oxide layer is formed on the semiconductor substrate described above. Its thickness is between 3000 and 6000 angstroms.

Please refer to FIG. 1 again. The above-mentioned gate oxide layer 14 is formed by thermally oxidizing the surface of the above-mentioned p-type silicon semiconductor substrate 10 and has a thickness between 40 and 300 angstroms, and the above-mentioned gate electrode 16 is formed by a low pressure chemical vapor deposition method ( It is made of polysilicon formed by LPCVD) and has a thickness of 2000 to 4000 Å. The above-described n ^- light doped source electrode 17A and drain electrode 17B are formed by using an ion layout technique, the type of the ions is phosphorus atom (P ³¹ ), and the amount of the ion layout agent is 1E13 to 3E14 atoms / cm.
² and the ion layout energy is 20 to 50
kev. The above-mentioned gate electrode spacer 18 is formed by depositing a single undoped silicon oxide layer and then performing vertical unidirectional etching on the undoped silicon oxide layer using a plasma etching technique. The above-described n ⁺ deeply doped source electrode 19A and drain electrode 19B are formed by using an ion layout technique, the kind of the ions is arsenic ion (As ⁷⁵ ), and the amount of the ion layout agent is 1E.
The ion layout energy is between 15 and 5E16 atoms / cm ² and between 40 and 100 keV.

Next, please refer to FIG. Subsequently, one undoped silicon oxide layer 22 and one thin silicon nitrided layer are formed by using low pressure chemical vapor deposition. This nitrated silicon layer is not shown in the figure. Thereafter, a first thermal chemical vapor deposition silicon dioxide layer 24 is formed by using a thermal chemical vapor deposition method, and a first plasma silicon dioxide layer is further formed by using a plasma enhanced chemical vapor deposition method. A layer 26 is formed. Further successively, the second thermal chemical vapor deposition silicon dioxide layer 28, the second plasma silicon dioxide layer 30, the third thermal chemical vapor deposition silicon dioxide layer 32, the third plasma silicon dioxide layer 34, and the fourth thermal chemical vapor A phase grown silicon dioxide layer 36 is formed, thereby forming an alternating multilayer structure. The above is as shown in FIG.

The above-mentioned undoped silicon oxide layer 22 is usually formed by using a low-pressure chemical vapor deposition method, and its reaction gas is tetraethoxysilane (TetraEthO).
xySilane; TEOS) and the reaction temperature is about 72
At 0 ° C., the reaction pressure is between 0.1 and 1.0 torr and its thickness is between 1000 and 3000 Å. The above-mentioned nitrated silicon layer is also formed by low-pressure chemical vapor deposition, and the reaction gases are SiH ₂ Cl ₂ and NH ₃ ,
The reaction temperature is about 720 ° C., and the reaction pressure is 0.2 to 0.5.
4 torr, and its thickness is 200 to 400 angstroms. The formation of each plasma silicon dioxide layer by the above-mentioned plasma-enhanced chemical vapor deposition method is performed by using a reaction gas Si
H ₄ and N ₂ O proceed at a reaction temperature of 300 to 400 ° C. In addition, the formation of each thermal chemical vapor deposition silicon dioxide layer using the low pressure chemical vapor deposition method described above is performed by using a reactive gas SiH _2.
Cl ₂ and N ₂ O, or SiH ₄ and N ₂ O, reaction temperature 7
Proceed at 50-900 ° C. The first plasma silicon dioxide layer 26 described above is formed. Further successively, a second thermal chemical vapor deposition silicon dioxide layer 28, a second plasma silicon dioxide layer 30, a third thermal chemical vapor deposition silicon dioxide layer 32,
The thickness of each layer of the alternating multilayer structure consisting of the third plasma silicon dioxide layer 34 and the fourth thermal chemical vapor deposition silicon dioxide layer 36 is between 200 and 400 angstroms.
Etching selectivity of plasma silicon dioxide layer and thermochemical vapor deposition silicon dioxide layer in hydrofluoric acid solution (Etc
h Selectivity) is approximately 4 to 1, ie, the etch rate of the plasma silicon dioxide layer described above is faster than the etch rate of the thermal chemical vapor grown silicon dioxide layer.
As a method for forming the above-mentioned thermal chemical vapor deposition silicon dioxide layer, low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), and sub-atmospheric pressure chemical vapor deposition (Sub-Atomsphere). Chemical
Vapor Deposition (SACVD) or other various chemical vapor deposition methods can be used.

Next, please refer to FIG. Next, the aforementioned alternate multilayer structure, the thin silicon nitride layer, and the undoped silicon oxide layer 22 in the aforementioned capacitor region are etched using lithography and plasma etching techniques to form the memory cell contact 3 of the field effect transistor.
7 (Cell Contact), that is,
The above-described fourth thermal chemical vapor deposition silicon dioxide layer 36, third plasma silicon dioxide layer 34, third thermal chemical vapor deposition silicon dioxide layer 32, second plasma silicon dioxide layer 30,
Thermochemical vapor grown silicon dioxide layer 28, first plasma silicon dioxide layer 26, first thermochemical vapor grown silicon dioxide layer 2
4. Etch the silicon nitride layer and the undoped silicon oxide layer 22, ending at the n ⁺ deeply doped source and drain surfaces 19A and 19B described above. The above is as shown in FIG.

Next, please refer to FIG. Lateral etching with buffered hydrofluoric acid solution (Lateral Etc
h), a part of the above-mentioned fourth thermal chemical vapor deposition silicon dioxide layer 36, third plasma silicon dioxide layer 34, third thermal chemical vapor deposition silicon dioxide layer 32, second plasma silicon dioxide layer 30, Second thermal chemical vapor deposition silicon dioxide layer 2
8. Etch the first plasma silicon dioxide layer 26 and the first thermal chemical vapor deposition silicon dioxide layer 24. Since the etch rate of the plasma silicon dioxide layer described above is faster than that of the thermal silicon dioxide layer, the first silicon dioxide layer 24 and the second silicon dioxide layer 28 During the second thermal chemical vapor deposition silicon dioxide layer 28 and the third thermal chemical vapor deposited silicon dioxide layer 32, between the third thermal chemical vapor deposited silicon dioxide layer 32 and the fourth thermal chemical vapor deposited silicon dioxide layer 32. A cavity 38 is formed between the layers 36. This is as shown in FIG. Later, the lower electrode of the capacitor is brought into electrical contact with the aforementioned n ⁺ deeply doped source electrode 19A of the aforementioned field effect transistor through the aforementioned memory cell contact 37.

The above-described fourth thermal chemical vapor deposition silicon dioxide layer 36, third plasma silicon dioxide layer 34, third thermal chemical vapor deposition silicon dioxide layer 32, second plasma silicon dioxide layer 30, second thermal chemical vapor Phase grown silicon dioxide layer 38, first
Plasma etching of the plasma silicon dioxide layer 26, the first thermal chemical vapor deposition silicon dioxide layer 24, the nitrated silicon layer and the undoped silicon oxide layer 22 generally comprises:
Magnetic field enhanced active ion plasma etching (Magn
etic Enhanced Reactive Io
n Etching (MERIE) or traditional active ion plasma etching (RIE), and the plasma reaction gas generally uses a fluoride gas such as CF ₄ and CHF ₃ .

After forming the wrinkled side walls as described above, the first polysilicon layer is formed by using a standard process. The first polysilicon layer is doped to have conductivity, and is provided so as to fill the cavity 38 and straddle the memory cell contact 37 to form the first polysilicon layer. It is electrically connected to the n ⁺ deeply doped source electrode 19A. Thereafter, the first polysilicon layer is etched in the capacitor region using lithography technology and plasma etching technology, thereby forming a lower electrode (Sto) of the capacitor.
(Region Node). The above-mentioned first polysilicon layer is usually formed by using a low-pressure chemical vapor deposition method and performing an in-situ doped method. The reaction impurities at this time were phosphorus atoms, the reaction gas was a mixed gas of PH ₃ and SiH ₄ , and the reaction temperature was 52
Between 5 and 575 ° C., its thickness is 1000 to 2500
Angstrom. The above-described plasma etching of the first polysilicon layer generally uses a magnetic field-enhanced active ion plasma etching (MERIE),
Generally, a halogen group gas such as SF ₆ and HBr is used as the plasma reaction gas.

Thereafter, using the buffered hydrofluoric acid solution, a surplus of the above-mentioned fourth thermochemical vapor deposition silicon dioxide layer 36,
Third plasma silicon dioxide layer 34, third thermal chemical vapor deposition silicon dioxide layer 32, second plasma silicon dioxide layer 3
0, etch second thermal chemical vapor grown silicon dioxide layer 28, first plasma silicon dioxide layer 26, first thermal chemical vapor grown silicon dioxide layer 24; This etching terminates at the surface of the nitrated silicon layer 22. Subsequently, using a standard fabrication process, one rough surface polysilicon layer is deposited, and a capacitor dielectric layer and a second polysilicon layer are deposited. The above-mentioned rough-surface polysilicon layer and the second polysilicon layer are doped to have conductivity.

Finally, the second polysilicon layer, the capacitor dielectric layer and the polysilicon layer having a rough surface are etched by using a lithography technique and a plasma etching technique, thereby forming a top layer electrode (Top Plate) of the capacitor.
e) is formed, and thus, a method of manufacturing a stacked capacitor having a high capacitance and a high integration density stacked DRAM is completed.

The polysilicon layer having a rough surface is formed by using a chemical vapor deposition method, and has a thickness of 300 to 10
00 angstrom. The capacitor dielectric layer described above is typically a silicon dioxide layer (Silicon Dio).
xide; O), nitrated silicon layer (Silicon)
Nitride; N) and a nitrated silicon oxide layer (Oxy
nitride) (O). The silicon dioxide layer described above is formed by thermally oxidizing a rough surface polysilicon layer,
Its thickness is between 50 and 200 angstroms. The above-mentioned nitrated silicon layer is formed by low pressure chemical vapor deposition,
Its thickness is between 40 and 60 angstroms. The above-mentioned silicon oxide nitrated layer is formed by oxidizing the above-mentioned silicon nitride layer, and has a thickness of 20 to 50 angstroms. The above-mentioned second polysilicon layer is usually formed by using a low-pressure chemical vapor deposition method as well as by synchronously doping (In-si
tu Doped), the reaction impurity atom is a phosphorus atom, the reaction gas is a mixed gas of PH ₃ and SiH ₄ , the reaction temperature is between 525 and 575 ° C., and the thickness is 1000 to 2000 Å. And
The capacitor dielectric layer described above is made of tantalum pentoxide (Ta ₂ O).
₅ ) may be used as a material.

[0033]

The present invention provides an alternating multilayer structure of a plasma enhanced silicon dioxide layer formed by plasma enhanced chemical vapor deposition and a thermochemical vapor grown silicon dioxide layer formed by thermal chemical vapor deposition. By forming a wrinkled oxide side wall above the memory cell contact and increasing the surface area of the lower electrode of the capacitor, the capacitance of the capacitor is greatly increased. Application to the manufacture of high-density stacked DRAMs of megabits or more greatly contributes to the high density of stacked DRAMs.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing process according to the embodiment of the present invention.

[Explanation of symbols]

10 p-type silicon semiconductor substrate 12 field oxide layer 14 gate oxide layer 16 gate electrode 18 gate electrode spacers 17A n ^- lightly doped source electrode 17B n ^- lightly doped drain electrode 19A n ⁺ deep doped source electrode 19B n ⁺ deep doped drain electrode 22 Undoped silicon oxide layer 24 First thermal chemical vapor deposition silicon dioxide layer 26 First plasma silicon dioxide layer 28 Second thermal chemical vapor deposition silicon dioxide layer 30 Second plasma silicon dioxide layer 32 Third thermal chemical vapor deposition dioxide Silicon layer 34 Third plasma silicon dioxide layer 36 Fourth thermochemical vapor deposition silicon dioxide layer 37 Memory cell contact 38 Void

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (9)

(57) [Claims] 1. A type of stacked DRAM (Stack DRAM)
And a method of manufacturing a semiconductor device (Silicon Semiconductor).
An oxide layer (Oxide) used for isolating the field effect transistor is formed on the dielectric substrate using a local silicon oxide isolation technique (LOCOS), and a gate oxide layer, a gate electrode, and a source electrode and a drain electrode are formed. Including a field effect transistor and a word line (Word)
Lines), forming one dielectric layer, and forming an alternating multilayer structure composed of a thermal chemical vapor grown silicon dioxide layer deposited by a thermal chemical vapor deposition method and a plasma silicon dioxide layer (Alternative Layers). Then, the lithography technique and the etching technique are used to etch the alternate multilayer structure and the dielectric layer to expose the source electrode, thereby forming a memory cell contact (Cell Contact) of the field effect transistor. Direction etching to remove some of the above-mentioned plasma silicon dioxide layer and thermal chemical vapor deposition silicon dioxide layer, and to form a cavity between the thermal chemical vapor deposition silicon dioxide layer and the thermal chemical vapor deposition silicon dioxide layer. (Cavity) to form a corrugated side wall (Corrugated Side).
wall), a first polysilicon layer is formed, the first polysilicon layer is filled with the above-mentioned cavity, and the memory cell contact is straddled, and a lithography technique and an etching technique are used. By etching the first polysilicon layer in the capacitor region, the lower electrode (Storage N) of the capacitor is formed.
mode) and a capacitor dielectric layer (Capacitor Dielec).
tric), a second polysilicon layer is formed, and the second polysilicon layer and the capacitor dielectric layer are etched using a lithography technique and an etching technique to form an upper electrode (Top Plate) of the capacitor. Manufacturing method of stacked DRAM. 2. The method according to claim 1, wherein the dielectric layer comprises an undoped silicon oxide layer and a nitrated silicon layer, wherein the thickness of the undoped silicon oxide is from 1000. A method of manufacturing a stacked DRAM, wherein the thickness is between 3000 Angstroms and the thickness of the nitrated silicon layer is between 200 and 400 Angstroms. 3. The method of claim 1, wherein the plasma silicon dioxide layer having an alternate multilayer structure is formed using a plasma enhanced chemical vapor deposition method, and the thickness of each layer is changed. A method for manufacturing a stacked DRAM having a thickness of 200 to 400 angstroms. 4. The method according to claim 1, wherein the alternately multi-layered thermal chemical vapor deposition silicon dioxide layer is formed by low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, Alternatively, it is formed using the next atmospheric pressure chemical vapor deposition method or another chemical vapor deposition method, and the thickness of each layer is 200
Between 400 and 400 angstroms, stack DR
Manufacturing method of AM. 5. The method for manufacturing a stacked DRAM according to claim 1, wherein a hydrofluoric acid solution is used as a method for forming a cavity. 6. The method of claim 1, wherein the first polysilicon layer is deposited by using a chemical vapor deposition method, and has a thickness of 2,000 to 5,000.
A method for manufacturing a stacked DRAM, which is performed between angstrom. 7. The method of claim 1, wherein the capacitor dielectric layer comprises a silicon oxide nitrate layer, a silicon nitride layer and a silicon dioxide layer, or tantalum pentoxide. A method for manufacturing a stacked DRAM. 8. The method of claim 1, wherein the second polysilicon layer is formed using a chemical vapor deposition method, and has a thickness of 1000 to 2000.
A method for manufacturing a stacked DRAM, which is performed between angstrom. 9. The method of claim 1, wherein the step of forming the capacitor dielectric layer comprises:
A method for manufacturing a stacked DRAM, wherein a polysilicon layer having a rough surface is formed.