JP2898927B2 - Method for manufacturing high-density stacked DRAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DRA for an integrated circuit.
M (Dynamic Random Access M)
manufacturing method, in particular, a stacked DRAM
(Stack DRAM).

[0002]

2. Description of the Related Art A typical stacked DRAM includes a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor) on a silicon semiconductor wafer.
actor Field Effect Transi
MOSFET) and a capacitor, and are connected to a lower electrode (Storage Node) of the capacitor using the source electrode of the above-mentioned field effect transistor, thereby forming a DRAM memory cell (Memory C).
ell), and a huge number of memory cells were assembled to form a memory integrated circuit.

In recent years, the integration density of DRAMs (Pac
(King Density) is increasing rapidly, and the memory cell size is already 6 to 1.5 square microns.
Those with 14 million bits are mass-produced. At NEC Corporation (NEC), a Japanese semiconductor manufacturer, 199
It has announced that it has already developed a 1 Gigabit DRAM prototype in 5 years.

In order to achieve the purpose of high integration of DRAM, it is necessary to reduce the size of memory cells, which means that the size of field effect transistors and capacitors must be reduced. However, when the size of the capacitor is reduced, the capacitance value becomes lower, the ratio of signal to noise (Signal Noise; S / N) of the memory circuit becomes lower, and the disadvantages such as erroneous disconnection of the electric circuit or instability of the electric circuit are mimicked. Was.

As a structure for maintaining or increasing the capacitance value of the capacitor when reducing the size of the capacitor, Masao Taguch of Fujitsu Limited of Japan is used.
The structure of a fin type capacitor disclosed in U.S. Pat. No. 5,021,357 by Ii et al. is the most typical, but the fin type capacitor has the following disadvantages. The first is that the lower electrode has a relatively weak structure because the fins on both sides are connected to different polysilicon, and the second is that the lower electrode has a relatively sharp geometrical shape. This means that local collapse of the capacitor dielectric layer was likely to occur at the edge (Edge).

[0006]

SUMMARY OF THE INVENTION The main object of the present invention is to:
Stack Capacitor (Stack Capa)
(Citor) manufacturing method.

Another object of the present invention is to provide a method of manufacturing a high density stacked DRAM.

[0008]

The invention of claim 1 is a kind of a method for manufacturing a stacked DRAM, and includes a method of manufacturing a silicon semiconductor substrate (Silicon Semiconductor).
Substrate, trench isolation (Tren)
A field effect transistor including a gate oxide layer, a gate electrode, a source electrode, and a drain electrode is used to form a field oxide transistor (Oxide) using a channel isolation (Oxide) technique. Word Line), one dielectric layer is formed, and a silicon dioxide layer deposited by a thermal chemical vapor deposition method and a plasma silicon dioxide layer are alternately deposited to form a multilayer structure. Vertical unidirectional etching is performed on the multilayer structure and the dielectric layer using the technology and the plasma etching technology, and by exposing the source electrode, the memory cell contact of the field effect transistor is formed. By performing lateral etching on the multilayer structure of the above, and forming a cavity between the layers of the thermal chemical vapor deposition silicon dioxide. Oxide layer sidewall having wrinkles (Corr
lithography technology and plasma etching technology, forming a first polysilicon layer, filling the first polysilicon layer with the above-described wrinkled oxide layer side walls, and straddling a memory cell contact. Forming the lower electrode (Storage Node) of the capacitor, forming one capacitor dielectric layer, and forming one second polysilicon layer by etching the first polysilicon layer in the capacitor region using Stack D formed by etching the above-mentioned second polysilicon layer and capacitor dielectric layer using lithography technology and plasma etching technology to form a capacitor upper electrode (Top Plate).
This is a method for manufacturing a RAM.

According to a second aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein the dielectric layer refers to a silicon nitride layer and has a thickness of 500 to 1500 angstroms. Manufacturing method.

According to a third aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein the plasma silicon dioxide having a multilayer structure alternately deposited is a plasma enhanced chemical vapor deposition method. And the thickness of each layer is 20
Stack DRA from 0 to 400 angstroms
M manufacturing method.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein the thermal chemical vapor deposition silicon dioxide layer having a multilayer structure alternately deposited is formed by a low pressure chemical vapor deposition. The stacked DRAM is formed by using a growth method, an atmospheric pressure chemical vapor deposition method, a sub-atmospheric pressure chemical vapor deposition method or another chemical vapor deposition method, and each layer has a thickness of 200 to 400 angstroms. Manufacturing method.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein a hydrofluoric acid solution is used as a method of forming a cavity.
M manufacturing method.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein the first polysilicon layer is formed by using a chemical vapor deposition method and has a thickness of 20 nm.
Stack D from 00 to 5000 Angstroms
This is a method for manufacturing a RAM.

According to a seventh aspect of the invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein the capacitor dielectric layer comprises a silicon oxide nitrated layer, a nitrated silicon layer and a silicon dioxide layer, or This is a method for manufacturing a stacked DRAM made of tantalum pentoxide.

According to an eighth aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein the second polysilicon layer is formed by using a chemical vapor deposition method and has a thickness of 10 nm.
Stack D from 2000 to 2000 angstroms
This is a method for manufacturing a RAM.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein a polysilicon layer having a rough surface is formed before forming a capacitor dielectric layer. Manufacturing method.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The manufacturing method of the present invention is as follows. First, a shallow trench isolation (Shallow Trench Isola) is formed on a silicon semiconductor substrate.
forming an electric field oxide layer for isolating the field effect transistor using a technique, and then forming the field effect transistor. Subsequently, a single layer of nitrated silicon (Si
Silicon nitride).

Thereafter, a thermal chemical vapor deposition method (Therma)
l Chemical VaporDeposition
n), a first thermal chemical vapor-deposited silicon dioxide (First Thermal CVD Oxid)
e) forming a layer and further plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical)
A first plasma silicon dioxide layer (Firs) using Vapor Deposition (PECVD).
t PE-Oxide) and further successively form a second thermal chemical vapor grown silicon dioxide layer, a second plasma silicon dioxide layer, a third thermal chemical vapor grown silicon dioxide layer, and a third plasma silicon dioxide layer. Formed, and the alternate multilayer structure (A
Oternative Layers).

Subsequently, a capacitor region (Capaci) is formed by using lithography technology and plasma etching technology.
The aforementioned alternating multilayer structure of the torsion region and the above-mentioned silicon nitride layer are etched, so that the memory cell contact (Cell Conta) of the field effect transistor is formed.
ct), i.e., the third plasma silicon dioxide layer, the third thermal chemical vapor deposition silicon dioxide layer, the second plasma silicon dioxide layer, the second thermal chemical vapor deposition silicon dioxide layer, the first plasma silicon dioxide layer. The silicon layer, the first thermal chemical vapor deposition silicon dioxide layer, and the silicon nitride layer are etched to complete the plasma etching on the surface of the silicon semiconductor wafer. Thereafter, a lateral etching is performed with a hydrofluoric acid solution, and the first plasma silicon dioxide layer, the first thermal chemical vapor deposition silicon dioxide layer, the second plasma silicon dioxide layer, and the second thermal chemical vapor deposition When the silicon layer, the third plasma silicon dioxide layer, and the third thermochemical vapor deposition silicon dioxide layer are removed, the etching rate of the above plasma silicon dioxide is faster than that of the thermochemical vapor deposition silicon dioxide. Cavity between the CVD silicon dioxide layer and the second thermal CVD silicon dioxide layer, and between the second and third thermal CVD silicon dioxide layers. Is formed, and the oxide layer side wall (Corrugated Oxide Sid) having wrinkles is formed.
ewall) is formed. Later, the lower electrode (Storage Node) of the capacitor is electrically connected to the source electrode of the above-mentioned field effect transistor via the above-mentioned memory cell contact.

Subsequently, a first polysilicon layer (First polysilicon layer)
Polysilicon). The first polysilicon layer is doped (Dope) and has conductivity, and is provided so as to straddle the above-described memory cell contact. After that, the capacitor region is etched using a lithography technique and a plasma etching technique to remove the first polysilicon layer, thereby forming a lower electrode (Storage Node) of the capacitor. Then, using a buffered hydrofluoric acid solution, the excess third plasma silicon dioxide layer, third thermal chemical vapor deposition silicon dioxide layer, second plasma silicon dioxide layer,
Etch the thermal CVD silicon dioxide layer, the first plasma silicon dioxide layer, and the first thermal CVD silicon dioxide layer. This etching terminates at the surface of the nitrated silicon layer. Thereafter, a polysilicon layer having a rough surface (Ru
gced Polysilicon, and a capacitor dielectric layer and a second polysilicon layer (Second).
Surface Polysilicon is deposited, and the second polysilicon layer is doped to have conductivity. Finally, the second polysilicon layer, the capacitor dielectric layer, and the polysilicon layer having a rough surface are etched by using a lithography technique and a plasma etching technique, thereby forming an upper electrode (Top Plate) of the capacitor.
e) is formed.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. First, the grid direction (10
0) p-type silicon semiconductor substrate 10 (Silicon
On the Semiconductor Substrate, a standard shallow trench isolation (Shallow Tr)
The field oxide layer 12 for isolating the field effect transistor is formed using an etch isolation technique.
The thickness of the field oxide layer 12 described above is between 4000 Angstroms and 10000 Angstroms and is used to isolate metal oxide field effect transistors. You. afterwards,
Form a metal oxide field effect transistor. This metal oxide field effect transistor has a gate oxide layer 14 (Ga
te Oxide), gate electrode 16 (Gate Ele)
cpole), the gate electrode spacer 18 (Space)
r), n ^- light doped source electrode 17A or drain electrode 17B, and n ⁺ deeply doped source pole 19A or drain pole 19B. See US Pat. No. 5,231,046 to Takata et al. For shallow trench isolation.

Please refer to FIG. The gate oxide layer 14 is formed by thermally oxidizing the surface of the p-type silicon semiconductor substrate 10 and has a thickness between 40 and 300 angstroms, and the gate electrode 16 is formed by low pressure chemical vapor deposition (LPCVD). ), And has a thickness of 2,000 to 4,000 angstroms. The above-described n ^- light doped source electrode 17A or drain electrode 17B is formed by using an ion layout technique, the type of the ions is phosphorus atom (P ³¹ ), and the amount of the ion layout agent is 1E13 to 3E14 atoms / cm.
² and the ion layout energy is 20 to 50
kev. The above-described gate electrode spacer 18 is formed by depositing a layer of undoped silicon dioxide and then performing a vertical unidirectional etching on the undoped silicon dioxide using a plasma etching technique. The above-described n ⁺ deeply doped source electrode 19A or drain electrode 19B is also formed by ion layout technology, the ion type is arsenic ion (As ⁷⁵ ), the ion layout agent amount is 1E15 to 5E16 atoms / cm ² , and the ion layout is Energy amount from 40 to 100k
ev.

Next, please refer to FIG. Subsequently, one layer of the nitrated silicon layer 22 is formed by low pressure chemical vapor deposition.
(Silicon Nitride). Thereafter, a first thermal chemical vapor deposition silicon dioxide layer 24 is formed using a chemical vapor deposition method, and further, a plasma enhanced chemical vapor deposition method (Plasma Enhanced Ch) is used.
electronic Vapor Deposition; P
A first plasma silicon dioxide layer 26 (First PE-Oxide) is formed using ECVD, and a second thermochemical vapor deposition silicon dioxide layer 2 is continuously formed.
8, forming a second plasma silicon dioxide layer 30, a third thermal chemical vapor deposition silicon dioxide layer 32, and a third plasma silicon dioxide layer 34, thereby forming an alternating multilayer structure (Aoternati).
ve Layers). This is as shown in FIG.

The above-mentioned nitrated silicon layer 22 is formed by using a low-pressure chemical vapor deposition method.
H ₂ Cl ₂ and NH ₃ , the reaction temperature is about 720 ° C.,
The reaction pressure is between 0.2 and 0.4 torr and its thickness is between 500 and 1500 angstroms. The formation of each plasma silicon dioxide layer using the above-mentioned plasma-enhanced chemical vapor deposition method is performed by using reactive gases SiH ₄ and N ₂ O,
The reaction is performed at a reaction temperature of 300 to 400 ° C. In addition, the formation of each thermal chemical vapor deposition silicon dioxide layer using the low pressure chemical vapor deposition method described above is performed by using a reaction gas of SiH ₂ Cl ₂ and N ₂ O,
Alternatively, SiH ₄ and N ₂ O, reaction temperature 750 to 900 ° C.
With The above-described first thermal CVD silicon dioxide layer 24, first plasma silicon dioxide layer 26, second thermal CVD silicon dioxide layer 28, second plasma silicon dioxide layer 30, third thermal CVD silicon dioxide layer Silicon layer 32, third
The thickness of each layer of the multilayer structure of the plasma silicon dioxide layer 34 is 200 to 400 angstroms. In a hydrofluoric acid solution, the etching selectivity of each of the above-mentioned plasma silicon dioxide layers and the thermal chemical vapor deposition silicon dioxide layer (Etch)
Selectivity) is approximately 4 to 1, ie, the etch rate of the plasma silicon dioxide layer described above is faster than the etch rate of the thermal chemical vapor grown silicon dioxide layer.
As a method of forming the silicon dioxide layer by thermal chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition (A
PCVD) or sub-atmospheric pressure chemical vapor deposition (Sub-
Atomsphere Chemical Vapor
Deposition (SACVD) or other various chemical vapor deposition methods can be used.

Next, please refer to FIG. Subsequently, the above-mentioned alternate multilayer structure in the capacitor region and the above-mentioned silicon nitride layer 22 are etched by using a lithography technique and a plasma etching technique, so that the memory cell contact 35 (Cell Contact) of the field effect transistor is etched. ), Ie, the third plasma silicon dioxide layer 34, the third thermal chemical vapor grown silicon dioxide layer 32, the second plasma silicon dioxide layer 30, the second thermal chemical vapor grown silicon dioxide layer 28,
The first plasma silicon dioxide layer 26, the first thermal chemical vapor deposition silicon dioxide layer 24, and the nitrated silicon layer 22 are etched, and the plasma etch is terminated at the surface of the n ⁺ deeply doped source pole 19A. The above is as shown in FIG.

Next, please refer to FIG. After that, lateral etching (Later) with a hydrofluoric acid solution (HF) is performed.
al Etch), and a part of the above-mentioned third plasma silicon dioxide layer 34, third thermal chemical vapor deposition silicon dioxide layer 32, second plasma silicon dioxide layer 30, and second thermal chemical vapor deposition silicon dioxide layer 28. When the first plasma silicon dioxide layer 26 and the first thermal chemical vapor grown silicon dioxide layer 24 are etched, the etching rate of each plasma silicon dioxide layer is faster than that of the thermal chemical vapor grown silicon dioxide layer. 2 Thermochemical vapor deposition silicon dioxide layer 28 and first
A cavity 37 (Cavity) is formed between the thermal chemical vapor grown silicon dioxide layer 26 and between the third thermal chemical vapor grown silicon dioxide layer 32 and the second thermal chemical vapor grown silicon dioxide layer 30, Wrinkled oxide layer sidewall (Corrugat)
ed Oxide Sidewall) is formed.
The above is as shown in FIG. Thereafter, the lower electrode (Storage Node) of the capacitor is electrically connected to the n ⁺ deeply doped source electrode 19A of the field effect transistor via the memory cell contact 35 described above.

Usually, the characteristics of the plasma silicon dioxide thin film can be modified by adjusting the electrode spacing, the reaction pressure and the firing frequency of the plasma deposition reaction chamber, and further the etching rate in the hydrofluoric acid solution can be modified. Can be. The above-mentioned third plasma silicon dioxide layer 34, third thermal chemical vapor deposition silicon dioxide layer 32, second plasma silicon dioxide layer 3
0, the second thermal chemical vapor grown silicon dioxide layer 28, the first plasma silicon dioxide layer 26, the first thermal chemical vapor grown silicon dioxide layer 24, and the plasma etching of the nitrated silicon layer 22 are generally performed using a magnetic field enhanced method. Active ion plasma etching (Magnetic Enhanced Re)
active Ion Etching; MERIE)
Alternatively, traditional active ion plasma etching (RI
E) can also be used, and the plasma reactant gas is generally CF
₄ and a fluoride gas such as CHF ₃ are used.

After the formation of the above-described wrinkled oxide sidewalls, a capacitor is formed using the standard process described below. First, a first polysilicon layer (Firs
t Polysilicon). The first polysilicon layer is doped (Dope) to have conductivity, and fills the above-mentioned cavity 37, and is provided so as to straddle the above-mentioned memory cell contact 35, so that the above-mentioned field effect transistor Is electrically connected to the n ⁺ deeply doped source electrode 19A. Thereafter, the above-mentioned capacitor region is etched using lithography technology and plasma etching technology to remove the above-mentioned first polysilicon layer, thereby forming a lower electrode (Storage) of the capacitor.
Node). For the above-mentioned plasma etching of the first polysilicon layer, generally, a magnetic field enhanced active ion plasma etching (MERIE) can be used, and the plasma reaction gas generally uses a halogenated gas such as SF ₆ and HBr. Then, using the buffered hydrofluoric acid solution, the excess third plasma silicon dioxide layer 3
4. Third thermal silicon dioxide layer 32, second plasma silicon dioxide layer 30, second thermal silicon dioxide layer 28, first plasma silicon dioxide layer 26, first thermal silicon dioxide layer The silicon layer 24 is etched. The etching terminates at the nitrated silicon layer surface 22.
Then, using a standard process, one roughened polysilicon layer (Rugged Polysilico) is formed.
n), a capacitor dielectric layer and a second polysilicon layer (Sec.)
on Surface Polysilicon, and etching the second polysilicon layer, the capacitor dielectric layer, and the rough polysilicon layer using lithography and plasma etching techniques, thereby forming a top plate of the capacitor (Top Plate). )
Thus, a stacked capacitor having a high capacitance and a stacked DRAM having a high integration density are completed.

The above-mentioned rough polysilicon layer is formed by using a chemical vapor deposition method, and has a thickness of 300 to 10
00 angstrom. The capacitor dielectric layer described above is typically a silicon dioxide layer (Silicon Di).
oxide; O), a nitrated silicon layer (Silicon)
Nitride; N) and a silicon oxide nitrated layer (Ox
ynitride; O). The above-mentioned silicon dioxide layer is formed by thermally oxidizing a rough surface polysilicon layer, and has a thickness of 50 to 200 angstroms. The above-mentioned silicon nitride layer is formed by low pressure chemical vapor deposition and has a thickness of 40 to 60 angstroms. The above-mentioned silicon oxide nitrated layer is formed by oxidizing the above-mentioned silicon nitride layer, and has a thickness of 20 to 50 angstroms. The above-mentioned second polysilicon layer is usually formed by using a low-pressure chemical vapor deposition method, and is formed by a synchronous doping method (In-situ Doped).
The reaction impurity atom is a phosphorus atom, and the reaction gas is PH.
₃ and a mixed gas of SiH ₄ , and the reaction temperature is 525 to 5
75 ° C. and its thickness is 1000 to 2000 Å. The above-described capacitor dielectric layer 46 can be made of tantalum pentoxide (Ta ₂ O ₅ ).

[0030]

The present invention provides an alternating multilayer structure of a plasma enhanced silicon dioxide layer formed by plasma enhanced chemical vapor deposition and a thermochemical vapor grown silicon dioxide layer formed by thermal chemical vapor deposition. By forming a wrinkled oxide side wall above the memory cell contact and increasing the surface area of the lower electrode of the capacitor, the capacitance of the capacitor is greatly increased. Application to the manufacture of high-density stacked DRAMs of megabits or more greatly contributes to the high density of stacked DRAMs.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing process according to the embodiment of the present invention.

[Explanation of symbols]

10 p-type silicon semiconductor substrate 12 field oxide layer 14 gate oxide layer 16 gate electrode 18 gate electrode spacers 17A n ^- lightly doped source electrode 17B n ^- lightly doped drain electrode 19A n ⁺ deep doped source electrode 19B n ⁺ deep doped drain electrode 22 Silicon nitride layer 24 first thermal chemical vapor grown silicon dioxide layer 26 first plasma silicon dioxide layer 28 second thermal chemical vapor grown silicon dioxide layer 30 second plasma silicon dioxide layer 32 third thermal chemical vapor grown silicon dioxide layer Layer 34 third plasma silicon dioxide layer 35 memory cell contact 37 cavity

Continuation of front page (56) References JP-A-4-340270 (JP, A) JP-A-8-236725 (JP, A) JP-A-8-222710 (JP, A) JP-A-6-318680 (JP) JP-A-56-147451 (JP, A) JP-A-7-307395 (JP, A) JP-A-6-1511763 (JP, A) JP-A-10-125870 (JP, A) (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (9)

(57) [Claims] 1. A method of manufacturing a stacked DRAM, comprising: a silicon semiconductor substrate (Silicon Semiconductor)
A field oxide transistor is formed on the substrate substrate using a trench isolation technique by using a trench isolation technique, and is used to isolate a field effect transistor. A gate oxide layer, a gate electrode, a source electrode, and a drain electrode are used. Including a field effect transistor and a word line (Word L)
ine), a dielectric layer is formed, and a silicon dioxide layer deposited by a thermal chemical vapor deposition method and a plasma silicon dioxide layer are alternately deposited to form a multilayer structure. By performing vertical unidirectional etching on the multilayer structure and the dielectric layer using the plasma etching technique and exposing the source electrode, a memory cell contact of a field effect transistor is formed, and Sidewall etching is performed on the multilayer structure to form voids between the layers of the thermal chemical vapor deposition silicon dioxide, thereby forming a wrinkled oxide sidewall (Corrugated S).
idewall), forming a first polysilicon layer, filling the first polysilicon layer with the above-described wrinkled oxide layer sidewalls, straddling a memory cell contact, and using lithography and plasma etching techniques. And etching the first polysilicon layer in the capacitor region to form a lower electrode (Storage) of the capacitor.
Ge Node), one capacitor dielectric layer is formed, one second polysilicon layer is formed, and the above-mentioned second polysilicon layer and capacitor dielectric layer are etched using lithography and plasma etching techniques. Therefore, the upper electrode of the capacitor (Top
(Plate) is formed. 2. The method of claim 1, wherein the dielectric layer is a nitrated silicon layer and has a thickness of 500 to 1500 angstroms. 3. The method for manufacturing a stacked DRAM according to claim 1, wherein the multi-layer plasma silicon dioxide alternately deposited is formed by a plasma enhanced chemical vapor deposition method. A method for manufacturing a stacked DRAM, wherein each layer has a thickness of 200 to 400 Å. 4. The method for manufacturing a stacked DRAM according to claim 1, wherein the silicon dioxide layer having a multi-layer structure, which is alternately deposited, is formed by low pressure chemical vapor deposition or atmospheric pressure. A method of manufacturing a stacked DRAM, wherein the stacked layers are formed by using a chemical vapor deposition method, a sub-atmospheric pressure chemical vapor deposition method or another chemical vapor deposition method, and each layer has a thickness of 200 to 400 angstroms. 5. The method for manufacturing a stacked DRAM according to claim 1, wherein a hydrofluoric acid solution is used as a method for forming a cavity. 6. The method of claim 1, wherein the first polysilicon layer is formed using a chemical vapor deposition method, and has a thickness of 2,000 to 5,000.
A method for manufacturing a stacked DRAM having an angle of Å. 7. The method of claim 1, wherein the capacitor dielectric layer comprises a silicon oxide nitrate layer, a silicon nitride layer and a silicon dioxide layer, or a ditantalum pentoxide layer. A method for manufacturing a stacked DRAM. 8. The method of claim 1, wherein the second polysilicon layer is formed using a chemical vapor deposition method, and has a thickness of 1000 to 2000.
A method for manufacturing a stacked DRAM having an angle of Å. 9. The method of claim 1, wherein the step of forming the capacitor dielectric layer comprises:
A method of manufacturing a stacked DRAM, wherein a polysilicon layer having a rough surface is formed.