TW314647B - Manufacturing method of memory with decreased memory cell layout area - Google Patents

Abstract

A method of forming polysilicon structure of integrated circuit comprises of the following steps: (1) on semiconductor wafer forming first dielectric, second dielectric and third dielectric, and planarizing the above second dielectric; (2) by lithography and etch technique etching the above first dielectric, second dielectric and third dielectric to form hole; (3) forming one first polysilicon, which filling the above hole; (4) by etch technique conducting etchback to the above first polysilicon, in which the above etch etches the above first polysilicon except the above hole region, and only in the above hole reserving the above first polysilicon to form first polysilicon plug; (5) oxidizing one portion of the above first polysilicon plug in the above hole to form polysilicon oxide, in which one portion of the above polysilicon oxide leaves in the above hole, one portion extrudes the above third dielectric; (6) removing the above third dielectric to expose the above polysilicon oxide and one portion of left the above first polysilicon plug; (7) forming one second polysilicon; (8) by etch technique conducting etchback to the above second polysilicon, so as to form second polysilicon spacer on the above polysilicon oxide and exposed side of the above first polysilicon plug; (9) removing the above polysilicon oxide, leaving the above first polysilicon and second polysilicon spacer to become shell shape with the above hole as symmetric center.

Description

Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Consumer Cooperative Society 31 S14647 at B7 V. Description of invention () 1 _Technical field of the invention The present invention relates to a manufacturing method of dynamic random access memory (DRAM) of integrated circuits (Manufacturing Method) , In particular, the manufacturing method of stacked dynamic random access memory (stack DRAM). Ι 2. Background of the invention Taiwan has now become the kingdom of integrated circuits. In 1995, the Hsinchu Science Industrial Park (Science Based Industry Park) produced more than NT $ 100 billion, and the main integrated circuit product of the Hsinchu Science Industrial Park was the gold oxygen half field. Effective crystal volume circuit (MOSFET 1C). The traditional method of manufacturing a metal oxide half field effect transistor volume body circuit is to form a field oxide layer (Field Oxide) needed to isolate the "metal oxide half field effect transistor" on a silicon semiconductor wafer, and then remanufacture Metal Oxide Half Field Effect Transistor (MOSFET), and can be divided into P Channel Gold Oxide Half Field Effect Transistor (PMOSFET), N Channel Gold Oxide Half Field Effect Transistor (NMOSFET) and Complementary Gold Oxide Half Field Effect Transistor (CMOSFET) » In order to increase the accumulation density, the traditional dynamic random access memory system process is to form a capacitor (Three Dimension Capacitor) in the third degree space above or below the field effect transistor to increase the capacitance value of the capacitor within a limited circuit layout area; The capacitor formed above the field effect transistor is called a stacked capacitor (Stacked Capacitor), and the capacitor formed below the field effect transistor is called a trenched capacitor (Trenched Capacitor). For example, TI-Acer's dynamic random access memory uses "recessed capacitors", and "World Advanced Integrated Circuits" dynamic random access memory uses "stacked capacitors". The dynamic random access memory products of Powerchip Semiconductor Corporation, Lianhua Electronics Corporation, Winbond Electronics Corporation, Taiwan Semiconductor Manufacturing Corporation and Nanya Group also all use "stacked capacitors". A typical dynamic random access memory is to manufacture a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a capacitor (Capacitor) on a silicon semiconductor wafer (Silicon Semiconductor Wafer), and use the gold The source of the oxygen half field effect transistor (Source) is connected to the charge storage electrode (StorageNode) of the capacitor to form a memory cell of the dynamic random access memory. A huge number of memory cells are gathered into a cell array (Cell Array). On the other hand, there are other circuits around the memory cell array, such as Sense Amplifier and other circuits. These external circuits are called Peripheral Circuits. Therefore, in order to achieve the purpose of high accumulation density of dynamic random access memory, it is necessary to reduce the memory cell size of the memory (memory cell size). However, the reduction in the size of the capacitor will reduce the capacitance value, making the signal of the memory circuit / Noise (Signal Noise; S / N) ratio is reduced, resulting in shortcomings such as circuit misjudgment or circuit instability. The reason is that in order to achieve a high accumulation density of dynamic random access memory, it is necessary to find more advanced process technology to reduce the planar circuit layout area of the memory cell (Plannar Layout Area), can maintain or increase the capacitor The capacitance value. 'This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) (know the precautions on the back and then fill in this page)

ΟΪ4647 A7 B7 V. Description of the invention () In recent years, the technology of integrated circuit manufacturing technology has advanced rapidly, and the packing density (.Packing Density) of dynamic random access memory has increased dramatically. It has entered the memory cell size of 1.5 square microns (um2) Sixty-four million bits of mass production, the Japanese semiconductor company NEC announced in 1995 that there have been 1 billion bits of dynamic random access memory (1GB DRAM) prototype samples. And in the [Hsinchu Science Industrial Park] in China • The major integrated circuit companies have also entered the mass production stage of the sixty-six million-bit dynamic memory access memory with a design criterion of 0.4 to 0.45 microns, for example, " The world's advanced integrated circuit company "," Taiwan integrated circuit manufacturing company "and F Deqi Semiconductor Company all have this capability. The traditional method of increasing the capacitance of stacked capacitors is to increase the thickness of the lower electrode plate (Storage Node) of the capacitor to increase the surface area of the capacitor (Surface Area), as shown in Figure 1, where 28 is the capacitor composed of polycrystalline silicon "Storage Node" is expected to reduce the planar circuit layout area of the memory cell while maintaining the same capacitance value. However, when the size of the billion yuan continues to shrink, only by increasing the capacitor's lower electrode plate Increasing the thickness of the capacitor capacitance is impossible, it is necessary to seek more sophisticated process technology to achieve this goal. T. Kaga et al. Of Hitachi, Japan published an article titled [A 0.29 um2 ΜΙΜ-CROWN Cell and process Technology for 1-Gigabit DRAMs] on page 927 of 1994 IEDM, revealing a paper called [ΜΙΜ-CROWN] advanced stacked capacitor structure, these capacitor structures can greatly increase the capacitance value of the capacitor. The present invention discloses a novel method for manufacturing stacked capacitors, which uses a source contact window (Node Contact) of a metal oxide half field effect transistor as a center to manufacture a stacked capacitor to form a "shell type charge storage electrode" (Storage Node with Shell Shape; SNSS) can greatly reduce the planar circuit layout area of the capacitor and greatly increase the capacitance of the capacitor, so it can be applied to the manufacture of ultra-high accumulation density stacked dynamic random access memory products. 3. Brief description of the invention The main purpose of the present invention is to provide a method for manufacturing a stacked capacitor that can reduce the layout area of a memory cell (printed by the Cooperative Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs) Please fill in this page again.) Another object of the present invention is to provide a manufacturing method of high packing density (Packing Density) stacked dynamic random access memory. The main method of the present invention is briefly described as follows. First, a standard process is used to form a field oxide layer needed to isolate the "gold oxide half field effect transistor" on the silicon semiconductor wafer (Silicon Semiconductor Wafer), and then, the "gold oxide half field effect transistor" is formed, and While forming the "Gold Oxide Half Field Effect Transistor" gate (Gate Electrode), a polysilicon wordline (Polysilicon Wordline) was also formed. _. -This paper is again applicable to China National Standard (CNS) A4 specification (210X297 mm). The A7 B7 is printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of invention () Next, deposit 1 "First Dielectric", "Second Djelectric" and "Third Dielectric", and planarize the "Second Dielectric". Next, the photolithographic plasma etching technique is used to etch the r-dielectric layer, the "second dielectric layer" and the "third dielectric layer" in the capacitor region to form the source contact window (N〇de Contact) 'In the future, the charge storage electrode (StorageNode) of the stacked capacitor will make electrical contact with the source of the metal oxide half field effect transistor through the "source_contact window". Then, a layer of "First Doped Polysilicon" (first doped polysilicon) is deposited, and the "doped first polysilicon layer" is filled with the "source contact window". Next, using plasma etching technology, the "doped first polycrystalline sand layer" is anisotropically etched back (Anisotropically Etchback), the "unidirectional etchback" etched away the "source contact The "doped first polycrystalline silicon layer" outside the window "area and only the" doped first polycrystalline silicon layer "remains in the" source contact window "to form the" first "Polycrystalline sand layer asks the column" (First Polysilicon Plug). Then 'use commercial thermal oxidation technology (Thermal Oxidation) to oxidize part of the' first polycrystalline sand flash column 'in the' source contact window 'to form a polycrystalline sand oxide layer (Polysilicon Oxide), the A part of the "polycrystalline silicon oxide layer" remains in the "source contact window", and a part protrudes the "third dielectric layer" and the bottom of the "polycrystalline silicon oxide layer" It is the remaining "first polycrystalline silicon latch pillar", that is to say, the "polycrystalline silicon oxide layer" and the remaining "first polycrystalline silicon latch pillar" constitute a stacked layer structure (Stacked Layer) 〇Then remove the "third dielectric layer" to expose the "polycrystalline silicon oxide layer" and a portion of the remaining "first polycrystalline silicon layer latch", and then deposit a layer of "doped Second Polycrystalline Silicon Layer ”(Second Doped Polysilicon). Then, use plasma etching technology to perform "unidirectional etch back" on the "doped second polycrystalline silicon layer", the "unidirectional etch back" etch away the [second dielectric layer ] The "doped second polycrystalline silicon layer" on the surface and the "doped second polycrystalline silicon layer" on the upper surface of the "polycrystalline silicon oxide layer", that is, the "single Anisotropic etch-back ”terminates on the surface of the“ second dielectric layer ”and the upper surface of the“ polycrystalline silicon oxide layer ”to expose the“ polycrystalline silicon oxide layer ”and the exposed A second polycrystalline sand sidewall (Second Polysilicon Spacer) is formed on the side surface of the first polycrystalline sand layer flash column. Next, the "polycrystalline silicon oxide layer" is removed by chemical etching solution or plasma etching technique, so the remaining "doped first polycrystalline silicon layer" and "second polycrystalline silicon sidewall" constitute The capacitor's charge storage electrode (StorageNode). The "charge storage electrode" takes the "source contact window" as the center of symmetry and has a "Shell Shape", so the "Shell Charge Storage Electrode" (Storage Node with Shell Shape; SNSS) can be The planar circuit layout area of the capacitor is greatly reduced and the capacitance of the capacitor is greatly increased, and the accumulation density of the dynamic random access memory is improved. Finally, a capacitor dielectric layer-(Capacitor Dielectric) and "Third Doped Polysilicon" (Third Doped Polysilicon) are formed on the surface of the "shell type charge storage electrode", and then the lithography technology and the etching technology are used Etching away the "capacitor dielectric layer" and "doped third polycrystalline silicon layer" to form the top electrode of the capacitor (Top Plate), a stacked dynamic random access with high accumulation density carry out. This paper scale is applicable to China's national standard rate (CNS & A4 specifications (210X297mm) (Please read the precautions on the back before filling this page)

Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ 14647 A7 B7 V. Description of the invention () 4. Brief description of the figure Figure 1 is a schematic cross-sectional view of the process of prior art (Prior Art) of stacked dynamic random access memory Process Cross Section); Figures 2 to 11 are schematic cross-sectional views of the process of the embodiment (Embodiment) of the present invention.丨

I Figure 1 is a schematic cross-sectional view of the prior art (Prior Art) process of stacked dynamic random access memory. The number of each layer is the same as the number of Figure ^^ 1, where 28 is the "charge" of the capacitor composed of polycrystalline silicon Storage Node. Figure 2 is a schematic cross-sectional view of the process after forming a "gold oxide half field effect transistor" on a silicon semiconductor wafer; Figure 3 is the deposition of "first dielectric layer", "second dielectric layer" and "third dielectric layer" ”, And planarize the schematic cross-sectional view of the process after the“ second dielectric layer ”; FIG. 4 is a schematic cross-sectional view of the process after forming the“ source contact window ”using lithography and uranium engraving technology; A schematic cross-sectional view of the manufacturing process after the doped first polycrystalline silicon layer, the "doped first polycrystalline silicon layer" is filled with the "source contact window"; FIG. A schematic cross-sectional view of the manufacturing process of the "doped first polycrystalline silicon layer" after unidirectional etching, the unidirectional etching back is terminated on the surface of the "third dielectric layer" The "first polycrystalline silicon latch post" is formed in the source contact window; Figure 7 is the use of high temperature "thermal oxidation technology" to oxidize a part of the "first polycrystalline silicon question post" in the "source contact window" , In order to form a polycrystalline sand oxide layer (PolysiliconOxide) after the process cross-sectional schematic diagram, so A part of the ^ polycrystalline silicon oxide layer remains in the "source contact window", a part highlights the "third dielectric layer", and the "polycrystalline silicon oxide layer" At the bottom is the remaining "first polycrystalline silicon latch post"; Figure 8 is to remove the "third dielectric layer" to expose the "polycrystalline silicon oxide layer" and a portion of the remaining "" Schematic diagram of the process profile after the first polycrystalline silicon latch column; Figure 9 is a schematic diagram of the process profile after the deposition of the "doped second polycrystalline silicon layer"; Figure 10 is the use of plasma etching technology for the "doped" The second polycrystalline silicon layer "is a schematic cross-sectional view of the process after" unidirectional etch back ", the" unidirectional etch back "etched away the" doped "surface of the" second dielectric layer " The second polycrystalline silicon layer "and the" doped second polycrystalline silicon layer "on the upper surface of the" polycrystalline silicon oxide layer ", that is, the" unidirectional etch back "ends at The surface of the "second dielectric layer" and the upper surface of the "polycrystalline silicon oxide layer" A second polysilicon spacer (Second Polysilicon Spacer) is formed on the exposed side of the "first polycrystalline silicon layer latch"; FIG. 11 is a schematic cross-sectional view of the process after removing the "polycrystalline silicon oxide layer", The remaining "doped first polycrystalline silicon layer" and the "second polycrystalline silicon sidewall" constitute the charge storage electrode (StorageNode) of the capacitor, and the "charge storage electrode" is based on the "source contact window" It is the center of symmetry and has a "Shell Shape". This paper wave scale is applicable to the Chinese National Standard (CNS) A4 format (210X297mm) (please read the notes on the back before filling out this page, tr A7 B7 V. Description of the invention) 5. Refer to Figure 2 for an example of the invention. First, the field oxide layer 4 is opened on the P-type silicon semiconductor wafer 2 (Silicon Semiconductor Wafer) in the lattice direction (100). It is stated that "field oxide layer 4" usually uses thermal oxidation technology (Thermal Oxidation) is formed by oxidizing the "P-type silicon semiconductor wafer 2", and its thickness is between 3000 angstroms and 6000 angstroms, which is used to isolate the "gold oxide half field effect transistor". Then refer to FIG. 2. Then, in the Describe the formation of "gold oxide half field effect transistor" on the surface of "P-type silicon semiconductor wafer 2", the "gold oxide half field effect transistor" includes gate oxide layer 6 (Gate Oxide), gate electrode 8 (Gate Electrode) 、 Silicon Dioxide Spacer 12 (Source / Drain), the “Source / Drain 14” contains N_Lightly Doped Region and N + Miscellaneous area (Heavily Doped Source / Drain), as shown in Figure 2. The oxide layer 6 is formed by thermally oxidizing (Oxidized) silicon atoms on the surface of the "P-type silicon semiconductor wafer 2" in a high-temperature environment containing oxygen, and its thickness is between 100 and 200 angstroms. The gate electrode 8 is generally made of polysilicon 8 (Polysilicon) formed by Low Pressure Chemical Vapor Deposition (LPCVD), and its thickness is between 1000 and 3000 Angstroms. Then, use low pressure Silicon Dioxide (Silicon Dioxide) is formed by chemical vapor deposition. The "Silicon Dioxide 10" is usually formed by low-pressure chemical vapor deposition. The reaction gas is TetraEthOxySilane (TEOS) , The reaction temperature is about 720 ° C, the reaction pressure is between 0.2 and 0.4 Torr, and the thickness is between 500 and 1200 Angstroms. Then, the photodiode 1 is etched away using photolithography and etching techniques. "And" polycrystalline silicon 8 "to form the gate structure of the" gold oxide half field effect transistor ". Then, the ion source technology (IonImplantation) is used to form the" source / drain 14 " N_lightly doped region (Li ghtly Doped Region), its ion type is phosphorus atom (P3 · 1), its ion distribution value is between 1E13 and 3E14 atoms / cm 2, and its ion distribution energy is between 20 and 50 kev, as shown in the figure "2" printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page) and then refer to Figure 2. Next, deposit a layer of "silicon dioxide 12", and unidirectionally etch back the "silicon dioxide 12" to form a "silicon dioxide sidewall sub 12" on both sides of the "gate 8" , And the "silicon dioxide 1?" Is usually formed by low-pressure chemical vapor deposition of silicon dioxide, the reaction gas is tetrahexyl silicate (TetraEthOxySilane; TEOS), the reaction temperature is about 720 ° C, the reaction The pressure is between 0.2 and 0.4 Torr, and the thickness is between 500 and 1500 Angstroms. Finally, the ion source technology is used to form a "Heavily Doped Region" of "Source / Drain 14". The ion type is arsenic atom (AS75), and the ion dose is between 1E15 and 3E16 atoms / square. Between centimeters, the ion distribution energy is between 30 and 90 kev. After the formation of the "densely doped region", the manufacture of the "gold-oxygen half field effect transistor" was completed in Yan, as shown in Figure 2. . This paper scale is applicable to China National Standard (CNS) A4 (210X297mm). Policy printed by Employee Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs A7 B7 V. Description of invention () Now refer to Figure 3. Next, deposit a layer of "First Dielectric Layer 18" (First Dielectric), "Second Dielectric Layer 20" (Second Dielectric) and F Third Dielectric Layer 22 "(Third Dielectric), and flatten the" Second Dielectric Layer " Electric layer 20 ". The "first dielectric layer 18" is usually silicon nitride (Silicon Nitride) or silicon dioxide (Silicon Dioxide) formed by low-pressure chemical vapor deposition, and its thickness is between 500 and 1500 angstroms. The "second dielectric layer 20" is generally a boron-phosphorus doped silicon dioxide film (BoroPhosphoSilicateGlass; BPSG) or a phosphorus-doped silicon dioxide film (PhosphoSilicate Glass; PSG) formed by atmospheric pressure chemical vapor deposition (APCVD) , Its thickness is between 3000 and 10000 angstroms. The flattening process generally uses conventional chemical mechanical polishing (CMP). The "third dielectric layer 22" may be silicon nitride formed by low-pressure chemical vapor deposition with a thickness between 2000 and 6000 angstroms. Refer now to Figure 4. Next, the "first dielectric layer 18", "second dielectric layer 20" and "third dielectric layer 22" are etched in the capacitor region by using the photolithography plasma etching technique to form a source In the future, the charge storage electrode (StorageNode) of the stacked capacitor will make electrical contact with the source of the metal oxide half field effect transistor through the "source contact window 23". For the "plasma etching" of the "first dielectric layer 18", "second dielectric layer 20" and "third dielectric layer 22", magnetic field enhanced active ion plasma etching technology (Magnetic Enhanced Reactive Ion Etching; MERIE) or Electron Cyclotron Resonance (ECR) or traditional reactive ion electric uranium engraving technology (Reactive Ion Etching; RIE), which is usually used in the field of submicron technology "4 field-enhanced active ion plasma etching technology", the plasma reaction gas is generally CF4, CHF3 and Ar and other gases, for example, American Lam Research company model RAINBOW 4500 etching machine or American Applied Materials company The etching machine of model PR5000E belongs to "magnetic field enhanced active ion plasma etching technology". Now refer to Figures 5 and 6. Next, a layer of [First Doped Polysilicon cm 24] (First Doped Polysiliccm) is deposited, and the [source doped polysilicon layer 24] fills the [source contact window 23]. The [doped first polycrystalline silicon layer 24] is generally formed by low-pressure chemical vapor deposition method of synchronous phosphorus atom doping (In-situ Phosphorus Doped), and the reaction gas is PH3, 3 old 4 and > 12 For mixed gases, the reaction temperature is between 520 and 580 ° C, and the thickness is between 1000 and 3000 Angstroms. Next, using plasma etching technology, the "doped first polycrystalline silicon layer 24" is anisotropically etched back (AnisotropicallyEtchback), and the "unidirectional etchback" etched away the "source contact The "doped first polycrystalline silicon layer 24" outside the area of the window 23, and only the "doped first polycrystalline silicon layer 24" remains in the "source contact window 23" to form "First Polysilicon Plug 24A" (First Polysilicon Plug), as shown in Figure 6. For the "unidirectional etch back" of the "doped first polycrystalline silicon layer 24", the "magnetic field-enhanced active ion electric award etching technology" or "electron cyclotron resonance plasma etching technology" or traditional "Reactive ion plasma uranium engraving technology", in the technical field of submicron integrated circuit manufacturing, usually "magnetic field enhanced active ion plasma etching technology", the plasma reaction gas is generally CC14, Cl2 and Chlorine-containing gas such as HBr. -This paper scale is applicable to China National Standard (CNS) A4 (210X297mm) (please read the precautions on the back before filling this page)

-1T Printed by Beigong Consumer Cooperative of Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Description of invention () Now refer to Figures 7 and 8. Next, a part of the "first polycrystalline silicon latch post 24A" in the "source contact window 23" is oxidized by a high temperature thermal oxidation technique (Thermal Oxidation) to become the "first polycrystalline silicon interlock 24B" post 24B ”, To form a polysilicon oxide layer 26 (Polysilicon Oxide), part of the F polysilicon oxide layer 26” remains in the “source contact window 23”, and a part highlights the Three dielectrics p 22A ", and the bottom of the" polycrystalline silicon oxide layer 26 "is the remaining" first polycrystalline silicon latch 24B ", that is, the" polycrystalline silicon oxide layer 26 "And the remaining" first polycrystalline silicon interrogation column 24B "constitute a multi-layer structure (StackedLayer), as shown in Figure 7. Next, the "third dielectric layer 22A" is removed to expose the "polycrystalline silicon oxide layer 26" and a portion of the remaining "first polycrystalline silicon layer latch 24B", as shown in FIG. 8 Show. Reference is now made to Figures 9 and 10. Next, deposit a "second doped polysilicon layer 28" (Second Doped Polysilicon), as shown in Figure 9. Then, using plasma etching technology, the "doped second polycrystalline silicon layer 28" is subjected to "unidirectional back etching", and the "unidirectional back etching" is used to etch away the second Electrical layer 20A] The "doped second polycrystalline silicon layer 28" on the surface and the "doped second polycrystalline silicon layer 28" on the upper surface of the "polycrystalline silicon oxide layer 26", that is That is, the "unidirectional etch back" ends at the surface of the "second dielectric layer 20A" and the upper surface of the "polycrystalline silicon oxide layer 26" to oxidize the "polycrystalline silicon oxide" Layer 26 ”and the exposed side of the“ first polycrystalline silicon layer latch 24B ”form a second polycrystalline silicon sidewall 28A (Second Polysilicon Spacer), as shown in FIG. 10. The "doped second polycrystalline sand layer 28" is generally formed by low-pressure chemical vapor deposition of synchronous phosphorus atom doping (In-situ Phosphorus Doped). The reaction gas is a mixed gas of PH3, SiH4 and N2, and the reaction temperature It is between 520 and 580 ° C and its thickness is between 800 and 2500 Angstroms. For the "unidirectional etch back" of the "doped second polycrystalline silicon layer 28", "magnetic field enhanced active ion plasma etching technology" or "electron cyclotron resonance plasma etch technology" or traditional "Active ion plasma etching technology", in the technical field of submicron integrated circuit manufacturing, usually "magnetic field enhanced active ion plasma etching technology", the plasma reaction gas is generally CC14, Cl2 and HBr Such as chlorine-containing gas. Finally, refer to Figure 11. Next, the "polycrystalline silicon oxide layer 26" is removed with a hydrofluoric acid solution, so that the remaining [doped first polycrystalline silicon layer 24B] and the "second polycrystalline silicon sidewall 28A" constitute a capacitor Storage node (Storage Node). The "charge storage electrode" takes the "source contact window 23" as the center of symmetry and has a "shell shape" (Shell Shape), so the "shell type charge storage electrode" (Storage Node with Shell Shape; SNSS) The planar circuit layout area of the capacitor can be greatly reduced, the capacitance of the capacitor can be greatly increased, and the accumulation density of the dynamic random access memory can be improved. Finally, a capacitor dielectric layer (Capacitor Dielectric) and a "Third Doped Polysilicon" (Third Doped Polysilicon) are formed on the surface of the "shell-type charge storage electrode", and then the lithography and etching techniques are used for uranium The "capacitor dielectric layer" and the "doped third polycrystalline silicon layer" are removed to form the top electrode of the capacitor, a stacked dynamic random access memory with high accumulation density is completed in Yan. _ * This paper is again applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297mm) (please read the precautions on the back before filling this page)

, 1T i. 314647 A7 V. Description of the invention () The "capacitor dielectric layer" is formed by a standard process. It is usually formed by Oxynitride, Silicon Nitride, and Silicon Dioxide by the following method. First, the "shell type charge storage electrode" composed of polycrystalline silicon is thermally oxidized at a temperature between 850 ° C and 950 ° C to form a "dioxide" with a thickness between 40 angstroms and 200 angstroms Silicon ”; then, at a temperature between 650 ° C and 750 ° C ^ low-pressure chemical vapor deposition method to form" nitride sand "with a thickness between 40 Angstroms and 60 Angstroms; finally, at a temperature of f degrees The "silicon nitride" is oxidized between 850 ° C and 950 ° C to form a "silicon nitride" with a thickness between 20 angstroms and 50 sides. The "capacitor dielectric layer" may also be composed of Ta205 material. The above is a description of the present invention with the preferred embodiments, rather than limiting the present invention, and anyone skilled in semiconductor technology can understand that appropriate and slight changes and adjustments will still not lose the essence of the present invention, nor Departs from the spirit and scope of the present invention. (Please read the notes on the back before filling this page) V.

、 1T Printed by Beigong Consumer Cooperative of Central Bureau of Standards of the Ministry of Economics The paper size is applicable to China National Standard (CNS) A4 format (210 X 297 mm)

Claims (1)

Printed and applied for patents by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 1-The formation method of the "polycrystalline silicon structure" of the integrated circuit includes the following steps: forming the first on the semiconductor wafer (Semiconductor Wafer) First dielectric layer (First Dielectric), Second dielectric layer (Second Dielectric) and Third dielectric layer (Third Dielectric), and planarize the "Second dielectric layer"; use lithography Technical etching technology etched away the "first dielectric layer", "second dielectric layer" and F third dielectric layer "to form holes (Hole); open more layers of" first polycrystalline sand layer "( FirstPotysiliccm) 'The "first polycrystalline sand layer" is filled with the "holes"; using uranium engraving technology to etch back the "first polycrystalline silicon layer" (Etchback), the "back etching" etching Go to the "first polycrystalline silicon layer" outside the "hole" area, and only the "first polycrystalline silicon layer" remains in the "hole" to form the "first polycrystalline silicon layer" "Silicon Bolt" (First Polysiliccm Plug); Oxidation (Oxidation)-part of the f hole The "first polycrystalline silicon latch pillar" in the "hole" to form a polysilicon oxide layer (Polysilicon Oxide), part of the "polycrystalline silicon oxide layer" remains in the "jian hole", a The part highlights the "third dielectric layer"; remove the "third dielectric layer" to expose the "polycrystalline silicon oxide layer" and a portion of the remaining "first polycrystalline silicon" "R column"; forming a "second polycrystalline silicon layer" (SecondPolysilicon); using etching technology to "etch back" the "second polycrystalline silicon layer" to the "polycrystalline silicon oxide layer" and exposed The side surface of the "first polycrystalline silicon latch column" forms a second polysilicon spacer (Second Polysilicon Spacer); remove the "polycrystalline silicon oxide layer", and the remaining "first polycrystalline silicon layer" "" And "Second polycrystalline silicon sidewalls" take the "hole" as the center of symmetry and have a "Shell Shape". 2. The formation method as described in item 1 of the patent application $ Wai, wherein the "semiconductor wafer" contains electrical components; electronic / electronic components (Electrical / Electronic Devices). 3-The formation method as described in item 1 of the patent application scope, wherein the "first dielectric layer" is composed of Silicon Nitride. 4. The formation method as described in item 1 of the patent application scope, wherein the "second dielectric layer" is composed of Silicon Dioxide. 5. The formation method as described in item 1 of the patent application scope, wherein the "third dielectric layer" is composed of silicon nitride (Silicon Nitride). 6-The formation method as described in item 1 of the patent application scope, wherein the "first polycrystalline silicon layer" is formed by a low-pressure chemical vapor deposition method. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) HINi —7 III Pack — IIII — Order — i I —J · " i (Please read the precautions on the back before filling this page) H3 7 The formation method as described in item 1 of the patent application scope, wherein the "second polycrystalline silicon layer" is formed by a low-pressure chemical vapor deposition method. 8. The formation method as described in item 1 of the patent application scope, wherein the "third polycrystalline silicon layer" is formed by a low-pressure chemical vapor deposition method. 9. The formation method as described in item 1 of the patent application scope, wherein the removal of the "polycrystalline silicon oxide layer" is by using a hydrofluoric acid solution. 10. The formation method as described in item 1 of the patent application scope, wherein the "etchback" refers to the magnetic enhanced reactive ion ion etching technology (Magnetic Enhanced Reactive Ion Etching; MERIE) or the electron cyclotron resonance electric award Etching technology (Electron Cyclotron Resonance; ECR) or traditional reactive ion electric award etching technology (Reactive Ion Etching; RIE) and other plasma etching technologies. The system includes the following 11 · A method for manufacturing a stacked dynamic random access memory (Stack DRAM): forming a "gold oxide half field effect transistor" (MOSFET) on a silicon semiconductor wafer; forming a "first First dielectric layer (First Dielectric), "Second dielectric layer (Second Dielectric) and" Third dielectric layer "(Third Dielectric), and planarize the" Second dielectric layer "; use of lithography technology Etching technology is used to complete the "first dielectric layer", "second dielectric layer" and "third dielectric layer" to form a source contact window (Node Contact Hole); forming a "first polycrystalline sand layer" (FirstPolysilicon), the "first polycrystalline sand layer" fills the "source contact window"; using etching technology to etch back the "first polycrystalline silicon layer" (Etchback), the "back etching" 『The first polycrystalline silicon layer outside the area of the“ source contact window ”is etched away, and the“ first polycrystalline silicon layer ”remains only in the“ source contact window ” Formed "First Polysilicon Pole" (First Polysilicon P lug); Employee Welfare Committee of the Central Bureau of Standards of the Ministry of Economic Affairs printed oxidation (Oxidation) — the “first polycrystalline silicon latch post” in the “source contact window” described in part to form a polycrystalline silicon oxide layer ) 'A part of the "polycrystalline silicon oxide layer" remains in the "source contact window", a part protrudes the "third dielectric layer"; remove the F third dielectric layer To expose the "polycrystalline silicon oxide layer" and a portion of the remaining "first polycrystalline silicon latch pillar"; form a layer of "second polycrystalline silicon layer" (SecondPoly ^ licon); use etching technology to The "second polycrystalline silicon layer" is "etched back" to form a second polycrystalline silicon sidewall on the side of the "polycrystalline silicon oxide layer" and the exposed "first polycrystalline silicon latch pillar" (Second Polysilicon Spacer); This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) S14647 H3 remove the "polycrystalline silicon oxide layer", the remaining "first polycrystalline silicon" The "layer" and "second polycrystalline silicon sidewall" are symmetrical with the F source contact window And a "Shell Shape" (ShellShape); form a "Capacitor Dielectric" on the surface of the "Shell Charge Storage Electrode" to form a "Third Polysilicon Layer" (ThirdPolysUicon), and then Using lithography and etching techniques to etch away the "capacitor dielectric layer" and "third polycrystalline silicon layer" to form the top electrode of the capacitor (Top Plate) ° I2-as described in item 11 of the patent application A manufacturing method, wherein the "gold oxide half field effect transistor" contains a gate oxide layer (Gate Oxide), a gate electrode (Gate Electrode), a silicon dioxide sidewall spacer (Silicon Dioxide Spacer), a source / drain (Source / Drain). Π The manufacturing method as described in item 11 of the patent application scope, wherein the "first dielectric layer" is composed of silicon nitride (SiliconNitride), and its thickness is between 800 angstroms and 1500 angstroms. 14. The manufacturing method as described in item 11 of the patent application scope, wherein the "second dielectric layer" is composed of silicon dioxide (Silicon Dioxide), and its thickness is between 3000 angstroms and 8000 angstroms. 15. The manufacturing method as described in item 11 of the patent application scope, wherein the "third dielectric layer" is composed of silicon nitride (SiliconNitride), and its thickness is between 2000 angstroms and 6000 angstroms. 16. The manufacturing method as described in item 11 of the patent application scope, wherein the "first polycrystalline silicon layer" is formed by a low-pressure chemical vapor deposition method, and its thickness is between 1000 angstroms and 3000 angstroms. 17. The manufacturing method as described in item 11 of the patent application scope, wherein the "second polycrystalline silicon layer" is formed by a low-pressure chemical vapor deposition method, and its thickness is between 600 angstroms and 2500 angstroms. 18. The manufacturing method as described in item 11 of the patent application scope, wherein the "third polycrystalline silicon layer" is formed by a low-pressure chemical vapor deposition method, and its thickness is between 1000 angstroms and 2500 angstroms. 19. The manufacturing method as described in item 11 of the patent application scope, wherein the removal of the "polycrystalline silicon oxide layer" uses a hydrofluoric acid solution. Economy. Printed by Qiu Central Standards Bureau Employee Welfare Committee 20 _ The manufacturing method as described in item 11 of the patent application scope, in which the "capacitor dielectric layer" is made of Oxynitride, Oxynitride and Nitrile Composed of oxidized sand, or composed of Ta205. 21. The manufacturing method as described in item 11 of the patent application scope, wherein the "etch back" refers to the magnetic enhanced ion reactive ion etching technology (Magnetic Enhanced Reactive Ion Etching; MERIE) or electron cyclotron resonance electric uranium Engraving technology (Electron Cyclotron Resonance; ECR) or traditional reactive ion plasma etching technology (Reactive Ion Etching; RDE) and other electric hybrid etching technology. The paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 104 7- ^ 8 S14647 Inch (N ¢ 1 314647 S14647 314647 Vv