TW307919B - The manufacturing method of capacitor - Google Patents

Abstract

A manufacturing method for memory cell of DRAM, it includes following steps:Form field oxide, MOSFET and wordline on semiconductor substrate; Deposit 1st and 2nd insulator, and planarize 1st insulator; Etch 1st and 2nd insulator to form node contact, which is through by storage node of capacitor to do electricity contacting with source of MOSFET;Deposit a 1st doped polysilicon to fill source contact; Form trench, which depth is smaller than thickness of 1st doped polysilicon, on 1st doped polysilicon; Deposit 3rd insulator to fill trench; Form 3rd insulator plug inside the trench; Proceed anisotropic etching back on 1st doped polysilicon to etch partially thickness of 1st doped polysilicon; Deposit a thin 2nd doped polysilicon, and proceed anisotropic etching back on thin 2nd and 1st doped polysilicon till the surface of 2nd insulator and 3rd insulator plug, and form polysilicon spacer on side of 3rd insulator plug; Remove 3rd insulator plug, and consist storage node of capacitor by residual 1st doped polysilicon and polysilicon spacer; Form thin capacitor dielectric and 3rd doped polysilicon on storage node, and etch capacitor dielectric and 3rd doped polysilicon to form plate electrode of capacitor.

Description

307919 A7 B7 V. Description of the invention () Printed by the employee consumer cooperative of the Central Standardization Bureau of the Ministry of Economic Affairs

1. The technical area of the invention. The present invention is related to the dynamics of Zhen Nuoer Road__Manufacturing Me ^ iod of the capacitor (C ^ acitor) ° .2. Background of the invention is typical The dynamic random access memory device is to manufacture a metal oxide semiconductor field effect transistor (MOSFET) and a capacitor review (Capacitor) on a silicon semiconductor substrate (Silicon Semiconductor Substrate), and use the metal oxide The source of the half field effect transistor (Source) is connected to the charge storage electrode (storageNode) of the capacitor to form a memory cell of the dynamic random access memory. '', The source of the metal oxide half field effect transistor is in electrical contact with the capacitor, digital information is stored in the capacitor, and the metal oxide half field effect transistor, the bit line and the word line array are used to relax Digital information stored in the capacitor. In order to increase the accumulation density of dynamic random access memory devices, the pass_state_machine access memory system process is to form a capacitor in the third-degree space above or below the metal oxide half field effect transistor to limit the circuit layout area The capacitance value of the capacitor is added internally; the capacitor formed above the metal oxide half field effect transistor is called a stacked capacitor (Stacked Capacitor), and the capacitor formed below the metal oxide half field effect transistor is called a trenched capacitor (TrenchedCapacitor) . Fu Tong [The method of increasing the capacitance of stacked capacitor 1 is to increase the thickness of the pad under the capacitor to increase the surface area of the capacitor (Surface Area), so as to reduce the planar area of the memory cell (Plannar Area), The same capacitance value should also be maintained. However, increasing the thickness of the lower electrode plate of the capacitor produces a steep terrain. The subsequent photolithographic etching and thin film sinking process is not easy to perform, reducing the yield of the product (Yield). [Concave Capacitor] The method of increasing the capacitance is to increase the depth of the concave groove in the semiconductor substrate to increase the surface area of the capacitor (Surface Area), so that the same capacitance should be maintained while reducing the [planar area] of the memory cell However, due to the destruction of the crystal structure of the semiconductor substrate by the [concave trench capacitor], leakage current is likely to occur. In recent years, the integration density of dynamic enzyme machine access memory has increased rapidly. At present, the integrated circuit company of Taiwan [Hsinchu Science Industrial Park] (ScienceBasedlndustrialParfc: SIPA) has entered the memory cell with a size of 600 square meters of 1.5 square micrometers. In the mass-production phase of 10,000 bits, for example, the world's advanced integrated circuit company (Vanguard International Semiconductor) stacked dynamic random access memory and the De groove semiconductor company (TI-Acer) grooved dynamic random access memory. The integration density of foreign dynamic random access memory devices has also shown a fairly rapid increase. For example, Japanese semiconductor companies such as SONY announced in 1995 that they already have prototypes of 1 billion dynamic random access memory (1GB DRAM) Samples come out: T. Kaga et al. Of Hitachi Corporation in IEDM in 1994 (please read the notes on the back before filling in this page) Λ. Order Λ This paper size is applicable to China National Standards (CNS) A4 specification (2丨 0X297mm) 307919 V. Description of the invention (Λ7 B7 page 927 was also published-an article titled [A 0.29 um2 ΜΙΜ-CROWN Cell and process T The paper "echnology for 1-Gigabit D ^ AMs" reveals an advanced capacitor structure called [ΜΙΜ-CROWN], and these stacked capacitor structures can greatly increase the capacity of the capacitor. The present invention discloses a High-density stacked dynamic random access memory (Stock Dynamic Random Access Memory; Stack DRAM) capacitor manufacturing method, can greatly increase the capacitance value of the capacitor, can be applied to more than 64 million bit [Heman type Dynamic Random Access Memory] process. 3. Brief description of the invention The improved dynamics of the present invention are as follows: § The main purpose is to provide a method for accessing memory in a limited circuit layout; £ «Container capacitance. (CircuitLayout) area (Please read the precautions on the back before filling in this page) " Printed by the Cooperative Society of the Central Standards Bureau of the Ministry of Economic Affairs. Another object of the present invention is to provide a high-density [heaped dynamic random access memory The manufacturing method of the 100 million body. The main manufacturing method of the present invention is as follows. First, a traditional standard process is used on a silicon semiconductor substrate (Silicon Semicondu ctor Substrate) to form a field oxide layer (Field Oxide) required to isolate the electrical active area (Active Area), and then to form a gold oxide half field effect transistor and a word line (WordUne), the gold gas half field effect transistor includes About the oxide layer (Gate Oxide), gate electrode (Gate Electrode), side wall (Spacer) and source / drain (Source / Drain). Next, deposit a layer of [First Insulation Layer] and [Second Insulation Layer], and planarize the [No .--- Insulation Layer]. Next, using lithography technology and plasma etching technology to etch away the [first insulation layer] and [second insulation layer] to form the source contact window (Node Contact) of the metal oxide half field effect transistor, in the future, capacitors The [charge storage electrode] will make electrical contact with the source of the [gold gas half field effect transistor] through the [source contact window]. Next, a layer of [First Doped Pdysiliccm] (First Doped Pdysiliccm layer) is deposited, and the [Doped first polycrystalline silicon layer] fills the [source contact window]. Then, a lithography technique and a plasma etching technique are used to form a trench on the surface of the [loaded first polycrystalline silicon layer] near the center of the [capacitor area]. Next, sink the gf-layer [third insulating layer], and then use plasma etching technology to unidirectionally etch back the [third insulating layer] (^^ 〇11 " 〇1 ^ £ 11 Etchback), The solid etching is terminated on the surface of the [doped first polycrystalline silicon layer] to form a [third insulating layer stud] (™ rdlnsulatorP1ug) in the [concave groove]. Next, a plasma etching technique is used to perform unidirectional etching (Anisotropical Etchback) on the [doped first polycrystalline silicon layer] to etch away a part of the thickness of the [doped first polycrystalline silicon M] , A part of the [third insulating layer stud] is exposed. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297mm)

* 1T gas! V. Description of the invention () A7 B7 Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. Next, deposit a thin layer of thin second doped polysilicon (Thin Second Doped Polysilicon), and immediately use plasma etching technology The [thin doped second polycrystalline silicon layer] performs unidirectional etch back, and the [unidirectional etch back] ends at the [second green layer] and [third insulating layer stud] 】 The upper surface to form a polysilicon spacer (Polysilicon Spacer) on the side of the ΥInsulation Zhan stud post, said [polysilicon spacer] and the phase of [doped first polysilicon layer] Connection, and finally, the [third green layer stud] is removed, and the [charge storage electrode] with high capacitance is completed in Yan. 4. Brief description of the drawings Figures 1 to 11 are process cross sections of the embodiment of the invention (Process Cross Section). 5. Embodiment of the invention First, the resistance value is about 3.5 ohm-ctn, the lattice direction (100 ) (Crystalline Orientation) P-type diced semiconductor substrate 1 is formed with a field oxide layer 3, the [field oxide layer 3] has a thickness between 3000 angstroms and 6000 angstroms, and is used to isolate electrical components. Then, a metal oxide half field effect transistor is formed on the [P-type silicon semiconductor substrate 1], the metal oxide half field effect transistor includes a gate oxide layer 5 (Gate Oxide) and a gate electrode 7 (Gate Electrode) , Side wall 11 (Spacer) and source / drain 13A / 13B (Source / Drain) and other components. The [gate oxide layer 5] is formed by thermally oxidizing the surface of the [P-type silicon semiconductor substrate 1], and its thickness is between 80 and 200 angstroms. The [Gate 7] is composed of polycrystalline sand 7 (Polysiliccm) formed by Low Pressure Chemica Vapor Deposition (LPCVD), and its thickness is between 1000 and 3000 angstroms. Then, the [Low Pressure Chemical Vapor Deposition Method] was used to form two gasification splashes. 9 (Cap Oxide), with a thickness between 500 and 1200 Angstroms, and then formulated using Lithography and Etching The patterns of the [silicon dioxide 9] and the [polycrystalline silicon 7] are used to form the [gate 7] of the gold gas half-field effect transistor. Next, a dielectric layer 11 is deposited, and the [dielectric layer 11] is unidirectionally back-etched to produce a [dielectric layer sidewall 11A] on both sides of the [gate 7] . The [dielectric layer 11] is usually an undoped silicon dioxide (Untyped Silicon Dioxide) formed by a low-pressure chemical vapor deposition method, and its reaction gas is TetraEth Oxysilane (TEOS), The reaction temperature is about 720 ° C, the reaction pressure is between 200 and 300 mTorr, and | 4: the thickness is between 800 and 1600 Angstroms. (Please read the note ^^ item on the back before filling in this page) Order A! This paper size is easy to use Chinese National Chess Standards (CNS) M specifications U10X297 public daughter) Λ7 B7 f- 307919 V. Description of invention () Then, form Source / Drain 13A / 13B (Source / Drain). The source / drain 13A / 13B is composed of [N-light source / drain] and [N + heavy source / drain]; the [N · light miscellaneous source / drain] Before the formation of [side wall element 11], use phosphorus ions (P31) for ion implantation to form On Implantation). The ion implantation dose is between 1E13 and 1EH atoms / cm2, and the ion implantation energy is between Between 20 and 40 Kev; [N + heavily doped source / drain] is formed after the formation of the [side wall sub 1], using arsenic ions (As75) for ion distribution, and the ion distribution dose is Between 1K15 and 1E16 atoms / cm 2, and the ion distribution energy is between 20 and 80Kev, after the completion of the [source / drain 13A / 13B], the production of gold-oxygen half-field effect transistors, Yu Yan Complete 'as shown in Figure〗. Next, deposit a layer of [first insulation layer 21] and [second insulation layer 23], and planarize the [first insulation layer 21], as shown in FIG. 2. The [first insulation waste 21] is usually a phosphorous glass film (13〇1: 〇-PhosphoSilicateGlass; BPSG) or _ skin glass film (PhosphoSilicateGlass; PSG) formed by chemical vapor deposition (Chemical Vapor Deposition; CVD) The thickness is between 5000 and 10000 angstroms. After the deposition is completed, the [first insulating layer 21] is planarized using traditional thermal flow technology (Thermal Flow), and the thermal flow temperature is between 85 (TC Between 95 and TC, the heat flow time is between 10 minutes and 30 minutes. In addition to using heat flow technology to planarize the [first insulating layer 21], conventional chemical mechanical polishing can also be used Technology (Chemicil Mechanical Polishing; CMP) planarizes the [first insulating layer 21]. The [second insulating layer 23] is usually silicon nitride (Silicon Nitride; Si3N4), the reaction gases are NH3 and SiH4, the reaction temperature is about 760 ° C, the reaction pressure is about 350 mtorr, and the thickness is between 500 and 1500 Angstroms. Then, using lithography and plasma etching technology (Lithography and Plasma Et ching) The [first insulating layer 21] and the [first ::: insulating layer 23] are etched away to form the source contact window 24 (Node Contact) of the metal oxide half field effect transistor, as shown in FIG. 3, in the future , The [charge storage electrode] of the capacitor will make electrical contact with the irrigation electrode of the metal oxide half field effect transistor through the [source gripping sugar window 24]. The [plasma etching] may be a magnetic field enhanced active ion type Plasma etching (Magnetic Enhanced Reactive Ion Etching; MERJE) or Electron Cyclotron Resonance (ECR) or traditional reactive ion plasma etching (Reactive Ion Etching; RIE) in submicron integrated circuits In the technical field, [Magnetic field-enhanced active ion plasma etching] is generally used, and plasma reaction gases-generally CF4, CHF3, and Ar-containing fluorine gases. Next, a layer of [doped] first polycrystalline silicon layer is deposited 25] (First Doped Polysilicon), the [doped first polycrystalline silicon layer 25] fills the [source contact window 24], as shown in FIG. 4. The [doped first polycrystalline silicon layer Layer 25] is to use synchronous phosphorus doping (In-sit u Phosphorus Doped) is formed by low-pressure chemical vapor deposition method, the reaction gas is PH3, SiH4 This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 grub) (please read the precautions on the back before filling this page ) —L-if Printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A 7 B7 Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention () Mixed gas with N2, the reaction temperature ranges from 525 to 575 ° C In between, since the width of the [source contact window 24] is between 2000 and 5000 angstroms, the thickness of the [doped first polycrystalline silicon layer 25] is between 4000 and 8000 angstroms. Then, a groove 26 (Trench) is formed on the surface of the [doped first polycrystalline comparison layer 25] near the central position of the [capacitor area] using the photolithography technique and the electric moth engraving technique, as shown in FIG. The plasma etching of the [doped first-polycrystalline silicon layer 25] may be magnetic field enhanced active ion plasma etching (Magnetk Enhanced Reactive Ion Etching; MER1E) or electron cyclotron resonance mildew plasma etching (Electron Cyclotron Resonance; ECR) or traditional Reactive Ion Etching (RIE), but in the field of sub-micron technology, [magnetic field strong-strength active ion plasma etching] is generally used. The gas is generally CC14, Cl2, HBr and other gas-containing gas. Next, a layer of [third insulating layer 27] is deposited, and the [third insulating layer 27] fills the recess 26, as shown in FIG. The two-layer Zhu Jiyuan layer 27] usually doped with low-pressure chemical vapor deposition of doped silicon dioxide (EtapedSiUccm Dioxide) or undoped heterogeneous silicon dioxide (Undoped Silicon Dioxide), the reaction gas is tetrahexyl silicic acid (TetraEtbOxySilane ; TEOS), the reaction temperature is about 720 ° C, the reaction pressure is between 200 and 300 mTorr, and its thickness is between 3000 and 6000 angstroms. Then, the plasma etching technique is used to perform unidirectional etch back (Anisotropical Etchback) on the [third insulating layer 27], the etch back is terminated on the surface of the [doped first polycrystalline silicon layer 25], In order to form a [Third Insulator Plug 27A] (Third Insulator Plug) in the [recess 26], as shown in FIG. 7. The [unidirectional etch back] of the [third insulating layer 27] is generally [magnetic field enhanced active ion plasma etching], and the plasma reaction gas is a fluorine-containing gas such as CF4, CHF3 and Ar. Next, using the [third insulating layer stud 27A] as an etch protection cover (EtchMask), a unidirectional etch back is performed on the [doped first polycrystalline silicon layer 25A] using plasma etching technology, to A part of the thickness of the [doped first polycrystalline silicon layer 25A] is etched away to become a [doped first polycrystalline silicon layer 25B], and a part of the [third insulating layer inspection pillar 27A] is exposed , Just 8 shows. For the unidirectional back touch etching of the [doped first polycrystalline silicon layer 25A], the [magnetic field enhanced active ion plasma etching] is generally used. The propeller reaction gas is generally CC14, Cl2 and Chlorine-containing gas such as HBr. 〇 Next, deposit a thin layer of thin second doped polycrystalline silicon (Thin Second Doped)

Polysilicon), as shown in FIG. 9, the plasma thin etching technique is used to unidirectionally perform the [thin doped second polycrystalline silicon layer 29] and [doped first polycrystalline silicon layer 25B] Etching back, the [unidirectional etch back] ends on the upper surface of the [second insulating layer 23] and [third insulating layer stud 27A], so that the [third insulating layer stud 27A] A polysilicon spacer 29A (Polysilicon Spacer) is formed on the side, and the [polysilicon spacer 29A] is connected to the polycrystalline cut layer 25C, as shown in FIG. 10. The [thin doped second polycrystalline silicon layer 29] described in this paper is also applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X 297mm) (please read the notes on the back and fill in this page ) L

、 1T V. Description of the invention () A7 B7 Printed by the Ministry of Economic Affairs, China National Bureau of Standards and Technology Negative Consumers Cooperatives is formed by the use of synchronous scale atoms. Doped (In-situ Phosphorus Doped) low-pressure chemical vapor deposition method, the reaction gas is The mixed gas of PH3, SiH4 and Hou has a reaction temperature between 52Q and 580 ° C and a thickness between 1000 and 2000 Angstroms. Next, using a diluted hydrofluoric acid solution (Diluted HF) to remove the [third insulating layer plug 27], the remaining [doped first-polycrystalline silicon layer 25C] and [polycrystalline silicon sidewall sub 2M] constitute The [charge storage electrode] of the capacitor is shown in Figure 1: 1, and the [charge storage electrode] with high capacity is completed in Yan. Finally, a standard process is used to form a very thin capacitor dielectric layer (Capacitor Dielectric) and a layer [doped H-polycrystalline silicon layer] on the surface of the [charge storage electrode] and use photolithography and plasma etching The technology etches the [capacitor interlayer 11] and the [doped third polycrystalline silicon layer] to form the upper electrode of the capacitor (Plate Electrode), and the stacked capacitor with high capacitance is completed in Yan. The [doped third polycrystalline silicon layer] is usually formed by low-pressure chemical vapor deposition method of synchronous phosphorus atom doping (Un-situ Phosphorus Doped). The reaction gas is a mixed gas of PH3, SiH4 and N2. The temperature is between 520 and 580 ° C, and its thickness is between 1000 and 2500 Angstroms. For the plasma etching of the [doped third polycrystalline silicon layer], the [magnetic field enhanced active ion plasma etching] is generally used, and the plasma reaction gases are generally C〇4, Cl2, HBr, etc. Chlorine-containing gas ° The [capacitor dielectric layer] is usually formed of silicon oxide nitride (Oxynitride), silicon nitride, and silicon dioxide by the following method, which is a traditional standard process. First, thermally oxidize the [charge storage electrode] composed of polycrystalline silicon at a temperature between 850 ° C and 950 ° C to form [silicon dioxide] with a thickness between 40 Angstroms and 200 Angstroms ; Then, at a temperature between 650 ° C to 750. (: [Silicon Nitride] with a thickness between 40 Angstroms and 60 Angstroms is formed by low-pressure chemical vapor deposition method at the time; finally, it is oxidized when the temperature is between 85 ° C and 950 ° C The [silicon nitride] is used to form a [silicon oxide nitride] with a thickness between 20 Angstroms and 50 Angstroms. The [Capacitor Dielectric Nitride] can also be composed of Ta205 material. The above is the best embodiment Let's describe the present invention, not limit the present invention, and those familiar with semiconductor technology can understand that appropriate and slight changes and adjustments will still lose the essence of the present invention and will not deviate from the spirit of the present invention He Fan Yuan-(Please read the notes on the back before filling this page)

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• The size of 1T paper is used in China National Standard (CNS) Α4 specification (2 丨 OX 2W mm)

Claims (1)

3079ί9 6. Patent scope B8 C8 D8 • A method of manufacturing memory cells for dynamic random access memory, which includes the following steps: forming an active area on a semiconductor substrate (Semiconductor Substrate) A field oxide layer (Field Oxide), and forming a metal oxide half field effect transistor and a word line (Wordline); deposit [first insulation layer] and [second insulation layer], and planarize the [first insulation [Layer]; The [first insulating layer] and the [second insulating layer] are etched away to form a source contact window (Node Contact). In the future, the charge storage electrode (Storage Node) of the capacitor will pass through the [source electrode Contact window] Make electrical contact with the source electrode of the metal-oxygen half field effect transistor (Source); (First Doped Polysilicon), the deposited layer [First Doped Polysilicon layer] (First D〇f [Doped The first polycrystalline silicon layer is full of the [source contact window] .; (Please read the precautions on the back before filling out this page). Installed. Printed in the [Capacitor area] by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Central position A trench is formed on the surface of the nearby [doped first polycrystalline silicon layer], and the depth of the [concave trench] must be less than the thickness of the [doped first polycrystalline silicon layer]; deposit a layer [third Insulation layer], the [third insulation calendar] fills the [concave ditch]; [Third Insulator Plug] (Third Insulator Plug) is formed in the [concave ditch]; for the [doped The first: Γ polycrystalline silicon layer J is unidirectionally etched back to etch a part of the thickness of the [doped first polycrystalline silicon layer]; deposit a layer of [thin doped second polycrystalline silicon layer 】 (Thin Second Doped Polysilicon), and the etching is used to unidirectionally etch the [thin doped second polycrystalline silicon layer] and [doped first polycrystalline silicon layer], the [single Anisotropic etchback] terminates on the upper surface of the [second insulating layer] and [third insulating layer stud] to form polysilicon sidewalls (PolysiliconSpacer) beside the [third insulating layer stud] ); Remove the [third insulating layer stud], the remaining [doped first polycrystalline silicon layer] and [The polysilicon sidewall] constitutes the [charge storage electrode] of the capacitor; a thin dielectric capacitor layer (CapacitorDielectric) and a layer of [doped third polysilicon layer are formed on the surface of the [charge storage electrode] ], And using photolithography and etching techniques to etch away the [capacitor dielectric layer] and the [doped third polycrystalline silicon layer] to form the upper electrode of the capacitor (PlateElectrode). The manufacturing method described in item 1, wherein the [first insulating layer] is silicon dioxide (Silicon Dioxide), and its thickness is between 5000 and (1 10000 Angstroms). 3. As described in item 1 of the patent application scope The manufacturing method, wherein the [second insulating layer] is silicon nitride (Silicon Nitride), the thickness of which is between 500 to 1S00 Angstroms. This paper scale is applicable to China National Standard (CNSJ A4 standard (210X297mm). Order A8, B8, C8, D8. Printed by the Ministry of Economic Affairs, Central Bureau of Preservation and Consumer Cooperatives =, patent application scope 4 The manufacturing method described above, wherein the method of forming the concave groove of the first polycrystalline silicon in the center of the capacitor includes: forming a layer of photoresist on the doped first complex crystal; defining the concave using photolithography technology _Position; etched groove; the depth of the groove is less than the thickness of the [doped second polycrystalline sand layer] above the second insulating layer. 5. As described in item 1 of the patent application scope The manufacturing method, wherein the [third insulating layer] is silicon dioxide (Silicon Dioxide), which is frequently between 3000 and 60 CK. 6. The production method as described in item 1 of the patent application park, wherein the thickness of the [first doped polycrystalline silicon layer] is between 4000 and 8000 angstroms. 7. The manufacturing method as described in item 1 of the patent application, wherein the [thin doped second polycrystalline silicon layer] has a thickness between 1000 to 20W. 8. The manufacturing method as described in item 1 of the patent application scope, wherein the thickness of the [doped third polycrystalline silicon layer] is between 10Q9 and Angstrom-9. As claimed in item 1 of the patent application park The manufacturing method described above, wherein the [capacitor dielectric layer] is composed of silicon oxide nitride (Oxynitride), silicon nitride and silicon dioxide, or is composed of Ta205. (1) The manufacturing method as described in item 1 of the patent application scope, wherein the method of forming the [third insulating layer stud] in the [concave ditch] is to engrave the [second insulating layer]. 11. The manufacturing method as described in item 1 of the patent application scope, wherein the method for removing the [third insulating layer inspection pillar] is to remove it by chemical wet etching. 12-A method for manufacturing memory cells of dynamic random access memory, including the following steps: forming a field oxide layer (Held Oxide) required to isolate an electrical active area (Semiconductor Substrate) on a semiconductor substrate (Semiconductor Substrate) , And form a metal oxide half field effect transistor and Wordline: deposit a layer of [first insulating layer], the [first green layer 1 is composed of gingival and silicon dioxide, silicon nitride is located Below, the chopped dioxide is located above, and then, the [first insulating layer] is flattened; a layer of [second insulating layer] is deposited; this paper scale is applicable to the Chinese National Falcon (CNS) A4 wash grid (210x297 public) 3 , Τ (please read the $ item on the back and then fill in this page) AS B8 C8 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy 6. The scope of the patent application is to etch the [first insulating layer] and the [second insulating layer] to form a source contact window (Node Contact). In the future, capacitors The charge storage electrode (Storage Node) will make electrical contact with the source electrode of the gold-oxygen half field effect transistor through the [source contact window]; " deposit a layer [the first complex compound Crystal Sands] (FirstDopedPolysi.li.con), the [doped first-polycrystalline silicon layer] fills the [source contact window]; the [doped first near the center of the [capacitor area] Polycrystalline silicon layer] A trench is formed on the surface, and the depth of the [concave trench] must be less than the thickness of the [doped first polycrystalline silicon layer]; deposit a layer of [third insulating layer I, the [ The third insulating layer is filled with the [concave ditch]; [Thifdlmulator Plug] is formed in the [concave ditch]; the [doped first polycrystalline silicon calendar] is performed Unidirectional etch back, to etch a part of the thickness of the 【 Mixed first polycrystalline silicon layer]; deposit a [thin second doped polysilicon layer] (Thin Second Doped Polysilicon), and use etching technology to the [thin doped second polycrystalline silicon layer] ] And [Doped first polycrystalline silicon layer] perform unidirectional etch back, the [unidirectional etch back] ends at the [second insulating layer] and [third insulating layer inspection column] On the upper surface, to form polysilicon space sidewalls (PolysiliconSpacer) beside the [third insulating layer stud]; remove the silicon dioxide on the [first_layer] upper layer, the [second insulating layer] and [Third insulation layer stud], the remaining [doped first polycrystalline sand layer] and [polycrystalline silicon sidewall] constitute the [charge storage electrode] of the capacitor; a layer of thickness is formed on the surface of the [charge storage electrode] Very thin capacitor dielectric layer (CapacitorDielectric) and a layer of [doped third polycrystalline silicon layer], and using lithography and etching technology to etch the [capacitor dielectric layer i and the said [doped third Polycrystalline silicon layer] to form the upper electrode of the capacitor (Pla te Electrode). 13. The manufacturing method as described in Item 12 of the patent application, wherein the [first insulating layer] is composed of silicon nitride (SiliconNitride) and silicon dioxide (Silicon Dioxide), silicon nitride is located below, two The oxide sand is located above, where the thickness of silicon nitride is between 500 and 1000 angstroms, and the thickness of silicon dioxide is between 5000 and 10000 angstroms. 14. The manufacturing method as described in item 12 of the patent application scope, wherein the [second insulating layer] is silicon nitride (Silicon Nitride), and its thickness is between 500 and 1500 angstroms. 15. The manufacturing method as described in Item 12 of the patent application, wherein the method of forming the concave groove of the first polycrystalline silicon in the center of the capacitor 'includes: forming a layer of photoresist on the doped first On the polycrystalline silicon layer: Use photolithography technology to define the location of the groove; etch the groove ί This paper scale is calibrated using the Chinese National Standard (CNS} _Α4 wash grid (210X 297 mm) (please read first Note on the back and fill in this Ϊ) Order A8 B8 08 D8 307919 6. The depth of the groove described in the patent application is less than the thickness of the [doped second polycrystalline silicon layer] above the second insulating calendar 16. The manufacturing method as described in item 12 of the patent application scope, wherein the [third insulating layer] is Silicon Dioxide (Silicon Dioxide), and its thickness is between 3000 and 6 (»0 Angstroms. 17 · The manufacturing method as described in item 12 of the patent application scope, wherein the thickness of the [doped first polycrystalline silicon layer] is between 4000 and 8000 angstroms. 18 · As described in item 12 of the patent application scope Manufacturing method, wherein the [thin doped second polycrystal Silicon layer] whose thickness is between 1000 and 2000 angstroms. 19 · The manufacturing method as described in item 12 of the patent application scope, wherein the thickness of the [doped third polycrystalline silicon layer] is between 1000 To 30Θ0 Angstroms. 20. The manufacturing method as described in item 12 of the patent application scope, wherein the [capacitor dielectric layer] is composed of Oxynitride, Silicon Nitride and Silicon Dioxide, Or composed of Ta205 ° 21 · The manufacturing method as described in item f of the patent application, where the method of forming the [third insulating peg post] in the [concave ditch] is to etch back the [second Insulation] 22 · The manufacturing method as described in item Π of the scope of the patent application, wherein the method of removing the [third insulating layer stud] is removed by chemical wet etching. (Please read the notes on the back first (Fill in this page again) Packing-The paper standard printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy uses the Chinese National Standard (CNS > A4 wash grid. (210X297mm)