五、發明説明（/) 1.發明之技術領域 本發明是有關積體電路之動態隨機存取記憶 :體之電容器 的製造方法（Method)與結構（structure)。 2 ·發明背景 動態隨機存取記憶體被廣汎的應用於電子工業’諸如電 腦工業等。典型的動態隨機存取記憶體是在矽半導體基板上 製造一個場效電晶體（Field Effect Transistor ; FET)與 電容器（Capac i tor )，並利用所述場效電晶體的源極 (Source)來連接電容器的電荷儲存電極（Storage Node) 以形成動態隨機存取記憶體的記憶元（Memory Cell)。周邊 電路的列解碼器（Row Decorder)藉由字語線和場效電晶體 來選擇存取記憶元，行解碼器（Column Decorder)和讀寫電 路（Read/ffrite Circuit )則將二元資訊（Binary Information)以電荷的型態儲存在電容器內。 最近幾年，動態隨機存取記憶體的集積化（Packing Density)快速的增加，例如，目前一個晶粒內約有 64000000個記憶元，估計到1998年時，-一個晶粒內將達到 2560G00GG個記憶元。爲了增加動態隨機存取記憶體之電容 器面積，一些特殊的堆疊式電容器結構’例如日本Fujitsu 公司的鰭型（Fin)、日本Mitsubishi公司的皇冠型 (Crown)等結構相繼出現。Y. Park等人更在美國專利第 5332685號亦揭露了一種【刀叉型】電容器電荷儲存電極 (Capacitor With Fork-Shaped Storage Node) ’ 但是’ 這種【刀叉型】電荷儲存電極結構卻需要額外的電路接地設 計準則（Ground Design Rule)，限制了記憶元的面積。 I u HI ^^^1 m 1 I— 1. i -« 1-»- 0¾--=° (請先閱讀背面之注意事項再填寫本頁) 夂紙垠尺度逯用中國國家標隼（CNS ; Μ規格；：!！0.< 2W公t5. Description of the invention (/) 1. Technical field of the invention The present invention relates to a dynamic random access memory of an integrated circuit: a manufacturing method (structure) and a structure of a capacitor of the body. 2. Background of the invention Dynamic random access memory is widely used in the electronics industry, such as the computer industry. A typical dynamic random access memory is to manufacture a field effect transistor (FET) and a capacitor (Capac i tor) on a silicon semiconductor substrate, and use the source of the field effect transistor (Source) to The storage node of the capacitor is connected to form a memory cell of the dynamic random access memory. The row decoder of the peripheral circuit (Row Decorder) uses word lines and field effect transistors to selectively access the memory cells, and the row decoder (Column Decorder) and the read / write circuit (Read / ffrite Circuit) use binary information ( Binary Information) is stored in the capacitor in the form of charge. In recent years, the packing density of dynamic random access memory (Packing Density) has increased rapidly. For example, there are currently about 64 million memory cells in a die. It is estimated that by 1998,-one die will reach 2560G00GG Memory cell. In order to increase the capacitor area of the dynamic random access memory, some special stacked capacitor structures, such as the fin type (Fin) of Japan Fujitsu Company and the crown type (Crown) of Japan Mitsubishi Company, have appeared successively. Y. Park et al. Also disclosed a "knife and fork type" capacitor charge storage electrode (Capacitor With Fork-Shaped Storage Node) in US Patent No. 5332685. However, this [knife and fork type] charge storage electrode structure requires An additional circuit design rule (Ground Design Rule) limits the area of the memory cell. I u HI ^^^ 1 m 1 I— 1. i-«1-»-0¾-= ° (please read the precautions on the back and then fill out this page) 圂 纸 垠 Scale: Chinese National Standard Falcon (CNS ; Μ specifications ;: !! 0. < 2W male t
本發明揭露了一種動態隨機存取記憶體（Dynamic Random Access Memory ; DRAM )之電容器的製造方法，此電 容器具有呈【柱型】結構之電荷儲存電極（Storage Node) ’能大幅增加電容器的電容値並縮小記憶元的面積。 问時’本方法僅需一道微影光罩（Photomask)即可同時形成 【源極接觸窗】與電容器的【電荷儲存電極】，而傳統方法 則需兩道微影光罩（Photomask)才能形成源極接觸窗與電容 器的電荷儲存電極。由於本發明方法能節省一道微影光罩 (Photomask)，因此，能降低生產成本，增進經濟效益，提 高產業競爭力，這一點對已經進入白熱化競爭的全世界半導 體工業，相當重要。 3·發明之簡要說明 本發明之目的是提供一種在有限的電路佈局（Circuit Layout)面積內提高動態隨機存取記憶體之電容値的電容器 製程。 本發明之另一個目的是提供一種【低生產成本】的動態 隨機存取記憶體的製造方法。 哩齊部申，^嘌^巧-:^--^费^^^卞裝 rk-- (請先閱讀背面之注意事項再填寫本頁) 本發明之另一個目的是提供一種以【複晶矽柱】作爲電 荷儲存電極（Storage Node)的動態隨機存取記憶體之電容 器的結構。 本發明之另一個目的是提供一種製造複晶砂柱的方法。 茲以六仟四佰萬位元（64MB)堆疊式動態隨機存取記憶 體（Stack Dynamic Random Access Memory ; Stack DRAM) 結構爲例，說明本發明之主要製程： a.在矽半導體基板上形成隔離電性活動區（Active Area)所 本紙張尺度適用中國國家榡準（CNS M4規格（210X297公麈 一叶- Λ7 B7 五、昏明説明（3) 需的場氧化層（Field Oxide); b. 形成場效電晶體，所述【場效電晶體】包含有閘氧化層 (Cate Oxide)、閘電極（Gate Electrode)與源極/汲極 (Source/Drain); c. 沈積一層【第一絕緣層】、【第二絕緣層】與【第三絕緣 層】，並利用化學機械式拋光技術（Chemical Mechanical Polishing ; CMP)將所述【第三絕緣層】平坦化； d. 利用傳統的微影技術制定源極接觸窗（Node Contact)的 光阻圖案（Photoresist Pattern); e. 利用電紫飽刻技術【單向性】的（Anisotropically)触去 所述【第三絕緣層】、【第二絕緣層】與【第一絕緣 層】，以形成源極接觸窗（Node Contact); f. 沈積一層【第一複晶矽層】，所述第一複晶矽層將塡滿所 述【源極接觸窗】； g. 利用電漿蝕刻技術【單向性】的對所述【第一複晶矽層】 進行回蝕刻（Etchback)，所述回蝕刻終止於所述【第三 絕緣層】之表面； h. 利用稀釋氫氟酸溶液（Diluted HF)對第一複晶矽層及第 二、三絕緣層之蝕刻率之不同去除所述【第三絕緣層】， 【柱型】之電容器電荷儲存電極（Storage Node)於焉形 成； i. 形成一層極薄的電容器介電層（Capacitor Dielectric); j.沈積一層【第二複晶矽層】，並利用微影與電漿蝕刻技術形成| 電容器的上層電極（Plate Electrode)。 丨 ---------ik— (請先閱讀背面之注意事項再填寫本f) 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0,< 297公慶) 經奇邹"·々噤4苟4-","*"卞泛 五、發明説明（4) 4·圖示的簡要說明 圖^ 是先前技藝（Prior Art )，圖一至圖十是本發明之實 施例的製程剖面圖。 圖一是形成場效電晶體後的製程剖面圖； 圖二是沈積【第一絕緣層】與【第二絕緣層】後的製程剖面 圖； 圖三是沈積【第三絕緣層】並使之【平坦化】後的製程剖面 圖； 圖四是利用電漿飽刻技術【單向性的】蝕去所述【第三絕緣 層】、【第二絕緣層】與【第一絕緣層】以形成源極接 觸窗後的製程剖面圖； 圖五是沈積一層【攙雜的第一複晶砂層】後的製程剖面圖， 所述攙雜的第一複晶矽層將塡滿所述【源極接觸窗】； 圖六是利用電漿蝕刻技術【單向性的】對所述攙雜的第一複 晶矽層進行「回蝕刻」後的製程剖面圖； 圖七是利用稀釋氫氟酸溶液（Diluted HF)除去所述【第三 絕緣層】後的製程剖面圖，以形成【柱型】之電容器 電荷儲存電極； 圖八是在電容器的【電荷儲存電極】表面形成一層厚度極薄 的【電容器介電層】和【第二複晶矽層】後的製程剖面 圖； 圖九是利用微影與電漿鈾刻技術製定電容器之上層電極 (Top Plate)，完成動態隨機存取記憶體之電容器後 的製程剖面圖； 圖十是形成位元線接觸窗（Bit Line c〇ntact)和位元線後 本紙張尺度適用中國國家標隼（CNS ) A4規格（21()x 297公釐） 一— ^------訂 (請先閱讀背面之注意事項再填寫本頁) A 7 _B7 五、發明説明（f) 的製程剖面圖。 圖十一是六仟四佰萬位元（64MB)堆疊式動態隨機存取記憶 體結構的先前技藝（Prior Art)的製程剖面圖，其 各層次的編號跟本發明實施例之各層次編號的說明相 同，亦即，【電荷儲存電極10A】、【電容器介電層 • 11】與上層電極 12 (Plate Electrode)。 5·發明之實施例 經濟部中失螵4¾¾二濞f合咋;t.?uThe invention discloses a method for manufacturing a dynamic random access memory (Dynamic Random Access Memory; DRAM) capacitor, which has a charge storage electrode (Storage Node) with a "pillar type" structure, which can greatly increase the capacitance value of the capacitor And reduce the area of memory cells. Ask the question 'This method only needs one photomask to form the [source contact window] and the capacitor [charge storage electrode], while the traditional method requires two photomasks to form The source contact window and the charge storage electrode of the capacitor. Since the method of the present invention can save a photomask, it can reduce production costs, increase economic benefits, and increase industrial competitiveness. This is very important for the semiconductor industry in the world that has entered the fierce competition. 3. Brief description of the invention The object of the present invention is to provide a capacitor process for improving the capacitance value of a dynamic random access memory within a limited circuit layout area. Another object of the present invention is to provide a [low production cost] manufacturing method of dynamic random access memory. Li Qibu Shen, ^ Pur ^ Qiao-: ^-^ fee ^^^ Bian installed rk-- (please read the notes on the back before filling this page) Another purpose of the present invention is to provide a Silicon pillar] The structure of the capacitor of the dynamic random access memory as the storage node. Another object of the present invention is to provide a method for manufacturing polycrystalline sand columns. Take 64 million megabits (64MB) stack dynamic random access memory (Stack Dynamic Random Access Memory; Stack DRAM) structure as an example to illustrate the main process of the present invention: a. Formation of isolation on a silicon semiconductor substrate The paper size of the electrical active area (Active Area) is applicable to the Chinese National Standard (CNS M4 specification (210X297 public leaf one leaf-Λ7 B7. V. Bright description (3) Field Oxide) required; b. Form a field effect transistor, the [field effect transistor] includes a gate oxide layer (Cate Oxide), gate electrode (Gate Electrode) and source / drain (Source / Drain); c. Deposit a layer of [first insulation Layer], [second insulating layer] and [third insulating layer], and using chemical mechanical polishing technology (Chemical Mechanical Polishing; CMP) to flatten the [third insulating layer]; d. Using traditional lithography Technically formulate the photoresist pattern of the source contact window (Node Contact); e. Use the electric violet saturation technology [Unidirectional] (Anisotropically) to touch the [Third Insulation Layer], [Second Insulation layer] and [first insulation layer To form a source contact window (Node Contact); f. Deposit a layer of [first polycrystalline silicon layer], the first polycrystalline silicon layer will fill the [source contact window]; g. Use plasma Etchback is performed on the [first polycrystalline silicon layer] by etching technology [unidirectional], and the etchback is terminated on the surface of the [third insulating layer]; h. Using diluted hydrofluoric acid The solution (Diluted HF) removes the difference between the etching rate of the first polycrystalline silicon layer and the second and third insulating layers [Third Insulating Layer], [pillar type] capacitor charge storage electrode (Storage Node) is formed in Yan ; I. Forming a very thin capacitor dielectric layer (Capacitor Dielectric); j. Depositing a layer [second polycrystalline silicon layer], and using lithography and plasma etching technology to form | capacitor upper electrode (Plate Electrode).丨 --------- ik— (Please read the precautions on the back before filling in this f) The size of the revised paper is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0, < 297 Gongqing) Qi Zou " · 々 噤 4 Gou 4- ", " * " Bian Pan V. Description of invention (4) 4. Simplified illustration ^ Previously described FIG art (Prior Art), is a view of a ten to a solid cross-sectional views of the embodiment of the present invention is applied. Figure 1 is a cross-sectional view of the process after the field effect transistor is formed; Figure 2 is a cross-sectional view of the process after depositing the [first insulating layer] and [second insulating layer]; Figure 3 is the deposition and making of the [third insulating layer] [Planarization] The cross-sectional view of the manufacturing process; Figure 4 is the use of plasma saturation etching technology [unidirectional] to etch away the [third insulating layer], [second insulating layer] and [first insulating layer] to Process profile after forming the source contact window; Figure 5 is a process profile after depositing a layer of [doped first polycrystalline sand layer], the doped first polycrystalline silicon layer will fill the [source contact Window]; FIG. 6 is a cross-sectional view of the process after “etching back” the doped first polycrystalline silicon layer using plasma etching technology [unidirectional]; FIG. 7 is a diluted hydrofluoric acid solution (Diluted) HF) A cross-sectional view of the process after removing the [third insulating layer] to form a [pillar type] capacitor charge storage electrode; FIG. 8 is to form a thin layer of [capacitor dielectric] on the surface of the capacitor [charge storage electrode] Electric layer] and [second polycrystalline silicon layer] Process cross-sectional view; Figure 9 is a process cross-sectional view after the use of lithography and plasma uranium engraving technology to formulate the top electrode of the capacitor (Top Plate) to complete the dynamic random access memory capacitor; Figure 10 is the formation of bit line contact window (Bit Line c〇ntact) and bit line after the paper size is applicable to the Chinese National Standard Falcon (CNS) A4 specifications (21 () x 297 mm) a-^ ------ order (please read the back of the first (Notes and then fill out this page) A 7 _B7 5. Process description of invention description (f). FIG. 11 is a process cross-sectional view of a prior art (Prior Art) process structure of a 64-million-bit (64MB) stacked dynamic random access memory structure. The number of each level is the same as the number of each level in the embodiment of the present invention. The explanation is the same, that is, [charge storage electrode 10A], [capacitor dielectric layer • 11] and upper electrode 12 (Plate Electrode). 5. Examples of inventions: Lost in the Ministry of Economic Affairs
In - -* «H - I— I ^ - —ΙΪ -· -¾ .’V5 (請先閱靖背面之注意事項再填薄本f ) 參考圖一。首先，在電阻値2.5 〇hm-cm、晶格方向 (100)的P型矽半導體基板1上形成場氧化層2，所述 【場氧化層2】之厚度介於3000埃到6000埃之間，然 後，再形成場效電晶體，所述「場效電晶體」包含有閘氧化 層3、閘電極4 (Gate Electrode)與N+源極/汲極6 (Source/Drain);形成所述閘電極4時，亦同時形成動態 隨機存取記憶體之字語線（Wordline)。所述【閘氧化層 3】係以熱氧化砍半導體基板而形成，其厚度介於50到150 埃之間。所述【閘電極4】係以低壓化學氣相沉積法（Low Pressure Chemical Vapor Deposition ; LPCVD)形成之複 晶矽或複晶矽化物4，其總厚度介於1000到3000埃之 間。接著，以低壓化學氣相沉積法形成二氧化矽層5，其厚 度介於1000到2000埃之間，再利用電漿蝕刻技術制定所 述二氧化矽5與複晶矽或複晶矽化物4的圖案。所述Γ 源極/汲極6係使用砷離子（AS75)或磷離子(p31)進行離 子佈値而成，其離子佈値劑量介於1E13到1E14原子/平方 公分之間，離子佈値能量則介於10到80 kev之間，場效 電晶體的製作，於焉完成。 本紙張尺度通用中國國家標準（CNS ) A4規格（210 X 297公釐） -7- ^^€483 a? B7 五、發明説明（Z) 接著，沈積一層【第一絕緣層7】與【第二絕緣層 8】，如圖二所示，所述【第一絕緣層7】一般是以低壓化學 氣相沉積法形成之二氧化砂（s丨1 icon D1 ox ide ) ’厚度介於 500到1500埃之間；所述【第二絕緣層8】則通常是以低 壓化學氣相沉積法形成之氮化砂（Silicon Nitride)，其反 應氣體是NH3和SiH4 ’反應溫度約76G°C，反應壓力約 350 mtorr，厚度介於500到1500埃之間。 接著，沈積一層【第三絕緣層9】’所述【第三絕緣層 9】通常是以大氣壓化學氣相沉積法（AtmosPhere Pressure Chemical Vapor Deposition ; APCVD)形成之棚鱗玻璃薄膜 (Boro-PhosphoSilicate Glass ; BPSG)，其反應壓力約 760 mtorr，反應溫度約400°C ’反應氣體爲Si(CH3)4 2056 seem、TMB 46 seem、 TMP 62 seem 與 N〗1314 seem ,剛兀 .^'^^-'^^tllnv!^:*^^^^'·^ (請先閱讀背面之注意事項再填寫本f ) 成沉積時之厚度介於50⑼到100Q0埃之間，並以熱流整技 術（Thermal Flow)使所述硼磷玻璃薄膜9平坦 (Planarized)，如圖三所示。除了利用熱流整技術將所述 硼磷玻璃薄膜Θ平坦化外，也可以利用習用的化學機械式拋 光技術（Chemical Mechanical Polishing ; CMP)將所述 【第三絕緣層9】平坦化。 接著，塗佈一層光阻（Photoresist)，並利用傳統的微 影技術制定所述源極接觸窗（Node Contact)的光阻圖案， 然後利用電漿蝕刻技術單向性的蝕去所述【第三絕緣層 9】、【第二絕緣層8】與【第一絕緣層7】，以形成源極接 觸窗’如圖四所示。所述電漿蝕刻可以是磁場增強式活性離 子式電紫触刻（Magnetic Enhanced Reactive On 本紙張尺度適用中國國家標準,:CNS ) A4規格（210:< 297公缝) ~ ' ' -S - B7 B7 •崎洚部""嘌4^1二消旁-咋吐;,,.5^ 五、發明説明（γ)In--* «H-I— I ^-—ΙΪ-· -¾ .’V5 (Please read the precautions on the back of Jing Jing before filling in this f) Refer to Figure 1. First, a field oxide layer 2 is formed on a P-type silicon semiconductor substrate 1 with a resistance value of 2.5 ohm-cm and a lattice direction (100). The thickness of the [field oxide layer 2] is between 3000 angstroms and 6000 angstroms. Then, the field effect transistor is formed again. The "field effect transistor" includes the gate oxide layer 3, the gate electrode 4 (Gate Electrode) and the N + source / drain 6 (Source / Drain); forming the gate At the time of the electrode 4, a word line of dynamic random access memory is also formed at the same time. The [gate oxide layer 3] is formed by thermally oxidizing a semiconductor substrate, and has a thickness between 50 and 150 angstroms. The [gate electrode 4] is a polycrystalline silicon or polycrystalline silicide 4 formed by Low Pressure Chemical Vapor Deposition (LPCVD), and its total thickness is between 1000 and 3000 angstroms. Next, the silicon dioxide layer 5 is formed by low-pressure chemical vapor deposition with a thickness between 1000 and 2000 angstroms, and then the plasma dioxide technique is used to formulate the silicon dioxide 5 and the polycrystalline silicon or polycrystalline silicide 4 picture of. The Γ source / drain electrode 6 is made of arsenic ions (AS75) or phosphorous ions (p31) for ion distribution. The ion distribution dose is between 1E13 and 1E14 atoms / cm2. The ion distribution energy Between 10 and 80 kev, the production of field effect transistors was completed by Yan Yan. The size of this paper is common to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -7- ^^ € 483 a? B7 5. Description of the invention (Z) Next, deposit a layer of [First Insulation Layer 7] and [No. The second insulating layer 8], as shown in Figure 2, the [first insulating layer 7] is generally formed by low-pressure chemical vapor deposition of sand dioxide (s 丨 1 icon D1 ox ide) 'thickness between 500 to Between 1500 Angstroms; The [Second Insulation Layer 8] is usually silicon nitride sand (Silicon Nitride) formed by low-pressure chemical vapor deposition. The reaction gas is NH3 and SiH4. The pressure is about 350 mtorr and the thickness is between 500 and 1500 Angstroms. Next, a layer of [third insulating layer 9] is deposited [the third insulating layer 9] is usually a greenhouse scale thin film (Boro-PhosphoSilicate Glass; AtmosPhere Pressure Chemical Vapor Deposition; APCVD) formed by atmospheric pressure chemical vapor deposition (APMOS); BPSG), the reaction pressure is about 760 mtorr, the reaction temperature is about 400 ° C 'The reaction gas is Si (CH3) 4 2056 seem, TMB 46 seem, TMP 62 seem and N〗 1314 seem, rigid. ^' ^^-' ^^ tllnv! ^: * ^^^^ '· ^ (Please read the precautions on the back before filling in this f) The thickness of the deposit is between 50⑼ and 100Q0 Angstrom, and the thermal flow technology (Thermal Flow) Planarized the borophospho glass film 9 as shown in FIG. 3. In addition to flattening the borophosphoglass thin film Θ by heat flow rectification, the [third insulating layer 9] can also be flattened by conventional chemical mechanical polishing (CMP). Next, coat a layer of photoresist, and use traditional photolithography technology to formulate the photoresist pattern of the source contact (Node Contact), and then use plasma etching technology to unidirectionally etch the Three insulating layers 9], [second insulating layer 8] and [first insulating layer 7] to form a source contact window 'as shown in FIG. 4. The plasma etching may be a magnetic field enhanced active ion electric violet touch (Magnetic Enhanced Reactive On, the paper scale is applicable to the Chinese national standard ,: CNS) A4 specification (210: < 297 male slit) ~ '' -S- B7 B7 • Qizhangbu " " Purine 4 ^ 1 second elimination side-spit; ,,. 5 ^ V. Description of invention (γ)
Etching ; MERIE)或電子迴旋共振電漿蝕刻（Electron Cyclotron Resonance ; ECR)或傳統的活性離子式電漿鈾刻 技術（Reactive On Etching ; RIE )，以美國 Lam Research公司所生產之RAINBOW 4500磁場增強式活性離 子式電漿蝕刻機器爲例，蝕刻條件設定爲反應室壓力300 mtorr、射頻功率1250 watts、反應氣體流量CF4 25 seem ' CHF3 25 seem、Ar 250 seem ° 接著，沈積一層攙雜的第一複晶矽層10 (Doped Polysilicon)，所述【第一複晶砍層10】將塡滿所述【源 極接觸窗】，如圖五所示。所述【第一複晶矽層1〇】係以同 步攙雜（In-situ Doped)之低壓化學氣相沉積法形成’反應 氣體是（15% PH3/85% SiH4)與（5% PH3/95% N2)的混合氣 體，反應溫度是570°C。所述【第一複晶矽層10】之厚度由 所述【源極接觸窗】之寬度來決定，-仟六佰萬位元 (16MB)或六仟四佰萬位元（64MB)堆疊式動態隨機存取記 憶體之【源極接觸窗】的寬度介於0.25到0.5微米之間’ 因此，所述【第一複晶矽層10】之厚度介於1500到2500 埃之間。接著，利用電漿鈾刻技術單向性的 (Anisotropically )對所述【第一複晶砍層10】進行回飽 刻（Etchback)，所述【回蝕刻】終止於所述所述【第三絕 緣層9】之表面，以去除所述【第三絕緣層9】表面之【第 一複晶矽層10】，而僅在所述【源極接觸窗】內保留有所述 【第一複晶矽層10A】，如圖六所示。以美國Lam Research 公司所生產之RAINBOW 4400磁場增強式活性離子式電漿飽 刻機器爲例，所述回蝕刻之蝕刻條件設定爲反應室壓力525 m nv^i Λί m n^i Am· ml mfl mV ‘ - 1 (請先閱讀背面之注意事項再填寫本頁) 本泜張尺度適用中國國家標準（CNS ) A4規格(210X 2W公釐） 超濟·坪中^;ΑΪ"1、-消资"'"吐.F,a ^6483 at _ B7 五、發明説明（J) mtorr、射頻功率45G watts、反應氣體流量He 180 seem、Cl2 420 seem、HBr 80 seem。 接著，利用稀釋氫氟酸溶液（Diluted HF)去除所述 【第三絕緣層9】，以露出所述【源極接觸窗】內之所述 【第一複晶矽層10A】，如圖七所示。所述攙雜的第一複晶 矽層10A呈【柱型】，構成了電容器的電荷儲存電極 (Storage Node)，提供比傳統電容器（請參考圖^一)更 大的電容（Capacitance)，也比傳統方法節省一道光罩 (Mask )，降低生產成本，提高產業經濟效益。 最後，在所述電容器的【電荷儲存電極10A】表面形成 一層厚度極薄的【電容器介電層〗1】和【第二複晶矽層 12】，如圖八所示。所述【第二複晶矽層12】之形成方法跟 所述【第一複晶矽層10】形成方法相同，其厚度介於1000 埃到2000埃之間。最後，利用微影與電漿蝕刻技術鈾去所 述【電容器介電層11】和【第二複晶矽層12】，以製定電 容器之上層電極12 (Plate Electrode)圖案，便完成Γ動 態隨機存取記憶體之電容器，如圖九所示。完成電容器的製 作後，便進行傳統位元線製程（Bi t Line Contact Pr〇cess)，沈積二氧化矽層13，並以習用的熱流整技術 (Thermal Flow)或化學機械式拋光技術（Chemical Mechanical Polishing ; GJP)使所述二氧化矽層13平坦 (Planarized)，再利用微影與電漿鈾刻技術形成位元線接 觸窗（Bit Line Contact)，再形成位元線14，如圖十所 示。 所述【柱型】電容器結構在所述【源極接觸窗】之尺寸 良‘戒張尺度連用中國國家標準（CNS ) A4規格（210X297公釐） —I I I I I I I n n 訂 I "^、i (請先閱讀背面之注意事項再填寫本頁) A7 Βη 五、發明説明（，） 極爲狹窄的情況下，增加了電容器的表面積，因而提高了動 態隨機存取記憶體之電容値，達到記憶體之高集積化（High Packing Density)之目的。甚至依據微影技術，可在有限空 間中放置數個圓柱以增加電容器的面積。同時，本方法僅需 一道微影光罩（Photomask)即可同時形成源極接觸窗（Node Contact)與電容器的電荷儲存電極（Storage Node)，因 此，能降低生產成本，增進經濟效益，提高產業競爭力，這 一點對已經進入白熱化競爭的全世界半導體工業，非常重 要。反之，傳統方法則需【兩道微影光罩】才能形成【源極 接觸窗】與電容器的【電荷儲存電極】，如圖十一所示，除 了電容値很小而無法形成高密度之動態隨機存取記憶體以 外，其高昂的生產成本亦不利於產業競爭力。 以上係利用最佳實施例來闡述本發明，而非限制本發 明，並且，熟知半導體技藝之人士皆能明瞭，適當而作些微 的改變及調整，仍將不失本發明之要義所在，亦不脫離本發 明之精神和範圍。 n I n m tit m n —ΐ^- -- n - - m T 、-° (請先閱讀背面之注意事項再4寫本w ) 經濟部中央標進局員工消費合作杜印掣 ^紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 29*7公釐 -tl'Etching; MERIE) or electron cyclotron resonance plasma etching (Electron Cyclotron Resonance; ECR) or traditional reactive ion plasma uranium engraving technology (Reactive On Etching; RIE). An example of a reactive ion plasma etching machine is that the etching conditions are set to 300 mtorr in the reaction chamber, 1250 watts of RF power, and CF4 25 seem 'CHF3 25 seem, Ar 250 seem °. Next, deposit a layer of doped first polycrystal In the silicon layer 10 (Doped Polysilicon), the [first polycrystalline cutting layer 10] will fill the [source contact window], as shown in FIG. 5. The [first polycrystalline silicon layer 10] is formed by synchronous doping (In-situ Doped) low-pressure chemical vapor deposition method. The reaction gas is (15% PH3 / 85% SiH4) and (5% PH3 / 95 % N2), the reaction temperature is 570 ° C. The thickness of the [first polycrystalline silicon layer 10] is determined by the width of the [source contact window], -60 million bits (16MB) or 64 million bits (64MB) stacked The width of the [source contact window] of the dynamic random access memory is between 0.25 and 0.5 microns. Therefore, the thickness of the [first polycrystalline silicon layer 10] is between 1500 and 2500 angstroms. Next, anisotropically using plasma uranium engraving technology to perform an Etchback on the [first polycrystalline cutting layer 10], the [etching back] terminates on the [third The surface of the insulating layer 9 to remove the [first polycrystalline silicon layer 10] on the surface of the [third insulating layer 9], but the [first complex] remains only in the [source contact window] Crystal silicon layer 10A], as shown in Figure 6. Taking the RAINBOW 4400 magnetic field enhanced active ion plasma saturation engraving machine produced by Lam Research in the United States as an example, the etching conditions of the etch back are set to the reaction chamber pressure 525 m nv ^ i Λί mn ^ i Am · ml mfl mV '-1 (Please read the precautions on the back before filling this page) This standard is applicable to the Chinese National Standard (CNS) A4 specification (210X 2W mm) Chaoji · Pingzhong ^; ΑΪ " 1, -Consumer " '" Spit. F, a ^ 6483 at _ B7 V. Description of the invention (J) mtorr, RF power 45G watts, reaction gas flow He 180 seem, Cl2 420 seem, HBr 80 seem. Next, the [third insulating layer 9] is removed using a diluted hydrofluoric acid solution (Diluted HF) to expose the [first polycrystalline silicon layer 10A] in the [source contact window], as shown in FIG. 7 As shown. The doped first polycrystalline silicon layer 10A has a [pillar shape], which constitutes a charge storage electrode (Storage Node) of a capacitor, and provides a larger capacitance (Capacitance) than a conventional capacitor (please refer to FIG. 1). The traditional method saves a mask (Mask), reduces production costs, and improves the economic efficiency of the industry. Finally, a layer of [thin capacitor dielectric layer 1] and [second polycrystalline silicon layer 12] of extremely thin thickness are formed on the surface of the [charge storage electrode 10A] of the capacitor, as shown in FIG. 8. The forming method of the [second polycrystalline silicon layer 12] is the same as the forming method of the [first polycrystalline silicon layer 10], and its thickness is between 1000 angstroms and 2000 angstroms. Finally, using lithography and plasma etching technology to remove the [capacitor dielectric layer 11] and [second polycrystalline silicon layer 12] uranium to develop the pattern of the upper electrode 12 (Plate Electrode) of the capacitor to complete the Γ dynamic randomization The capacitor for accessing the memory is shown in Figure 9. After the production of the capacitor is completed, the traditional bit line contact process (Bi t Line Contact Pr cess) is performed, the silicon dioxide layer 13 is deposited, and the conventional thermal flow technology (Thermal Flow) or chemical mechanical polishing technology (Chemical Mechanical Polishing; GJP) to make the silicon dioxide layer 13 flat (Planarized), and then use lithography and plasma uranium engraving technology to form a bit line contact (Bit Line Contact), and then form a bit line 14, as shown in Figure 10 Show. The [pillar type] capacitor structure is good in the size of the [source contact window] or the scale of the Chinese National Standard (CNS) A4 specification (210X297 mm) —IIIIIII nn order I " ^, i (please (Read the precautions on the back before filling in this page) A7 Βη V. Description of the invention (,) Under extremely narrow conditions, the surface area of the capacitor is increased, thus increasing the capacitance value of the dynamic random access memory to reach the height of the memory The purpose of accumulation (High Packing Density). Even according to the lithography technology, several cylinders can be placed in a limited space to increase the area of the capacitor. At the same time, this method only needs a photomask to form the source contact (Node Contact) and the charge storage electrode (Storage Node) of the capacitor, so it can reduce production costs, increase economic benefits, and improve industry Competitiveness is very important for the worldwide semiconductor industry that has entered fierce competition. On the contrary, the traditional method requires [two lithography masks] to form the [source contact window] and the [charge storage electrode] of the capacitor, as shown in FIG. In addition to random access memory, its high production costs are not conducive to industrial competitiveness. The above uses the best embodiments to explain the present invention, not to limit the present invention, and those familiar with semiconductor technology can understand that appropriate and slight changes and adjustments will still not lose the essence of the present invention, nor Departs from the spirit and scope of the present invention. n I nm tit mn — l ^--n--m T,-° (please read the precautions on the back first and then 4 copies w) Employee consumption cooperation of the Central Standardization Bureau of the Ministry of Economic Affairs Du Yinji ^ The paper size is applicable to China Standard (CNS) Λ4 specification (210X 29 * 7mm-tl '