312834 經濟部中央樣準局員工消費合作社印裝 A7 B7 五、發明説明（） 1 _發明之技術領域 本發明是關於積體電路之動態隨機存取記億體之電容器的的製造方法’特別是 關於堆疊式動態隨機存取記憶體之電容器的的製造方法。 2·發明背景 典型的動態隨機存取記憶體是在矽半導體晶圓上製造一個金氧半場效電晶體與 電容器，所述金氧半場效電晶體是作爲轉移閘電晶體（transferred gate transistor) ’ 並利用所述轉移閘電晶體的源極來連接電容器的下層電極以形成動態隨機存取記憶 體的記億元。數目龐大的記億元聚集成爲記億元陣列。其中’所述轉移閘電晶體的 源極跟電容器作電性接觸，數位資訊儲存在電容器內’並藉著所述轉移閘電辱體、 位元線和字語線陣列來取得儲存在電容器內的數位資訊.。另一方面，在記憶元陣列 的附近則有其它電路圍繞，例如感測放大器等電路，這些外部電路’稱爲週邊電路 區域（peripheral circuit)。因此，要達到動態隨機存取記憶體之尚積集密度的目的， 必需縮小記憶體之記憶元的尺寸，然而電容器尺寸的縮小會降低電容値’使得記憶 體電路的訊號/雜訊（Signal Noise ; S/N)比例降低’造成電路誤判或電路不穩定等 缺點。職是之故，爲了達成高積集密度的動態隨機存取記億體，必需尋找更尖端的 製程技術，以在降低記憶元之平面電路佈局面積之同時，能夠維持或增加電容器之 電容値° 電容的公式是C= εΑ/Τ，其中，ε是電容器介電層（capacitor dielectric)之介 電常數，A是電容器下層電極之表面積，T是電容器下層電極之厚度，因此，要增加 電容器之電容可以從兩個方向著手，第一個方向是採用高介電常數的材料作爲電容 器介電層，£!!如，Ta2〇5、Ti02和SrTi03材料都具有非常高的介電常數，可惜， 由於這些高巧電常數的材料之薄膜品質不佳，存在有絕緣層的奔潰電壓等可靠性問 題，因此到目前爲止還無法應用到動態隨機存取記憶體。 使用高介電常數的電容器介電層既然不甚可行，吾人由電容的公式C= εΑ/Τ 可知電容的大小跟電容器下層電極之表面積成正比，因此，增加電容器下層電極之 表面積是增加電容器之電容的另一個方向，而目前最普遍的是所謂三度空間電容器 (3-D capacitor )。所述三度空間電容器是在所述轉移閘電晶體之上方或下方的第三 度空間形成電容器，以在有限的平面電路佈局面積內增加電容器之電容値。電容器 製造在所述轉移閘電晶體之上方時，稱爲堆疊式電容器（stack capacitor)，而電容 器製造在所述轉移閘電晶體之下方時稱爲凹溝式電容器（trenchcapacitor)。目前， 動態隨機存取記憶體工業主要是使用堆疊式電容器結構，例如，日本和韓國的半導 體公司主要是採用堆疊式電容器結構。312834 Printed A7 B7 by the Employees ’Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs 5. Description of the invention () 1 _Technical field of the invention The present invention relates to the manufacturing method of dynamic random access capacitors for integrated circuits, especially A method for manufacturing a capacitor of a stacked dynamic random access memory. 2. Background of the Invention A typical dynamic random access memory is to fabricate a metal oxide half field effect transistor and a capacitor on a silicon semiconductor wafer. The metal oxide half field effect transistor is used as a transferred gate transistor. And the source electrode of the transfer gate transistor is used to connect the lower electrode of the capacitor to form a billion yuan of dynamic random access memory. A huge number of billions of dollars is gathered into an array of billions of dollars. Where 'the source of the transfer gate transistor makes electrical contact with the capacitor, and the digital information is stored in the capacitor' and is stored in the capacitor by the array of the transfer gate electric body, bit line and word line Digital information. On the other hand, there are other circuits around the memory cell array, such as sense amplifier circuits. These external circuits are called peripheral circuits. Therefore, to achieve the purpose of still accumulating density of dynamic random access memory, it is necessary to reduce the size of the memory cell. However, the reduction in the size of the capacitor will reduce the capacitance value so that the signal / noise (signal noise) of the memory circuit ; S / N) ratio reduction 'causes shortcomings such as circuit misjudgment or circuit instability. The reason is that in order to achieve a high accumulation density of dynamic random access memory, it is necessary to find more advanced process technology to reduce or reduce the planar circuit layout area of the memory cell while maintaining or increasing the capacitance value of the capacitor ° The formula for capacitance is C = εΑ / Τ, where ε is the dielectric constant of the capacitor dielectric layer, A is the surface area of the lower electrode of the capacitor, and T is the thickness of the lower electrode of the capacitor, therefore, the capacitance of the capacitor should be increased You can start from two directions. The first direction is to use high dielectric constant materials as capacitor dielectric layers. For example, Ta205, Ti02, and SrTi03 materials all have very high dielectric constants. Unfortunately, because The thin films of these high-electric constant materials have poor quality and reliability problems such as burst voltage with an insulating layer, so they have not been able to be applied to dynamic random access memory so far. Since the use of high dielectric constant capacitor dielectric layers is not feasible, we can see from the formula of capacitance C = εΑ / Τ that the size of the capacitor is proportional to the surface area of the lower electrode of the capacitor. Therefore, increasing the surface area of the lower electrode of the capacitor is to increase the capacitor. The other direction of capacitance, and the most common at present is the so-called 3-D capacitor. The three-dimensional space capacitor forms a capacitor in the third-degree space above or below the transfer gate transistor to increase the capacitance value of the capacitor within a limited planar circuit layout area. When the capacitor is fabricated above the transfer gate transistor, it is called a stack capacitor, and when the capacitor is fabricated below the transfer gate transistor, it is called a trench capacitor. At present, the dynamic random access memory industry mainly uses stacked capacitor structures. For example, semiconductor companies in Japan and South Korea mainly use stacked capacitor structures.
Watanabe 等人於 IEDM 1988 年第 600 頁所發表之「stacked capacitor cells for high density dynamic RAMs」與 Wakamiya 等人於 VLSI Technology 1989 第 69 頁所發表之 「novel stacked capacitor cell for 64 Mb DRAM」均揭露了堆疊式電容器結構。S. Kimura等人的美國專利第4742018號和T.Ema美國專利4977102號亦揭露堆疊式電 2 本纸張尺度適用中國國家標车（CNS ) A4说格（210X297公釐） tut ^m— an— ml m «ml mu ff^i— 龟 (請先閱讀背而之注意事項再填寫本萸) A7 B7 經濟部中央樣準局員工消費合作社印裝 五、發明説明（） 容器以增加電容器電容。日本富士通公司的Masao Taguchi等人在美國專利第 5〇21357號更揭露了改良的堆疊式電容器結構，稱爲鰭型電容器結構（fln capacitor)，大幅增加電容器電容，提高動態隨機存取記億體之集積密度。曰本 Hitachi公司的T. Kaga等人更在1994年IEDM第927頁之一篇題目爲「A 0.29 um2 ΜΙΜ-CROWN cell and process technology for 1-Gigabit DRAMs」的論文，揭露了一種 更爲先進的稱爲「ΜΙΜ-CROWN結構」的堆疊式電容器，這些電容器結構均能大幅 增加電容器的電容値，提高動態隨機存取記憶體元件之集積密度。 3·發明之簡要說明 本發明的主要目的是提供一種能增加電容之堆疊式電容器的製造方法。 本發明的另一個目的是提供一種高集積密度之堆疊式動態隨機存取記憶體的製 造方法。 兹簡述本發明之主要方法如下。首先，以標準製程在矽半導體晶圓上形成隔離 金氧半場效電晶體所需要的場氧化層，接著，形成金氧半場效電晶體和字語線 (wordline)。接著，接著，沈積一層第一介電層與第二介電層，並利用化學機械式 琢磨技術平坦化所述第二介電層。接著，利用微影技術與電漿蝕刻技術蝕刻所述第 一介電層與第二介電層以露出所述金氧半場效電晶體之源極，以形成記億元接觸窗 (node contact)。接著，沈積一層第一複晶矽，然後，沈積一層第三介電層。所述 第三介電層是利用低壓化學氣相沉積法形成之氮化矽，其功用是作爲後續抗氧化 罩。接著，形成點狀的複晶矽半球型晶粒（dotHemi-Spherical Grain ; dotHSG)。 然後，身刻所述第三介電層，同時也蝕刻掉一部份的所述複晶矽半球型晶粒， 然後.，氧化所述複晶矽半球型晶粒和第一複晶矽，使所述複晶矽半球型晶粒成爲複 晶政氧化層（poly-oxide)，也使一部份的所述第一複晶砂成爲複晶砂氧化層。接 著，去除所述複晶矽氧化層，以在所述第一複晶矽表面形成溝槽，再去除所述第三 介電層。 .. : 接著，利用微影技術形成光阻圖案，然後，利用電漿蝕刻技術對所述第一複晶 矽進行蝕刻，以定義電容器之下層電極的圖案。去除所述光阻圖案後，具溝槽的電 容器的下層電極於焉形成。所述具溝槽之電容器的下層電極（bottomelectrode)，能 大幅增加下層電極表面積，故能大幅增加電容器電容，縮小電路佈局面積，提高動 態隨機存取記憶體之集積密度。接著，以標準製程在所述電容器的下層電極表面形 成一層厚度很薄的電容器介電層，接著，形成一•層第一複晶砂。最後’利用微影技 術與電漿蝕刻技術蝕刻所述電容器介電層和第二複晶矽，以形成電容器的上層電極 (top electrode )，一種具備高集積密度之堆疊式動態隨機存取記憶體於焉完成。 3 (請先聞讀背面之注意事項再填寫本頁) 裝- -訂 本纸張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） 312834 Α7 Β7 經濟部中央橾举局只工消费合作社印裝 五、發明説明（） 4·圖示的簡要說明 圖一到圖十六是本發明之實施例的製程剖面示意圖。 圖一是在矽半導體晶圓上形成轉移閘電晶體和字語線後的製程剖面示意圖； 圖二是_沈積一層第一介電層與第二介電層，並平坦化所述第二介電層後的製程剖面 不意圖； 、圖三是利用微影技術與電漿蝕刻技術蝕刻所述第一介電層與第二介電層以以形成記 憶元接觸窗（node contact)後的製程剖面示意圖； 圖四是沈積一層第一·複晶矽後的製程剖面示意圖； 圖五是沈積一層第三介電層後的製程剖面示意圖； 圖六是形成點狀的複晶矽半球型晶粒（Hemi-SphericalGrain ; HSG)後的製程剖面 示意圖； 圖七是蝕刻所述第三介電層，同時也蝕刻掉一部份的所述複晶矽半球型晶粒後的製 程剖面示意圖； 圖八是在含濕氧或乾氧的高溫環境中熱氧化所述複晶矽半球型晶粒和第一複晶矽， 以形成複晶矽氧化層（poly-oxide)後的製程剖面示意圖； 圖九是去除所述複晶矽氧化層後的製程剖面示意圖； 圖十是去除所述第三介電層後的製程剖面示意圖； 圖十一是利用微影技術在所述記憶元接觸窗上方形成光阻圖案後的製程剖面示意 Γο.Ι · 圖， 圖十二是利用電漿蝕刻技術對所述第一複晶矽進行蝕刻，以定義電容器之下層電極 後的製程剖面示意圖； 圖十三是去除所述光阻圖案後的製程剖面示意圖； 圖十四是在所述電容器的下層電極表面形成一層電容器介電層後的製程剖面示意 圖， 圖十五是形成一層第二複晶矽後的製程剖面示意圖； 圖十六是利用微影技術與磁場增強式活性離子式電漿蝕刻技術蝕刻所述薄的電容器 介-層和第二複晶矽，以形成電容器的上層電極（topelectrode)後的製程剖 面示意圖。 5·發明之實施例 現在請參考圖一。首先’在電阻値約2.5 ohm-cm、晶格方向（100)之P型砂 半導體基板10上形成場氧化層12 ’所述場氧化層12通常是利用熱氧化技術氧化 所述P型矽半導體基板10而形成’其厚度介於3500埃到6500埃之間，作爲隔 離金氧半場效電晶體之用。^然’也可以利用傳統的淺凹溝隔離技術（Shallow Trench Isolation ; STI)來形成隔離金氧半場效電晶體所需之場氧化層12。然後，在 所述P型砂半導體基板10之表面形成金氧半場效電晶體，所述金氧半場效電晶體 包含有閘氧化層14 '閘極16A、覆盖:氧化層18 (capped oxide)、N_淡摻雜源極/ 汲極20A/20B、二氧化矽側壁子22和N+源極/汲極24A/24B，如圖一所示。另 外，在形成閘極16A之同時也形成字語線16B，如圖一所示。 4 本紙張尺度適用中國國家標準（CNS ) Α4現格（210Χ297公楚） I I -----I J I I —. I I ——訂 (請先W讀背面之注意事項再填寫本頁) 五、發明説明（） A7 B7 經濟部中央標準局員工消资合作社印裝 請再參考圖一。所述閘氧化層Μ是在含乾氧的高溫環境中熱氧化所述P型矽 半導體基板10之表面之矽原子而成’其氧化溫度介於850到1〇〇〇 °C之間，其厚 度介於50到200埃之間。所述閘極16A則一般是由低壓化學氣相沉積法 (LPCVD)形成之複晶矽16或鎢複晶矽化物所構成，若由複晶矽構成，其厚度介 於2000到4000埃之間，若由鎢複晶矽化物構成，則下層複晶矽之厚度介於1〇〇〇 到2000埃之間，上層矽化鎢之厚度介於1000到2000埃之間，其總厚度也是介 於2000到4000埃之間。所述覆蓋氧化層18是利用低壓化學氣相沉積法形成之無 摻雜的二氧化矽，其厚度介於800到1600埃之間。然後，利用微影技術與電獎蝕 刻技術蝕刻所述覆蓋氧化層18和複晶矽16f鎢複晶矽化物’以形成所述轉移閘電 晶體之閘極結構（gate structure )，如圖一所示_。 形成所述複晶矽16之反應溫度介於500到700 °C.之間，而形成之複晶矽16 可以未經摻雜，然後再利用離子佈植技術予以摻雜使具導電性’其離子佈植劑量介 於1E13到1E16原子/平方公分之間，離子佈植能量則介於30到80 Kev之間，以 完成對所述複晶矽16之摻雜。當然，也能利用同步磷離子攙雜方法Un-situ doped)以完成對所述複晶矽16之摻雜，其反應氣體是PH3、SiH4與N2的混合氣 體或AsH3、SiH4與N2的混合氣體，最後的磷離子濃度介於1E20到1E21原子/立 方公分之間，而較理想的磷離子濃度是5E20原子/立方公分之間。對所述複晶矽18 之電漿蝕刻，其反應氣體則是由SF6、Cl2和HBr組成之混合氣體，能提供效果相 當理想的單向性蝕刻、蝕刻率和蝕刻均勻度，所述複晶矽16對所述閘氧化層14之 蝕刻選擇率也非常高。 請再參考圖一。接著，利用磷離子佈植技術來形成所述轉移閘電晶體之N-淡 摻雜源極/汲極20A/20B，其離子佈植劑量介於1£13到3E14原子/平方公分之 間，離子佈植能量則介於20到50 Kev之間，如圖一所示，所述N·淡摻雜源極/汲 極20A/20B是爲了降低熱載子效應，以提高所述轉移閘電晶體之可靠性。接著，沉 積一層二氧化矽22，並利用磁場增強式活性離子式電漿蝕刻技術對所述二氧化矽 22進行垂直單向性的回蝕刻，以在所述鬧極16之二翻形成二氧化矽側壁子22。 而所述二氧化矽22通常是利用低壓化學氣相沉積法形成之無攙雜的二氧化矽，其反 應氣體是矽甲烷或四已基矽酸鹽（Si(C2H50)4)和氧氣，反應溫度介於600到800 °C之間，反應壓力介於0.2到0.4托爾之間，厚度介於500到1500埃之間。最 後，利用離子砷佈植技術形成N+源極24A/汲極24B，其離子佈植劑量介於1E15到 5E16原子/平方公分之間，離子佈植能量則介於30到80 Kev之間，以提供良好的歐 姆接觸，如圖一所示。 現在請參考圖二與圖三。完成所述轉移閘電晶體和字語線16B的製造後，接 著，沈積一層第一介電層26與第二介電層28，並利用化學機械式琢磨g術 (Chemical Mechanical Polishing ; CMP )平坦化所述第一介電層28，如圖—所不。 接著，利用微影技術與電漿蝕刻技術鈾刻所述N+源極24A上方之所述第一介電層 26與第二介電層28以露出所述N+源極24A，以在所述N+源極24A區域形成 5 I- -- I II - - 11 - I m t- I...........1-- -II !· I ,訂 (請先閲讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CMS ) A4说格（210X297公釐） A7 B7 經濟部中央標準局貝工消费合作社印裝 五、發明説明（) 記憶元接觸窗30 (node contact)’如圖三所示，未來，堆叠式電容器之下層電極將 透過所述記憶元接觸窗30跟所述轉移閘電晶體之N+源極24A作電性接觸。 所述第一介電層26可以是利用低壓化學氣相沉積法（LPCVD)形成之無攙雜 的二氧化矽，其反應溫度介於330到370 °C之間，其反應氣體是四已基矽酸鹽 (TE0S)與氧化氮（N20)或甲烷（silane)與氧化氮（N20)，其厚度介於800 埃到1600埃之間。所述第二介電層28則是利用大氣壓化學氣相沉積法 (APCVD)或次大氣壓化學氣相沉積法（ SACVD)形成之硼磷摻雜二氧化矽 (BPSG)或磷摻雜二氧化矽（PSG)，其反應氣體是TMB、TMP與氧化氮，其厚 度介於3000到8000埃之間。對所述第一介電層26與第二介電層28之電漿蝕刻 以形成所述記憶元接觸窗30，可以利用磁場增強式活性離子式電漿蝕刻技術 (MERIE)或電子迴旋共振電漿蝕刻技術（ECR)或傳統的活性離子式電獎触刻技 術（RIE) ’而通常是利用磁場增強式活性離子式電發蝕刻技術，其電漿反應氣體是 三氟氫化碳和氬氣，例如，曰本電氣公司（TEL)所製造型號TEL8500之蝕刻機或 美國應用材料公司（applied materials)所製造型號PR5000E之蝕刻機，其蝕刻原理 均屬於磁場增強式活性離子式電漿蝕刻技術，能提供效果相當理想的單向性蝕刻、 蝕刻率和蝕刻均勻度，且所述對P型矽半導體基板10之鈾刻選擇率也非常高。 現在請參考圖四與圖五。然後，沈積一層笔二砂32，如圖四所示。然 後，沈積一層第三企重層33，如圖五所示。所述第一擾瓦吞32通常是利用同步攙 雜之低壓化學氣相沉積运运成，其反應氣體是PH3、SiH4與N2或AsH3、SiH4與 N2的混合氣體，反應溫度介於500到650 °C之間，其厚度介於2000到6000埃之 間’其雜質離子濃度介於1E20到1E21原子/立方公分之間，而較理想的濃度是 5E2〇原子/立方公分。所述第三介電層33是利用低壓化學氣相沉積法形成之笔作 泛’其反應氣體是NH3和SiH4或NH3和SiCl2H2的混合氣體，反應溫度介於60—0 ϋ 800 °C之間，反應壓力介於0.2到0.4托爾之間，厚度介於1000到2000埃之 間，其功用是作爲後續抗氧化罩。 現在請參考圖六與圖七。然後，利用低壓化學氣相沉積法形成點狀的複晶矽半 球裂晶粒_34 ( Hemi-Spherical Grain ; HSG )，形成所述複晶砍半球型晶粒34之反 應溫 1乔菸500到75〇 °C之間，其直徑介於50到500埃之間，如圖六所示。然 後，利用磁場增強式活性離子式電漿触刻技術蝕刻所述第三介電層33 ,同時也触刻 掉一部份的所述複晶矽半球型晶粒34，使所述第三介電層33成爲第三介電層 33a ’使所述複晶矽半球型晶粒34成爲複晶矽半球型晶粒34a，如圖七所示。對所 述第三介電層33之磁場增強式活性離子式電駿触刻，其電漿反應氣體是四氟化碳 等氣體，對所述第三介電層33之軸刻率比所述複晶矽半球型晶粒34高，並且’能 提供效果相當理想的蝕刻率和蝕刻均勻度。 現在請參考圖八、圖九與圖十。然後，在含濕氧或乾氧的高溫環境中熱氧化所 述複晶矽半球型晶粒34a和第一複晶矽32，使所述複晶矽半球型晶粒3½成爲複 晶矽氧化層36 (P〇ly-oxide)，使一部份的所述第一複晶矽32成爲複晶矽氧化層 6 (請先閲讀背面之注意事項再填寫本頁) 裝. 訂 本紙張尺度適用中國國家標準（CNS ) M说格（2丨〇><297公釐） A7 B7 經濟部中央樣準局員工消费合作社印裝 五、發明説明（） 38 (poly-oxide)，所述熱氧化溫度介於700到900 t之間，如圖八所示。接著， 利用電漿蝕刻或稀釋氫氟酸溶液或蒸氣氫氟酸（vaporHF)去除所述複晶矽氧化層 36和複晶矽氧化層38 ’在所述第一複晶矽32表面形成溝槽，如圖九所示。再利用 電漿蝕刻技術或磷酸濕蝕刻技術去除所述第三介電層33a後，如圖十所示。 現在請參考圖十一、圖十二與圖十三。接著，利用微影技術在所述記憶元接觸 窗30上方形成光阻圖案44，如圖十一所示，所述光阻圖案44是正光阻，其厚度 介於8000到12000埃之間。然後，利用磁場增強式活性離子式電漿触刻技術對所述 第一複晶矽32a J1行飩刻，使成爲第一複晶矽32b，以定義電容器之下層電極的圖 案，如圖十二所示。利用氧氣電漿和硫酸去除所述光阻圖案44後，所述第一複晶矽 32b構成了電容器的下層電極，如圖十三所示。對所述第一複晶矽32ά之磁場增強 式活性離子式電漿蝕刻，其電漿反應氣體是六氟化硫和溴化氫之混合氣體，能提供 效果相當理想的蝕刻率和蝕刻均勻度，並且，在六氟化硫和溴化氫之氣體電漿內， 所述第一複晶矽32a對光阻圖案44之触刻選擇率非常高，介於1〇到20之間。請 注意，由所述第一複晶矽32b構成之電容器的下層電極32b，具有溝槽，能大幅增 加下層電極3¾表面積，大幅增加電容器電容，縮小電路佈局面積，提高動態隨機 存取記億體之集積密度。 現在請參考圖十四、圖十五與圖十六。接著，利用傳統標準製程在所述電容器 的下層電極32b表面形成一層厚度相當薄的電容器介電層邮，如圖十四所示。接 著，再形成一層第二複晶矽48，如圖十五所示。最後，利ϋ影技術與磁場增強式 活性離子式電紫触刻技術触刻所述薄的電容器介電層46和第二複晶矽48，以形成 電容器的上層電極（top electrode)，如圖十六所示，一種高集積密度之堆疊式動態 隨機存取記憶體於焉完成。 所述電容器介電層46通常是由氧化氮化砂.（Oxynitride)、氮化砍（Nitride) 和二氧化矽（Oxide)藉由下述方法形成。首先，在溫度介於800°C到950°C之間時 熱氧化由複晶矽構成之所述下層電極32b，以形成厚度介於40埃到200埃之間的 氧化矽。接著’在溫度介於650°C到750°C .之間時以低壓化學氣相沉積法形成厚度 介於40埃到60埃之間的氮化矽。最後，在溫度介於800°C到950°C之間時氧化所 述氮化矽，以形成厚度介於20埃到50埃之間的氧化氮化砂。自然，所述電容器介 電層46亦可由其它高介電常數材料組成，例如五氧二鉅（Ta2〇5 )，或由Ti02 和SrTi03等高介電常數材料所組成。 所述第二複晶矽48之形成方法跟第一複晶矽32 —樣，是利用同步攙雜之低 壓化學氣相沉積法形成，其反應氣體是PH3、SiH4與N2或AsH3、SiH4與N2的 混合氣體，反應溫度介於500到650 °C之間，其厚度介於1000到2000埃之間，其 雜質離子濃度介於1E20到1E21原子/立方公分之間，而較理想的濃度是5E20原子/ 立方公分。而形成電容器的上層電極48之電漿蝕刻，可以利用磁場增強式活性離子 式電漿蝕刻技術（MERIE)，其電漿反應氣體是六氟化硫和溴化氫之混合氣體。 7 ^^^1- —^n ^—.1· tn ml d·^— I I ^ nn In (請先聞讀背面之注意事項再填寫本頁} 本紙張尺皮適用中國國家標芈（CNS > A4現格（2丨OX297公釐） 312834 A7 A7 B7 五、發明説明（） 以上係以最佳實施例來闡述本發明，而非限制本發明，並且，熟知半導體技藝 之人士皆能明瞭，適當而作些微的改變及調整，仍將不失本發明之要義所在，亦不 脫離本發明之精神和範圍。 (請先閲讀背面之注意事項再填寫本頁) 裝. 訂 經濟部中央標车局員工消费合作社印裝 本紙張尺反適用中國國家標準（CNS > A4現格（210X297公釐）"Stacked capacitor cells for high density dynamic RAMs" published by Watanabe et al. On page 600 in IEDM 1988 and "novel stacked capacitor cells for 64 Mb DRAM" published by Wakamiya et al. On page 69 of VLSI Technology 1989 Stacked capacitor structure. U.S. Patent No. 4742018 of S. Kimura et al. And U.S. Patent No. 4977102 of T.Ema also disclose that the stacking type 2 paper size is applicable to the Chinese National Standard Vehicle (CNS) A4 grid (210X297 mm) tut ^ m- an — Ml m «ml mu ff ^ i— tortoise (please read the precautions before filling in the cornel) A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Samples of the Ministry of Economic Affairs V. Invention Instructions () Container to increase the capacitor capacitance. Masao Taguchi et al. Of Fujitsu Corporation of Japan further disclosed an improved stacked capacitor structure, called a fin-type capacitor structure (fln capacitor), which greatly increases the capacitor capacitance and improves the dynamic random access memory. The accumulation density. T. Kaga et al. Of Hitachi, Inc., published a paper titled "A 0.29 um2 ΜΙΜ-CROWN cell and process technology for 1-Gigabit DRAMs" on page 927 of 1994 IEDM, which revealed a more advanced The stacked capacitors called "MIM-CROWN structure" can greatly increase the capacitance value of the capacitor and increase the accumulation density of dynamic random access memory devices. 3. Brief description of the invention The main object of the present invention is to provide a method for manufacturing a stacked capacitor capable of increasing capacitance. Another object of the present invention is to provide a method for manufacturing a stacked dynamic random access memory with high packing density. The main method of the present invention is briefly described as follows. First, a standard process is used to form a field oxide layer on the silicon semiconductor wafer that is required to isolate the metal oxide semiconductor field effect transistor. Then, the metal oxide semiconductor field word transistor and the wordline are formed. Next, next, a first dielectric layer and a second dielectric layer are deposited, and the second dielectric layer is planarized using chemical mechanical polishing technology. Next, the first dielectric layer and the second dielectric layer are etched using photolithography technology and plasma etching technology to expose the source electrode of the metal oxide half field effect transistor to form a node contact . Next, a layer of first polycrystalline silicon is deposited, and then a layer of third dielectric layer is deposited. The third dielectric layer is silicon nitride formed by low-pressure chemical vapor deposition, and its function is as a subsequent anti-oxidation mask. Next, dot-shaped polycrystalline silicon hemispherical grains (dotHemi-Spherical Grain; dotHSG) are formed. Then, engraving the third dielectric layer, and also etching away a part of the polycrystalline silicon hemispherical crystal grains, and then, oxidizing the polycrystalline silicon hemispherical crystal grains and the first polycrystalline silicon, The polycrystalline silicon hemispherical crystal grain is made into a polycrystalline oxide layer (poly-oxide), and a part of the first polycrystalline sand is made into a polycrystalline sand oxide layer. Next, the polycrystalline silicon oxide layer is removed to form a trench on the surface of the first polycrystalline silicon, and then the third dielectric layer is removed. ..: Next, a photoresist pattern is formed using a lithography technique, and then the first polycrystalline silicon is etched using a plasma etching technique to define the pattern of the underlying electrode of the capacitor. After the photoresist pattern is removed, the lower electrode of the grooved capacitor is formed. The bottom electrode of the grooved capacitor can greatly increase the surface area of the bottom electrode, so it can greatly increase the capacitor capacitance, reduce the circuit layout area, and increase the accumulation density of dynamic random access memory. Next, a thin-layer capacitor dielectric layer is formed on the surface of the lower electrode of the capacitor by a standard process, and then a layer of first polycrystalline sand is formed. Finally, the photolithography technology and plasma etching technology are used to etch the capacitor dielectric layer and the second polycrystalline silicon to form a top electrode of the capacitor, a stacked dynamic random access memory with high accumulation density Yu Yan completed. 3 (Please read the precautions on the back before filling out this page) Binding--The size of the paper is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) 312834 Α7 Β7 The Central Bureau of Economic Affairs of the Ministry of Economic Affairs only consumes Cooperative cooperative printing 5. Description of the invention () 4. Brief description of the drawings Figures 1 to 16 are schematic cross-sectional views of the manufacturing process of the embodiment of the present invention. Figure 1 is a schematic cross-sectional view of the process after forming a transfer gate transistor and word lines on a silicon semiconductor wafer; Figure 2 is a method of depositing a first dielectric layer and a second dielectric layer, and planarizing the second dielectric The process profile after the electrical layer is not intended; FIG. 3 is the process after etching the first dielectric layer and the second dielectric layer using photolithography technology and plasma etching technology to form a memory cell contact (node contact) Schematic cross-section; Figure 4 is a schematic cross-sectional view of the process after depositing a layer of first polysilicon; Figure 5 is a schematic cross-sectional view of the process after depositing a third dielectric layer; Figure 6 is a dotted polycrystalline silicon hemispherical grain (Hemi-SphericalGrain; HSG) Process cross-sectional schematic diagram; FIG. 7 is a process cross-sectional schematic diagram after the third dielectric layer is etched and part of the polycrystalline silicon hemispherical grains are also etched; FIG. 8 It is a schematic cross-sectional view of the process after thermally oxidizing the polycrystalline silicon hemispherical crystal grains and the first polycrystalline silicon in a high temperature environment containing wet or dry oxygen to form a polycrystalline silicon oxide layer (poly-oxide); FIG. 9 After removing the polycrystalline silicon oxide layer Schematic cross-sectional view; Figure 10 is a schematic cross-sectional view of the process after removing the third dielectric layer; Figure 11 is a schematic cross-sectional view of the process after forming a photoresist pattern on the memory cell contact window using lithography technology. FIG. 12 is a schematic cross-sectional view of the process after the first polycrystalline silicon is etched using plasma etching technology to define the underlying electrode of the capacitor; FIG. 13 is a schematic cross-sectional view of the process after removing the photoresist pattern; Fig. 14 is a schematic cross-sectional view of the process after forming a capacitor dielectric layer on the lower electrode surface of the capacitor, Fig. 15 is a schematic cross-sectional view of the process after forming a second polycrystalline silicon layer; The cross-sectional schematic diagram of the process after the magnetic field enhanced active ion plasma etching technique etches the thin capacitor dielectric layer and the second polycrystalline silicon to form the top electrode of the capacitor. 5. Embodiment of the invention Now please refer to FIG. First, a field oxide layer 12 is formed on a P-type sand semiconductor substrate 10 with a resistance value of about 2.5 ohm-cm and a lattice direction (100). The field oxide layer 12 is usually a thermal oxidation technique to oxidize the P-type silicon semiconductor substrate 10 to form 'its thickness is between 3500 Angstroms to 6500 Angstroms, used as isolation metal oxide half field effect transistors. ^ Ran 'can also use traditional shallow trench isolation technology (Shallow Trench Isolation; STI) to form the field oxide layer 12 required for isolating the metal oxide half field effect transistor. Then, a metal oxide half field effect transistor is formed on the surface of the P-type sand semiconductor substrate 10, and the metal oxide half field effect transistor includes a gate oxide layer 14 'gate electrode 16A, covered with: an oxide layer 18 (capped oxide), N _Lightly doped source / drain 20A / 20B, silicon dioxide sidewall spacer 22 and N + source / drain 24A / 24B, as shown in FIG. 1. In addition, the word line 16B is formed at the same time as the gate electrode 16A is formed, as shown in FIG. 4 This paper scale is applicable to the Chinese National Standard (CNS) Α4 present style (210Χ297 Gongchu) II ----- IJII —. II ——Order (please read the precautions on the back before filling this page) V. Description of invention () A7 B7 Printed and printed by the Cooperative Society for Employee Expenditure of the Central Bureau of Standards of the Ministry of Economic Affairs, please refer to Figure 1 again. The gate oxide layer M is formed by thermally oxidizing silicon atoms on the surface of the P-type silicon semiconductor substrate 10 in a high-temperature environment containing dry oxygen. The oxidation temperature is between 850 and 1000 ° C. The thickness is between 50 and 200 Angstroms. The gate electrode 16A is generally composed of polycrystalline silicon 16 or tungsten polycrystalline silicide formed by low pressure chemical vapor deposition (LPCVD). If it is composed of polycrystalline silicon, its thickness is between 2000 and 4000 angstroms If made of tungsten polycrystalline silicide, the thickness of the lower polycrystalline silicon is between 1000 and 2000 angstroms, the thickness of the upper tungsten silicide is between 1000 and 2000 angstroms, and the total thickness is also between 2000 To 4000 Angstroms. The cover oxide layer 18 is undoped silicon dioxide formed by low-pressure chemical vapor deposition, and has a thickness between 800 and 1600 angstroms. Then, the photolithography technology and the electric award etching technology are used to etch the cover oxide layer 18 and the polycrystalline silicon 16f tungsten polycrystalline silicide 'to form a gate structure of the transfer gate transistor, as shown in FIG. 1示 _. The reaction temperature for forming the polycrystalline silicon 16 is between 500 and 700 ° C. The formed polycrystalline silicon 16 may be undoped and then doped using ion implantation technology to make it conductive. The ion implantation dose is between 1E13 and 1E16 atoms / cm 2, and the ion implantation energy is between 30 and 80 Kev to complete the doping of the polycrystalline silicon 16. Of course, the synchronous phosphorus ion doping method (Un-situ doped) can also be used to complete the doping of the polycrystalline silicon 16, the reaction gas is a mixed gas of PH3, SiH4 and N2 or a mixed gas of AsH3, SiH4 and N2, The final phosphorus ion concentration is between 1E20 and 1E21 atoms / cubic centimeter, while the ideal phosphorus ion concentration is between 5E20 atoms / cubic centimeter. For the plasma etching of the polycrystalline silicon 18, the reaction gas is a mixed gas composed of SF6, Cl2 and HBr, which can provide a unidirectional etching, etching rate and etching uniformity that are quite ideal. The etching selectivity of silicon 16 to the gate oxide layer 14 is also very high. Please refer to Figure 1 again. Next, the N-lightly doped source / drain 20A / 20B of the transfer gate transistor is formed using phosphor ion implantation technology, and the ion implantation dose is between 1 £ 13 to 3E14 atoms / cm2, The energy of ion implantation is between 20 and 50 Kev. As shown in Fig. 1, the N · lightly doped source / drain 20A / 20B is to reduce the hot carrier effect and increase the transfer gate current. Crystal reliability. Next, a layer of silicon dioxide 22 is deposited, and the magnetic field enhanced active ion plasma etching technique is used to perform a vertical unidirectional etch back on the silicon dioxide 22 to form the dioxide in the second of the anode 16 Silicon side wall 22. The silicon dioxide 22 is usually an impurity-free silicon dioxide formed by low-pressure chemical vapor deposition. The reaction gas is silicon methane or tetrahexyl silicate (Si (C2H50) 4) and oxygen. The reaction temperature Between 600 and 800 ° C, the reaction pressure is between 0.2 and 0.4 Torr, and the thickness is between 500 and 1500 Angstroms. Finally, the ion implantation technology is used to form the N + source 24A / drain 24B. The ion implantation dose is between 1E15 and 5E16 atoms / cm2, and the ion implantation energy is between 30 and 80 Kev. Provide good ohmic contact, as shown in Figure 1. Now please refer to Figure 2 and Figure 3. After the manufacture of the transfer gate transistor and the word line 16B is completed, a first dielectric layer 26 and a second dielectric layer 28 are deposited, and then flattened by chemical mechanical polishing (CMP) The first dielectric layer 28 is changed as shown in the figure. Next, the first dielectric layer 26 and the second dielectric layer 28 above the N + source electrode 24A are uranium-etched using photolithography and plasma etching techniques to expose the N + source electrode 24A, so that the N + Source 24A area formation 5 I--I II--11-I m t- I .......... 1-- -II! I, order (please read the notes on the back first (Fill in this page again) This paper scale is applicable to the Chinese National Standard (CMS) A4 said grid (210X297 mm) A7 B7 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of invention () Memory cell contact window 30 (node As shown in FIG. 3, in the future, the lower electrode of the stacked capacitor will make electrical contact with the N + source electrode 24A of the transfer gate transistor through the memory cell contact window 30. The first dielectric layer 26 may be a doped silicon dioxide formed by low pressure chemical vapor deposition (LPCVD), the reaction temperature of which is between 330 and 370 ° C, and the reaction gas is tetrahexyl silicon The thickness of the acid salt (TEOS) and nitrogen oxide (N20) or methane (silane) and nitrogen oxide (N20) is between 800 angstroms and 1600 angstroms. The second dielectric layer 28 is boron-phosphorus doped silicon dioxide (BPSG) or phosphorus-doped silicon dioxide formed by using atmospheric pressure chemical vapor deposition (APCVD) or sub-atmospheric pressure chemical vapor deposition (SACVD) (PSG), the reaction gas is TMB, TMP and nitrogen oxide, and its thickness is between 3000 and 8000 angstroms. Plasma etching of the first dielectric layer 26 and the second dielectric layer 28 to form the memory cell contact window 30 can use magnetic field enhanced active ion plasma etching technology (MERIE) or electron cyclotron resonance electric Etching technology (ECR) or traditional reactive ion electro-engraving technology (RIE) 'and usually use magnetic field enhanced active ion electro-etching technology, the plasma reaction gas is trifluorocarbon and argon, For example, the etching machine model TEL8500 manufactured by Japan Electric Company (TEL) or the etching machine model PR5000E manufactured by American Applied Materials, the etching principle belongs to the magnetic field enhanced active ion plasma etching technology. It provides unidirectional etching, etching rate and etching uniformity with a quite ideal effect, and the uranium etching selectivity of the P-type silicon semiconductor substrate 10 is also very high. Now please refer to Figure 4 and Figure 5. Then, a layer of pen second sand 32 is deposited, as shown in FIG. 4. Then, a third layer 33 is deposited, as shown in Figure 5. The first disturbing wharton 32 is usually transported by low-pressure chemical vapor deposition with simultaneous doping. The reaction gas is PH3, SiH4 and N2 or AsH3, SiH4 and N2 mixed gas, and the reaction temperature is between 500 and 650 Between C, its thickness is between 2000 and 6000 Angstroms, and its impurity ion concentration is between 1E20 and 1E21 atoms / cubic centimeter, while the ideal concentration is 5E2〇 atoms / cubic centimeter. The third dielectric layer 33 is formed by a low-pressure chemical vapor deposition method. The reaction gas is a mixed gas of NH3 and SiH4 or NH3 and SiCl2H2, and the reaction temperature is between 60-0 and 800 ° C. The reaction pressure is between 0.2 and 0.4 Torr, and the thickness is between 1000 and 2000 Angstroms. Its function is as a subsequent anti-oxidation cover. Now please refer to Figure 6 and Figure 7. Then, the low-pressure chemical vapor deposition method is used to form point-like polycrystalline silicon hemispherical cracked grains_34 (Hemi-Spherical Grain; HSG), and the reaction temperature for forming the polycrystalline cut hemispherical grains 34 is 1 to 500 to 500. Between 75 ° C, its diameter is between 50 to 500 Angstroms, as shown in Figure 6. Then, the third dielectric layer 33 is etched by using a magnetic field enhanced active ion plasma contact etching technology, and at the same time, a part of the polycrystalline silicon hemispherical crystal grains 34 are also touched away to make the third dielectric The electric layer 33 becomes the third dielectric layer 33a ', so that the polycrystalline silicon hemispherical crystal grain 34 becomes the polycrystalline silicon hemispherical crystal grain 34a, as shown in FIG. 7. For the magnetic field-enhanced active ion type electroetching of the third dielectric layer 33, the plasma reaction gas is gas such as carbon tetrafluoride, and the axial engraving rate of the third dielectric layer 33 is higher than that The polycrystalline silicon hemispherical crystal grains 34 are high, and can provide an ideal etching rate and etching uniformity. Now please refer to Figure 8, Figure 9 and Figure 10. Then, the polycrystalline silicon hemispherical crystal grains 34a and the first polycrystalline silicon 32 are thermally oxidized in a high temperature environment containing wet or dry oxygen, so that the polycrystalline silicon hemispherical crystal grains 3½ become a polycrystalline silicon oxide layer 36 (P〇ly-oxide), making part of the first polycrystalline silicon 32 into a polycrystalline silicon oxide layer 6 (please read the precautions on the back before filling in this page). Packing. The size of this paper is applicable to China National Standard (CNS) M Saoge (2 丨 〇 < 297mm) A7 B7 Printed by the Central Consumers ’Bureau of the Ministry of Economic Affairs Employee Consumer Cooperative V. Invention Instructions () 38 (poly-oxide), the thermal oxidation The temperature is between 700 and 900 t, as shown in Figure 8. Next, the polycrystalline silicon oxide layer 36 and the polycrystalline silicon oxide layer 38 'are removed by plasma etching or dilute hydrofluoric acid solution or vapor hydrofluoric acid (vaporHF) to form grooves on the surface of the first polycrystalline silicon 32 , As shown in Figure 9. After removing the third dielectric layer 33a by plasma etching technology or phosphoric acid wet etching technology, as shown in FIG. Now please refer to Figure 11, Figure 12 and Figure 13. Next, a photolithography technique is used to form a photoresist pattern 44 above the memory cell contact window 30. As shown in FIG. 11, the photoresist pattern 44 is a positive photoresist with a thickness between 8000 and 12000 angstroms. Then, the first polycrystalline silicon 32a J1 is engraved by using magnetic field enhanced active ion plasma contact etching technology to become the first polycrystalline silicon 32b to define the pattern of the underlying electrode of the capacitor, as shown in FIG. 12 As shown. After removing the photoresist pattern 44 with oxygen plasma and sulfuric acid, the first polycrystalline silicon 32b constitutes the lower electrode of the capacitor, as shown in FIG. 13. For the magnetic field enhanced active ion plasma etching of the first polycrystalline silicon 32, the plasma reaction gas is a mixed gas of sulfur hexafluoride and hydrogen bromide, which can provide an ideal etching rate and etching uniformity And, in the gas plasma of sulfur hexafluoride and hydrogen bromide, the contact selectivity of the first polycrystalline silicon 32a to the photoresist pattern 44 is very high, ranging from 10 to 20. Please note that the lower electrode 32b of the capacitor composed of the first polycrystalline silicon 32b has a groove, which can greatly increase the surface area of the lower electrode 32, greatly increase the capacitor capacitance, reduce the circuit layout area, and increase the dynamic random access memory The accumulation density. Now please refer to Figure 14, Figure 15 and Figure 16. Next, a conventional standard process is used to form a relatively thin capacitor dielectric layer on the surface of the lower electrode 32b of the capacitor, as shown in FIG. 14. Then, a second layer of polycrystalline silicon 48 is formed, as shown in FIG. 15. Finally, the thin film dielectric layer 46 and the second polycrystalline silicon 48 are etched by Liying technology and magnetic field-enhanced active ion electroviolet lithography technology to form the top electrode of the capacitor, as shown in the figure As shown in Figure 16, a high-density stacked dynamic random access memory is completed in Yan. The capacitor dielectric layer 46 is generally made of Oxynitride, Oxynitride, Nitrid, and Oxide by the following method. First, the lower electrode 32b composed of polycrystalline silicon is thermally oxidized at a temperature between 800 ° C and 950 ° C to form silicon oxide with a thickness between 40 angstroms and 200 angstroms. Next, silicon nitride with a thickness between 40 Angstroms and 60 Angstroms is formed by low-pressure chemical vapor deposition at a temperature between 650 ° C and 750 ° C. Finally, the silicon nitride is oxidized at a temperature between 800 ° C and 950 ° C to form oxynitride sand with a thickness between 20 Angstroms and 50 Angstroms. Naturally, the capacitor dielectric layer 46 may also be composed of other high dielectric constant materials, such as pentoxide (Ta205), or high dielectric constant materials such as Ti02 and SrTi03. The forming method of the second polycrystalline silicon 48 is the same as that of the first polycrystalline silicon 32, and is formed by synchronously doped low-pressure chemical vapor deposition method, and the reaction gas is PH3, SiH4 and N2 or AsH3, SiH4 and N2 Mixed gas, the reaction temperature is between 500 and 650 ° C, the thickness is between 1000 and 2000 Angstroms, the impurity ion concentration is between 1E20 and 1E21 atoms / cm3, and the ideal concentration is 5E20 atoms / Cubic centimeters. For plasma etching of the upper electrode 48 forming the capacitor, magnetic field enhanced active ion plasma etching technology (MERIE) can be used. The plasma reaction gas is a mixed gas of sulfur hexafluoride and hydrogen bromide. 7 ^^^ 1- — ^ n ^ —. 1 · tn ml d · ^ — II ^ nn In (please read the precautions on the back and then fill out this page) This paper ruler is suitable for China National Standards (CNS >); A4 present case (2 丨 OX297mm) 312834 A7 A7 B7 V. Description of the invention () The above is the best embodiment to illustrate the present invention, not to limit the invention, and the person skilled in semiconductor technology can understand it Appropriate and slight changes and adjustments will still not lose the essence of the present invention, and will not deviate from the spirit and scope of the present invention. (Please read the precautions on the back before filling this page) The paper ruler printed by the Bureau ’s Staff Consumer Cooperative applies the Chinese National Standard (CNS > A4 now (210X297mm)