Α7 4 44325 Β7 五、發明說明（/) 發明領域： (請先Μ讀背面之注意事項再填寫本頁) 本發明係關於一種於矽基板上形成渠溝的方法，特別 是關於防止產生圓錐形矽化物(Si cone defeat)於淺渠溝區域 中。 發明背景： 近年來，隨著積體霉路集積密度的快速增加，爲了降 低各電晶體之間的間隔，並確保各電晶體的運作不會受到 其他電晶體的影響，而有閉鎖(Latch Up)現象的發生，因此， 有淺渠溝隔離（Shallow Trench Isolation)產生；但在進行淺 渠溝隔離製程中會遇到許多困難處，如淺渠溝隔離與接近 主動元件區(active region)之邊角通常會趨近直角，因此，邊 角處之表面能之區率半徑很小，其表面能很高，因此，不 易形成氧化矽薄膜於其上，使得電晶體在正常運作下容易 有提早導通(early tum-on)的轉折效應(kink effect)產生。 經濟部智慧財產局員工消費合作社印製 爲解決上述之轉折效應，習知技術中係在餓刻形成淺 渠溝過程中，其反應氣體會產生少許高分子聚合物於所述 之淺渠溝之邊角120上，作爲製程中之微小之蝕刻罩幕 (micro-mask)，使得蝕刻出之淺渠溝之邊角120不會趨近直 角’如圖一所示，先在基板上形成墊氧化層25及氮化矽層 3〇 ’並定義出淺渠溝位置後除去淺渠溝位置上之墊氧化層 及氮化矽層，最後，蝕刻以形成淺渠溝，但在此蝕刻淺渠 溝的製程中蝕刻出淺渠溝20時，製程所使用之触刻氣體爲 氦氣(He)-氧氣(〇2)、四氟化碳(Cf4)、三氟化烷(CHF3)及溴 __ 2 本紙張尺度適用+國國家標準（CNS)A4規格（21〇 κ 297公爱） A7 A7 經濟部智慧財產局員工消費合作社印製 444325 五、發明說明（；） .化物，如此，蝕刻過程中會產生高分子聚合物於淺渠溝之 邊角120，使邊角120不會形成直角之狀況，因此’於淺渠 溝之邊角120之高分子聚合物在蝕刻過程中扮演微小之蝕 刻罩幕的角色。.但在此触刻過程中所產生之高分子聚合物 係有兩種，分別爲溴之矽化物1〇〇及溴之矽氧化物1〇1，上 述之兩種之差別在於溴之矽化物100易揮發’而溴之矽氧 化物101不易揮發，但在蝕刻過程中，上述之高分子聚合 物(溴之砂化物l〇〇[SiBrJ及溴之矽氧化物101[siBrx_i〇])除 了會在淺渠溝之邊角120處產生外，還會在淺渠溝20中存 在，因此，在蝕刻過程中存在於淺渠溝20之高分子聚合物 (溴之矽化物100及溴之矽氧化物101)，亦會於蝕刻過程中 形成微小之蝕刻罩幕，使得淺渠溝20中形成圓錐形矽化物 110，如此所形成之淺渠溝將會造成隔離效果不佳及因隔離 效果不佳而造成之漏電流的情況產生，若在蝕刻過程中僅 形成溴之矽化物100，便不會有圓錐形砂化物no產生。 因此，本發明揭露一種於矽基板上形成渠溝的方法， 以防止習知技術所述之問題產生。 發明之槪述： 本發明之主要目的是提供一種於矽基板上形成渠溝的 方法，在形成淺渠溝過程中，避免產生圓錐形矽化物於淺 渠溝中，可防止漏電流的狀況產生。 本發明的另一目的是提供一種於矽基板上形成渠溝的 方法，降低不易揮發的含溴之矽氧化物的高分子在蝕刻過 3 本紙張尺度適用中國國家棵準（CNS>A4规格（210 x 297公釐〉 --------------裝· ！ {猜先閱讀背面之注意事項再填寫本頁) . ，線 444325 A7 444325 A7 經濟部智慧財產局費工消費合作杜印製 五、發明說明（3 ) 程中形成。 本發明是利用下列技術手段來達到上述之各項目的： 首先，於一半導體基板上形成墊氧化層及氮化矽層，再於 所述氮化矽層上，定義出淺渠溝區域，並依序蝕刻未被光 阻覆蓋之所述氮化矽層及所述墊氧化層，接續，使用反應 性離子蝕刻方式蝕刻淺渠溝區域之基板以形成淺渠溝區 域，在蝕刻基板過程中，需注意反應氣體供給之條件，係 調整氦氣-氧氣、四氟化碳、氣體的流量或壓力及射頻功率 等，使蝕刻過程中不易揮發的含溴之矽氧化物，不會於淺渠 溝區域中產生。 圖式簡要說明： 圖一是習知技藝中，蝕刻以形成淺渠溝隔離之剖面示 意圖。 圖二是本發明實施例中，蝕刻以形成淺渠溝隔離之剖面 示意圖。 圖號說明： 10- 基板 20- 淺渠溝 25- 墊氧化層 30- 氮化矽層 100-溴之矽化物 101- 溴之矽氧化物 110- 圓錐形矽化物 120- 淺渠溝之邊角 發明詳細說明： 本發明可運用在製作半導體製程之淺渠溝製程中，藉著 4 本紙張尺度適用中S0家標準（CNSXA4⑽（210 X297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝 -線 4443 2 5 a? _ B7___ 五、發明說明（I ) 氦氣(He)-氧氣(02)、四氟化碳(CF4)氣體的流量(gas flow烕 壓力及射頻功率等之控制，降低蝕刻製程中含溴之矽氧化物 的高分子形成，本發明係運用製作矽半導體基板之淺渠溝製 程之具體實施例說明本發明的原則與精神。 首先，請參閱圖二，在基板1〇上形成一墊氧化層(Pad oxide)，接續於所述之墊氧化層上形成一氮化矽層，該墊氧 化層的厚度介於1〇〇埃到500埃之間，該氮化砂的厚度介 於500埃到2000埃之間，所述之墊氧化層係作爲主動元件 區的閘氧化層之用，而氮化矽層係作爲後續以電發触刻出 淺渠溝時所述之墊氧化層之蝕刻罩幕(mask)。 接續，旋塗(spin coating)光阻(resist)於所述之氮化较 層，使用光罩進行曝光顯影後，以定義出淺渠溝20之位置， 接著，進入本發明之重點，依序使用等向性飽刻(Isotmpic etching)未被光阻覆蓋之所述之氮化砂層、所述墊氧化層， 使基板1〇上原所定義之淺渠溝20位置之基板裸露出來， 所留下之氮化矽層30可保護位於氮化矽層30底下之墊氧 化層25。 接著，使用反應性離子蝕刻方式(Reactive ion etching ; RIE)以形成淺渠溝20，因習知技術中不易揮發之溴之矽氧 化物1〇1殘留，而成爲微小之蝕刻罩幕，而有圓錐形矽化 物110於淺渠溝20中產生，如圖一所示。爲了使蝕刻過程 中降低不易揮發之溴之矽氧化物101產生，因此在蝕刻過 程中本發明將控制反應氣體的流量或改變射頻功率以防止 溴之矽氧化物101生成。 5 本紙張尺度適用中國國家標準（CNS)A4规格（210 X 297公釐） ---------裝--- (請先閱讀背面之注意事項再填寫本頁) 訂· 線. 經濟部智慧財產局員工消費合作杜印製 五 I 經濟部智慧財產局員工消費合作社印製 4443 25 發明說明（(） 本實施例中可以下列三種方式達到本發明之目的： 1. 降低反應氣體之氦氣(He)-氧氣(〇2)流速’使上述之流 速介於0〜20sccm之間，如此在形成淺渠溝過程中， 因過程中氧原子的供給減少，所以’可抑制不易揮發 之溴之矽氧化物產生。 2. 增加反應氣體之四氟化碳(CF4)流速，所述之流速介於 5~3〇SCcm之間，因蝕刻過程中增加上述之四氟化碳流 速時可加強蝕刻強度，如此在形成淺渠溝過程中，可 移除形成之高分子聚合物，防止所述之高分子聚合物 於淺渠溝中生成。 3. 增加射頻功率係介於800至1000 W之間，並降低反 應壓力係介於30至60 mton之間，因在高射頻功率 與低壓下，其離子之平均自由徑(mean free path)較 長，使離子較易到達晶圓表面而與砂原子反應，而可 增加易揮發性高分子(溴之矽化物)的生成。 4. 可將上述之三種方式一起使用，如此，所得到之效果 爲最佳或採用上述之任兩種方法一倂使用也可得到 預期之效果，以期解決習知技術中所造成之問題。 綜上所述，本發明所提供之淺渠溝隔離方法較習知技術 具有之優點係爲：不需增加任何製程步驟及耗費製程多餘 之成本即可改善習知技術中所存在之問題。 以上所述係利用較佳實施例詳細說明本發明，而非限制 本發明的範圍，因此熟知此技藝的人士應能明瞭，適當而 作些微的改變與調整，仍將不失本發明之要義所在，亦不 6 背 事 訂 本紙張尺度適用中因國家標準（CNS)A4規格（210 X 297公« ) 經濟部智慧財產局員工消費合作社印製 4443 2 5_^_ 五、發明說明（l) 脫離本發明之精神和範圍，故都應^|爲本發明的進一步實 施狀況。謹請貴審查委員明鑑，並祈惠准，是所至禱。 (請先閱讀背面之注意事項再填寫本頁) 裝 · 線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉Α7 4 44325 Β7 V. Description of the invention (/) Field of invention: (Please read the precautions on the back before filling this page) The present invention relates to a method for forming trenches on a silicon substrate, especially to prevent the formation of conical shapes Silicide (Si cone defeat) in the shallow trench area. BACKGROUND OF THE INVENTION: In recent years, with the rapid increase of the accumulation density of integrated mold circuits, in order to reduce the interval between transistors and ensure that the operation of each transistor is not affected by other transistors, there is a latch-up (Latch Up ) Phenomenon, therefore, shallow trench isolation (Shallow Trench Isolation) occurs; but in the process of performing shallow trench isolation, many difficulties are encountered, such as shallow trench isolation and access to the active component area (active region). The corners usually approach right angles. Therefore, the surface energy at the corners has a small radius of surface energy and its surface energy is very high. Therefore, it is not easy to form a silicon oxide film on it, which makes the transistor easier to advance under normal operation. The kink effect of early tum-on occurs. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs in order to solve the above-mentioned turning effect, in the conventional technology, in the process of forming a shallow trench, the reaction gas will generate a small amount of high-molecular polymer in the shallow trench. On the corner 120, as a tiny etching mask (micro-mask) in the process, the corner 120 of the etched shallow trench will not approach a right angle. As shown in FIG. 1, pad oxidation is first formed on the substrate. Layer 25 and silicon nitride layer 30 ′ and define the shallow trench position, and then remove the pad oxide layer and silicon nitride layer on the shallow trench position, and finally, etch to form the shallow trench, but here the shallow trench is etched When the shallow trench 20 is etched in the process, the contact gas used in the process is helium (He)-oxygen (〇2), carbon tetrafluoride (Cf4), trifluoroalkane (CHF3) and bromine__ 2 This paper size applies + National National Standard (CNS) A4 specification (21〇κ 297 public love) A7 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 444325 V. Description of invention (;). So, during the etching process Will generate high polymer at the corner 120 of the shallow trench, so that the corner 120 will not be shaped The right-angle condition, so 'shallow drainage ditch edges 120 of the polymer plays a slight erosion of the mask during the etch engraved characters curtain. However, there are two types of high-molecular polymers produced in this process: bromide silicide 100 and bromine siloxide 101. The difference between the above two types lies in bromide silicide. 100 is volatile 'and bromine silicon oxide 101 is not easily volatile. However, during the etching process, the above-mentioned high-molecular polymer (sand compound of bromine 100 [SiBrJ and silicon oxide of bromine 101 [siBrx_i〇]) will It is generated at the corner 120 of the shallow trench, and it will also exist in the shallow trench 20. Therefore, the high-molecular polymer (silicide 100 of bromine and silicon oxide of bromine) that exists in the shallow trench 20 during the etching process Object 101) will also form a small etching mask during the etching process, so that a conical silicide 110 is formed in the shallow trench 20. The shallow trench formed in this way will cause poor isolation and poor isolation. The resulting leakage current occurs. If only the silicide 100 of bromine is formed during the etching process, no conical sanding compound no will be generated. Therefore, the present invention discloses a method for forming trenches on a silicon substrate to prevent the problems described in the conventional technology from occurring. Description of the invention: The main object of the present invention is to provide a method for forming trenches on a silicon substrate. In the process of forming shallow trenches, it is possible to avoid the formation of conical silicide in shallow trenches, which can prevent the occurrence of leakage current. . Another object of the present invention is to provide a method for forming a trench on a silicon substrate, which can reduce the non-volatile brominated silicon oxide-containing polymer after etching. The paper size is applicable to the Chinese national standard (CNS > A4 specification ( 210 x 297 mm> -------------- installed! (Guess read the notes on the back before filling in this page)., Line 444325 A7 444325 A7 Intellectual Property Bureau of the Ministry of Economic Affairs Consumption Cooperation Du Printed 5. The invention is described in (3). The invention uses the following technical means to achieve the above-mentioned objectives: First, a pad oxide layer and a silicon nitride layer are formed on a semiconductor substrate, and then A shallow trench region is defined on the silicon nitride layer, and the silicon nitride layer and the pad oxide layer which are not covered by a photoresist are sequentially etched. Then, the shallow trench is etched using a reactive ion etching method. In the process of etching the substrate, it is necessary to pay attention to the conditions of the reaction gas supply. The helium-oxygen, carbon tetrafluoride, gas flow rate or pressure, and RF power are adjusted to make the etching process. Non-volatile bromine-containing silicon Chemicals will not be generated in the shallow trench area. Brief description of the drawings: Figure 1 is a schematic cross-sectional view of etching to form a shallow trench isolation in the conventional art. Figure 2 is an example of the present invention, etching to form a shallow trench Cross-section diagram of trench isolation. Drawing number description: 10- substrate 20- shallow trench 25- pad oxide layer 30- silicon nitride layer 100- bromide silicide 101- bromide silicon oxide 110- conical silicide 120- Shallow trench trench corner invention detailed description: The present invention can be applied to the shallow trench trench manufacturing process for semiconductor manufacturing. By 4 paper sizes, the S0 standard (CNSXA4⑽ (210 X297 mm) is applicable. (Please read the back Please fill in this page again) Pack-line 4443 2 5 a? _ B7___ V. Description of the invention (I) Helium (He)-Oxygen (02), Carbon tetrafluoride (CF4) gas flow (pressure) And RF power control to reduce the formation of bromine-containing silicon oxide polymers in the etching process. The present invention uses specific embodiments of the shallow trench process for making silicon semiconductor substrates to illustrate the principles and spirit of the present invention. First, please See Figure 2. A pad oxide layer is formed on 10, and a silicon nitride layer is formed on the pad oxide layer. The thickness of the pad oxide layer is between 100 angstroms and 500 angstroms. The thickness of the sand is between 500 angstroms and 2000 angstroms. The pad oxide layer is used as a gate oxide layer in the active device region, and the silicon nitride layer is used when the shallow trench is subsequently etched by electrical contact. The etching mask of the oxide layer described above. Next, a spin coating photoresist is applied to the nitrided layer, and exposure and development are performed using a photomask to define a shallow trench 20 Position, then, enter the focus of the present invention, and sequentially use the nitrided sand layer and the pad oxide layer that are not covered by photoresist and are not covered by photoresist, so that the substrate 10 is defined by Uehara The substrate at the position of the shallow trench 20 is exposed, and the remaining silicon nitride layer 30 can protect the pad oxide layer 25 under the silicon nitride layer 30. Next, a reactive channel etching (Reactive ion etching; RIE) method is used to form the shallow trench 20, and the silicon oxide 101, which is not volatile bromine in the conventional technology, remains as a tiny etching mask, and has a cone shape. A shaped silicide 110 is generated in the shallow trench 20, as shown in FIG. In order to reduce the generation of non-volatile bromine silicon oxide 101 during the etching process, the present invention will control the flow of the reaction gas or change the radio frequency power to prevent the formation of bromine silicon oxide 101 during the etching process. 5 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) --------- install --- (Please read the precautions on the back before filling this page) Order and line. Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed on the 5th I Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 4443 25 Description of the Invention (() In this embodiment, the purpose of the present invention can be achieved in the following three ways: 1. The helium (He) -oxygen (〇2) flow rate 'enables the above flow rate to be between 0 and 20 sccm. Therefore, in the process of forming a shallow trench, the supply of oxygen atoms is reduced during the process, so it can suppress the non-volatile The silicon oxide of bromine is generated. 2. Increasing the flow rate of carbon tetrafluoride (CF4) of the reaction gas, the flow rate is between 5 and 30 SCcm, because the above flow rate of carbon tetrafluoride can be increased during the etching process. Strengthen the etching strength, so that during the formation of the shallow trench, the formed polymer can be removed to prevent the formation of the polymer in the shallow trench. 3. Increase the RF power between 800 and 1000 W And reduce the reaction pressure between 30 and 60 mton At high RF power and low pressure, the mean free path of ions is longer, which makes it easier for ions to reach the wafer surface and react with sand atoms, which can increase volatile polymers (bromine Silicide). 4. The above three methods can be used together, so that the obtained effect is the best, or any of the two methods mentioned above can be used together to get the expected effect, in order to solve the conventional technology. In summary, the advantages of the shallow trench isolation method provided by the present invention over the conventional technology are: without adding any process steps and consuming extra costs of the process, the conventional technology can be improved. Existing problems. The above is a detailed description of the present invention using the preferred embodiments, rather than limiting the scope of the present invention. Therefore, those skilled in the art should be able to understand that appropriate changes and adjustments will still be made without loss. The essence of the invention is also not to be outdated. 6 The paper size is applicable due to the National Standard (CNS) A4 specification (210 X 297) «Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 444 3 2 5 _ ^ _ V. Description of the invention (l) Departing from the spirit and scope of the present invention, it should be ^ | this is the state of further implementation of the present invention. I would like to ask your reviewing committee to make a clear reference and pray for your approval. (Please read the precautions on the back before filling out this page.) The size of the paper for the bound and threaded paper is applicable to China National Standard (CNS) A4 (210 X 297 mm)