經濟部中央標準局貝工消费合作社印製 3 7 4 11wf . do 4Q&2Q2 A1 Η 7 五、發明説明（丨） 本發明是有關於一種淺溝渠隔離結構的製造方法，且 特別是有關於一種利用自動對準（self-aligned)罩幕，來進 行淺溝渠隔離結構的製造之方法。 化學機械硏磨法（CMP)是當今能提供一般超大型積體 電路(very large scale integration, VLSI)，甚至於更高精密 度之極大型積體電路(ultra large scale integration, ULSI)製 程中，應用於全面平坦化（global planarization)的一種技 術，由於此項技術極可能成爲半導體業者在大幅降低積體 電路的圖案尺寸（feature size)，所唯一必須依賴的平坦化 製程，因此相關業者莫不全力開發此項技術，以降低生產 成本，提高競爭優勢。 當半導體元件愈趨縮小的情況下，如線寬大小已達 0·25μιη 或甚至 〇·18μηι 的深半次微米（deep sub-half micron) 技術時，以化學機械硏磨法作爲晶片表面平坦化的處理技 術，尤其是在處理淺渠溝表面絕緣層的平坦，已經是愈來 愈重要。但爲了預防以化學機械硏磨法處理面積較大的淺 渠溝表面絕緣層之平坦，所可能發生的凹陷現象（dishing effect)，其中典型的方法即是在製程中提出一種反相罩幕 (reverse tone mask)，並利用回蝕（etch back)製程，以得到 較佳的化學機械硏磨一致性（CMP uniformity)，然而卻可 能因爲光罩對不準效應（misalignment)，造成淺溝渠隔離結 構受到回蝕現象。 第1A圖至第1D圖，其所繪示的係爲習知一種利用反 相罩幕’於淺溝渠隔離結構製造方法的剖面示意圖。請參 ___ 3 本紙^( CNS ) A4規格（21G X297公处） (請先閲讀背面之-意事項再填寫本頁) '裝-· UJ. L----Γ-訂 經濟部中央標準局員工消費合作社印聚 3 74 1twf · Λ7 1Γ 五、發明説明（> ) 照第1A圖，首先提供一半導體基底10，在基底10上沉 積一氮化矽層12，而基底10及氮化矽層12經由微影製程 及非等向性蝕刻後，形成淺溝渠14及主動區域16。 請參考第1B圖，以化學氣相沉積法（CVD)在基底10 上沉積一層二氧化矽之絕緣層18,並塡滿淺溝渠14內部， 然而，由於淺溝渠14凹陷於基底10內，使基底10呈現 出高低起伏之表面，導致二氧化矽層18覆蓋於基底10上 方後，仍無法改變其沉積後所呈現出之高低起伏且較圓滑 的表面。此時，在二氧化矽層18表面塗佈一層光阻劑， 並經由微影形成反相罩幕20。此反相罩幕20覆蓋在淺溝 渠14的上方，並與主動區域16形成互補 (complementarity)。 然而，此反相罩幕20在形成時，卻容易因製程上的誤 差，而造成對不準（misaligned)，導致未完全覆蓋到淺溝渠 14，反相罩幕20會暴露出位於淺溝渠的二氧化矽層18， 在後續進行部分二氧化矽層18的蝕刻步驟時，會去除掉 塡充在淺溝渠中的二氧化矽層18而產生凹槽，可能產生 頸結效應(kink effect)，發生短路現象或漏電流，致使整個 晶片良率受到影響。而且，利用反相罩幕相當於增加一道 額外的罩幕’這會增加整個淺溝渠隔離的製程步驟，對於 製作的成本與製程的複雜性均有很大的影響。 請參考第1C圖’蝕刻未被反相罩幕2〇所覆蓋之二氧 化矽層18 ’接著，再剝除反相罩幕20，在約對應於主動 區16上方形成一凹槽（未標示），留下如圖所示之二氧化矽 4Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 3 7 4 11wf. Do 4Q & 2Q2 A1 Η 7 V. Description of the Invention (丨) The present invention relates to a method for manufacturing a shallow trench isolation structure, and in particular to a method for manufacturing a shallow trench isolation structure. A method of manufacturing a shallow trench isolation structure using a self-aligned mask. Chemical mechanical honing (CMP) is a process that can provide general very large scale integration (VLSI) and even ultra-large scale integration (ULSI) processes with higher precision. A technology applied to global planarization. Because this technology is likely to become the only planarization process that semiconductor manufacturers must rely on to significantly reduce the feature size of integrated circuits, the relevant industry players are doing their best. Develop this technology to reduce production costs and increase competitive advantage. When semiconductor devices are shrinking, such as deep sub-half micron technology, where the line width has reached 0.25 μm or even 0.18 μm, chemical mechanical honing is used to planarize the wafer surface The processing technology, especially the flatness of the insulation layer on the surface of shallow trenches, has become increasingly important. However, in order to prevent the flatness of the insulation layer on the surface of a shallow trench with a large area treated by chemical mechanical honing, a dishing effect may occur. One of the typical methods is to propose an inversion cover in the manufacturing process ( reverse tone mask), and etch back process is used to obtain better CMP uniformity, but it may cause shallow trench isolation structure due to misalignment of the photomask. Affected by etch back. FIG. 1A to FIG. 1D are schematic cross-sectional views showing a conventional method for manufacturing a shallow trench isolation structure using an inversion mask '. Please refer to ___ 3 paper ^ (CNS) A4 specification (21G X297) (Please read the notice on the back before filling out this page) 'Packing- · UJ. L ---- Γ- Set the central standard of the Ministry of Economic Affairs Bureau Consumer Consumption Co., Ltd. 3 74 1twf · Λ7 1Γ V. Description of the Invention According to Figure 1A, a semiconductor substrate 10 is first provided, and a silicon nitride layer 12 is deposited on the substrate 10, and the substrate 10 and nitride After the silicon layer 12 is subjected to a lithography process and anisotropic etching, a shallow trench 14 and an active region 16 are formed. Referring to FIG. 1B, a chemical vapor deposition (CVD) method is used to deposit a silicon dioxide insulating layer 18 on the substrate 10 and fill the interior of the shallow trenches 14. However, since the shallow trenches 14 are recessed in the substrate 10, The substrate 10 exhibits a wavy surface, so that after the silicon dioxide layer 18 covers the substrate 10, it cannot change the wavy and smooth surface that it displays after deposition. At this time, a layer of photoresist is coated on the surface of the silicon dioxide layer 18, and a reverse mask 20 is formed through lithography. This inversion mask 20 covers the shallow trench 14 and forms a complementarity with the active area 16. However, when the inversion mask 20 is formed, it is easy to be misaligned due to process errors, which causes the shallow trench 14 to not be completely covered. The inversion mask 20 will expose the The silicon dioxide layer 18, when the subsequent etching step of the silicon dioxide layer 18 is performed, the silicon dioxide layer 18 filled in the shallow trench is removed and a groove is generated, which may cause a kink effect. A short circuit or leakage current occurs, which affects the yield of the entire chip. Moreover, the use of an inverse mask is equivalent to adding an additional mask ', which will increase the entire process steps of shallow trench isolation, which has a great impact on the cost of production and the complexity of the process. Please refer to FIG. 1C, “etch the silicon dioxide layer 18 not covered by the inversion mask 20”. Then, the inversion mask 20 is peeled off to form a groove (not labeled) corresponding to about the active area 16. ), Leaving silicon dioxide as shown 4
Bl« imm—w I —A —Li— iwi «ml n^i v^X? Ay (請先閱讀背面之.江·意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公楚） 經濟部中央標準局員工消費合作社印製 ^ 4 11wf . doc _________H? _________________ 五、發明説明（3 ) 層 18a。 請參考第ID圖，以化學機械硏磨方式將高於淺渠溝14 表面的二氧化矽層18a硏磨去除，並以氮化矽層12爲硏 磨中止層’磨至暴露出氮化矽層12的表面’使氮化矽12與 絕緣層18b表面高度相同。 有鑑於此，本發明提供了一種淺溝渠隔離結構的製造 方法’利用自動對準罩幕，配合化學機械硏磨的製程來製 作淺溝渠隔離結構，藉以避免光阻對不準而在淺溝集之絕 緣層表面產生凹槽，或是在主動區上方的絕緣層袠面形成 細小的刻痕，而導致頸結效應，發生短路現象，致使整個 晶片良率受到影響。 · 爲達本發明之上述及其他目的，本發明提供〜種淺溝 渠隔離結構之製造方法。首先，提供一半導體基底，在基 底上沉積一氮化矽層，經由微影製程而形成淺溝渠及主動 區域。在基底上依序沉積共形的絕緣層，罩幕層與氧化層。 接著’再利用化學機械硏磨法將部分氧化層磨除，暴露& 對應於主動區之罩幕層，然後，利用蝕刻的方法去除對應 於主動區之罩幕層，暴露出絕緣層，以對應於淺溝渠的罩 幕層爲餓刻中止層，去除氧化層與絕緣層，直至暴露出對 應於淺溝渠的罩幕層。最後，剝除對應於淺溝渠的罩幕層， 再利用化學機械硏磨的方式，磨除絕緣層，直至暴露出主 動區上方之氮化矽層。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 5 m —ϋ ι^ϋ· fl^ V ^^^^1 n^i ^^^^1 n^— ml· n—β a ^ •V? i y (請先閱讀背面之：山意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐〉 經濟部中央標準局員工消費合作社印製 3741twf . doc/ Λ7Bl «imm—w I —A —Li— iwi« ml n ^ iv ^ X? Ay (Please read the .Jiang · Itinerary on the back before filling in this page) The paper size applies to the Chinese National Standard (CNS) Λ4 specification ( 210X297 Gongchu) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs ^ 4 11wf .doc _________H? _________________ V. Description of the Invention (3) Level 18a. Please refer to Figure ID. Honing the silicon dioxide layer 18a above the surface of the shallow trench 14 by chemical mechanical honing, and grinding the silicon nitride layer 12 as a honing stop layer until the silicon nitride is exposed. The surface 'of the layer 12 makes the silicon nitride 12 the same height as the surface of the insulating layer 18b. In view of this, the present invention provides a method for manufacturing a shallow trench isolation structure 'using an automatic alignment mask and a process of chemical mechanical honing to produce a shallow trench isolation structure, so as to avoid misalignment of the photoresist in the shallow trench. A groove is formed on the surface of the insulating layer, or a small nick is formed on the surface of the insulating layer above the active area, which results in a neck-knot effect and a short-circuit phenomenon, which affects the entire wafer yield. In order to achieve the above and other objects of the present invention, the present invention provides a method for manufacturing a shallow trench isolation structure. First, a semiconductor substrate is provided, a silicon nitride layer is deposited on the substrate, and shallow trenches and active regions are formed through a lithography process. A conformal insulating layer, a mask layer and an oxide layer are sequentially deposited on the substrate. Next, the chemical oxide honing method is used to remove a part of the oxide layer to expose the mask layer corresponding to the active area, and then, the mask layer corresponding to the active area is removed by etching, and the insulating layer is exposed to The mask layer corresponding to the shallow trench is a hung-stop layer, and the oxide layer and the insulation layer are removed until the mask layer corresponding to the shallow trench is exposed. Finally, the mask layer corresponding to the shallow trench is removed, and then the insulating layer is removed by chemical mechanical honing, until the silicon nitride layer above the active area is exposed. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below and described in detail with the accompanying drawings, such as 5 m—ϋ ι ^ ϋ · fl ^ V ^ ^^^ 1 n ^ i ^^^^ 1 n ^ — ml · n—β a ^ • V? Iy (please read the back of the page: mountain matters before filling out this page) This paper size applies Chinese National Standard (CNS ) Α4 size (210X297mm) printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 3741twf.doc / Λ7
)V 五、發明説明（V ) 下： 圖式之簡單說明： 第1A圖至第1D圖係繪示習知一種淺溝渠隔離結構製 造方法之剖面示意圖；以及 第2A圖至第2E圖，其所繪示的是依照本發明一較佳 實施例，一種利用自動對準罩幕，來進行淺溝渠隔離結構 製造方法的剖面示意圖。 其中，各圖示之標號所代表的元件結構如下： 1〇，1〇〇 :半導體基底 12，102，氮化矽層 110，110a :罩幕層 14，104 :淺溝渠 16，106 :主動區 18，18a，18b，108，108a，108b :絕緣層 112，112a :氧化層 20 :光阻層 實施例 第2A圖至第2E圖，其所繪示的是依照本發明一較佳 實施例，一種利用自動對準罩幕，來進行淺溝渠隔離結構 製造方法的剖面示意圖。 請參照第2A圖，首先，提供一半導體基底100，在基 底1〇〇上沉積一氮化矽層102，而基底100及氮化矽層102 經由微影製程及非等向性蝕刻後，形成淺溝渠1〇4及主動 區域106。由於佈局上（layout)的規劃及考慮，不同主動區 6 (請先閱讀介面之注意事項再填寫本頁) 裝卜) V V. Description of the invention (V) Below: Brief description of the drawings: Figures 1A to 1D are schematic cross-sectional views showing a conventional method for manufacturing a shallow trench isolation structure; and Figures 2A to 2E, which Shown is a schematic cross-sectional view of a method for manufacturing a shallow trench isolation structure using an automatic alignment mask in accordance with a preferred embodiment of the present invention. Wherein, the element structures represented by the symbols in the figures are as follows: 10, 100: semiconductor substrates 12, 102, silicon nitride layers 110, 110a: mask layers 14, 104: shallow trenches 16, 106: active areas 18, 18a, 18b, 108, 108a, 108b: insulating layer 112, 112a: oxide layer 20: photoresist layer embodiment 2A to 2E, which are shown in accordance with a preferred embodiment of the present invention, A schematic cross-sectional view of a method for manufacturing a shallow trench isolation structure by using an automatic alignment mask. Please refer to FIG. 2A. First, a semiconductor substrate 100 is provided. A silicon nitride layer 102 is deposited on the substrate 100, and the substrate 100 and the silicon nitride layer 102 are formed by a lithography process and anisotropic etching. Shallow trench 104 and active area 106. Due to layout planning and consideration, different active areas 6 (Please read the precautions of the interface before filling out this page)
、1T 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） 741twf. doc/ 741twf. doc/ 鯉濟部中央橾隼局員工消費合作社印製 五'發明説明（) 域106之間所需的隔離程度亦有所不同，因此會形成尺寸 大小不一的淺溝渠104。 請參考第2B圖，例如以化學氣相沉積法(CVD)，在基 底100上沉積一層絕緣層108，並塡滿淺溝渠104內部， 其較佳材質比如爲二氧化矽。然而，由於淺溝渠104凹陷 於基底100內，使基底100呈現出高低起伏之表面，導致 絕緣層108覆蓋於基底100上方後，仍無法改變其沉積後 所呈現出之高低起伏且較圓滑的表面。此時，在絕緣層108 袠面沉積一層共形的罩幕層110，其約對應於主動區106 上方之罩幕層110的高度比約對應於淺溝渠104上方的 高，且其較佳材質比如爲氮化矽。接著，在罩幕層110上 方沉積一層氧化層112，其較佳材質比如爲二氧化矽。 請參考第2C圖，例如利用化學機械硏磨方式，以對 應於主動區106的罩幕層110爲硏磨中止層，將部分氧化 層II2硏磨去除，直至暴露出約對應於主動區106之罩幕 層110，留下如圖所示之氧化層112a，而氧化層112a約 對應於淺溝渠1〇4上方。因爲罩幕層110之材質較氧化層 U2爲硬，因此可保護約對應於主動區106上方的絕緣層 以避免習知因化學機械硏磨法，而在絕緣層（STI oxide) 上造成細小的刻痕（scratch) ’而導致頸結效應，發生短路 現象，致使晶片良率受到影響。 接著，請參考第2D圖，例如利用濕蝕刻或乾蝕刻的 方法，先將暴露出的罩幕層110剝除，留下如圖所示; 應於淺溝渠104之罩幕層110a。接著，以罩幕層li〇a胃 7 (請先閲讀肾面之汰意事項再填寫本頁) --*訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 3 7 411wf doc/ 4Θ5202 3 7 411wf doc/ 4Θ5202 經漭部中央標準局員工消费合作社印裂 H' —---- " ....... ..------------ 五、發明説明（4 ) 蝕刻中止層，例如以濕蝕刻的方法，將氧化層ll2a及部 分絕緣層108去除’直至暴露出罩幕層II〇a，留下如圖所 示之罩幕層ll〇a與絕緣層i〇8a。本發明的特徵之一是利 用對應於主動區106與淺溝渠1〇4上方之罩幕層U()具有 一高度差，以提供一自動對準效果的罩幕層ll〇a，取代習 知利用光阻做爲反相罩幕’應用於淺溝渠隔離的製造方法 中，因此本發明可以避免光阻對不準的問題產生。 然後，請參考第2E圖，例如濕蝕刻或乾蝕刻的方法， 先將罩幕層ll〇a剝除，暴露出絕緣層l〇8a，再以例如化 學機械硏磨法，將部分絕緣層108a去除，直至暴露出氮 化矽層102，留下如圖所示之絕緣層108b。 本發明提供一氮化矽（SiN)爲罩幕層，取代習知的反相 罩幕，不但保有習知利用反相罩幕形成淺溝渠隔離結構的 優點，可以縮短化學機械硏磨所花費的時間，增加化學機 械硏磨的產能與製程的裕度。因爲硏磨時間縮短，也可以 避免一些因爲化學機械硏磨產生的微小凹陷或是缺陷的現 象。而且以氮化矽層（SiN)爲罩幕時，在蝕刻絕緣層時可提 供自動對準的效果，無須擔心如習知利用反相罩幕可能有 光阻對不準的問題產生，不但對於節省成本有很大的助 益，對於提高元件的良率也有很大的功效。 綜上所述’本發明所提出之淺溝渠隔離結構製造方法， 具有以下的特點： (1)本發明之淺溝渠隔離結構製造方法中，可以避免習 知光阻對不準而產生的頸結效應，以及其所導致的短路現 8 本紙張尺度適用中國國家標準「CNS ) A4規格（210X297公" (請先閲讀背面之汰意事項再填寫本頁) 袈·Γ '1Τ 3 74 1twf . doc/d^y ίί 02 Λ? H? — __________ 五、發明説明（1 ) 象，因而提高晶片的良率。 (2) 本發明之淺溝渠隔離結構製造方法中’提供一罩幕 層以避免因化學機械硏磨法，而在主動區上方的絕緣層 (STI oxide)表面造成細小刻痕，導致頸結效應’短路現象 的發生，進而提高晶片的良率。 (3) 本發明之淺溝渠隔離結構製造方法中，可以縮短 化學機械硏磨進行的時間，因此可增加產能與淺溝渠隔離 製程的裕度（window) ’ (4) 本發明之淺溝渠隔離結構製造方法中，縮短了過度 硏磨的時間，對絕緣層的硏磨程度會減少，相對的化學機 械硏磨製程產生的微凹陷與缺陷的現象也會減少。 (5) 本發明之淺溝渠隔離結構製造方法中，客頁 外的反向罩幕及微影製程，這會使得整個淺溝渠隔離的製 程步驟較爲簡化，降低製作的成本。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明’任何熟習此技藝者’在不脫離本發明之精 神和範圍內’當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 -----------, 裝----Γ - IJ- - (請先閱讀背面之：ϊ;一意事項再填寫本頁) 經濟部中央標隼局員工消费合作社印製 9 ^紙度適用中國國家標準（CNS ) A4規格（210X297公浼）、 1T This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 741twf. Doc / 741twf. Doc / Printed by the Consumer Affairs Cooperative of the Central Government Bureau of the Ministry of Civil Affairs of the People's Republic of China (5) Invention Description () between domain 106 The required degree of isolation is also different, so shallow trenches 104 of different sizes are formed. Please refer to FIG. 2B. For example, a chemical vapor deposition (CVD) method is used to deposit an insulating layer 108 on the substrate 100 and fill the inside of the shallow trench 104. A preferred material is silicon dioxide. However, because the shallow trench 104 is recessed in the substrate 100, the substrate 100 presents a undulating surface. After the insulating layer 108 is covered over the substrate 100, the undulating and smooth surface presented by the insulating layer 108 cannot be changed. . At this time, a conformal mask layer 110 is deposited on the surface of the insulating layer 108, which corresponds approximately to the height of the mask layer 110 above the active area 106 to approximately the height above the shallow trench 104, and its preferred material is For example, silicon nitride. Next, an oxide layer 112 is deposited on the mask layer 110, and a preferred material thereof is silicon dioxide. Please refer to FIG. 2C. For example, by using a chemical mechanical honing method, using the mask layer 110 corresponding to the active area 106 as a honing stop layer, honing and removing part of the oxide layer II2 until the exposed area corresponding to The mask layer 110 leaves an oxide layer 112a as shown in the figure, and the oxide layer 112a corresponds approximately to the shallow trench 104. Because the material of the cover layer 110 is harder than the oxide layer U2, it can protect the insulation layer corresponding to the area above the active area 106 to avoid the fineness of the insulation layer (STI oxide) due to the conventional chemical mechanical honing method. Scratches ('scratch') cause the neck knot effect and short circuit phenomenon, which affects the yield of the wafer. Next, please refer to FIG. 2D. For example, by using wet etching or dry etching, the exposed mask layer 110 is first stripped off, leaving the mask layer 110a as shown in the figure. Next, use the curtain layer li〇a stomach 7 (please read the depreciation of the kidney surface before filling out this page)-* The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 3 7 411wf doc / 4Θ5202 3 7 411wf doc / 4Θ5202 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs H '—---- " ....... ..------------ V. Description of the invention (4) The etching stop layer, for example, the wet etching method, removes the oxide layer 112a and part of the insulating layer 108 until the mask layer II0a is exposed, leaving the mask layer 11 as shown in the figure. 〇a and insulation layer 〇8a. One of the features of the present invention is to use the mask layer U () corresponding to the active area 106 and the shallow trench 104 above a height difference to provide an automatically aligned mask layer 110a, instead of the conventional method. The use of a photoresist as an inversion mask is applied to a manufacturing method of shallow trench isolation, so the present invention can avoid the problem of misalignment of the photoresist. Then, referring to FIG. 2E, for example, wet etching or dry etching, the cover layer 110a is first stripped to expose the insulating layer 108a, and then, for example, a chemical mechanical honing method is used to partially remove the insulating layer 108a. It is removed until the silicon nitride layer 102 is exposed, leaving an insulating layer 108b as shown in the figure. The present invention provides a silicon nitride (SiN) as a mask layer, which replaces the conventional inversion mask. Not only does it have the advantages of forming a shallow trench isolation structure using the inversion mask, it can shorten the cost of chemical mechanical honing. Time, increasing the capacity and process margin of chemical mechanical honing. Because the honing time is shortened, some small depressions or defects caused by chemical mechanical honing can also be avoided. Moreover, when a silicon nitride layer (SiN) is used as a mask, an automatic alignment effect can be provided when the insulating layer is etched. There is no need to worry about the problem of misalignment of the photoresist, such as the conventional use of an inverted mask. Cost savings are of great help, and they are also effective in improving the yield of components. In summary, the manufacturing method of the shallow trench isolation structure proposed by the present invention has the following characteristics: (1) In the manufacturing method of the shallow trench isolation structure of the present invention, the neck knot effect caused by inaccurate photoresist can be avoided, And the short circuit caused by it. 8 paper sizes are applicable to the Chinese national standard "CNS" A4 specification (210X297) " (Please read the notice on the back before filling out this page) 袈 · Γ '1Τ 3 74 1twf. Doc / d ^ y ίί 02 Λ? H? — __________ V. Description of the invention (1) The phenomenon, thereby improving the yield of the wafer. (2) In the manufacturing method of the shallow trench isolation structure of the present invention, 'provide a cover layer to avoid chemical The mechanical honing method causes small nicks on the surface of the insulating layer (STI oxide) above the active area, resulting in the occurrence of the neck-junction effect 'short-circuit phenomenon, thereby improving the yield of the wafer. (3) The shallow trench isolation structure of the present invention In the manufacturing method, the time required for chemical mechanical honing can be shortened, so that the capacity and the margin of the shallow trench isolation process can be increased. (4) In the method of manufacturing the shallow trench isolation structure of the present invention, The honing time will reduce the degree of honing of the insulating layer, and the phenomenon of micro depressions and defects generated by the relative chemical mechanical honing process will also be reduced. (5) In the manufacturing method of the shallow trench isolation structure of the present invention, the guest page The external reverse mask and lithography process will simplify the entire shallow trench isolation process steps and reduce the production cost. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in this art' can do various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application. --- --------, Outfit ---- Γ-IJ--(Please read the back: ϊ; please fill in this page if you want to pay attention) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economy 9 ^ paper degree Applicable to China National Standard (CNS) A4 specification (210X297 cm)