US20050191822A1 - Shallow Trench Isolation Method for a Semiconductor Wafer - Google Patents
Shallow Trench Isolation Method for a Semiconductor Wafer Download PDFInfo
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- US20050191822A1 US20050191822A1 US10/908,438 US90843805A US2005191822A1 US 20050191822 A1 US20050191822 A1 US 20050191822A1 US 90843805 A US90843805 A US 90843805A US 2005191822 A1 US2005191822 A1 US 2005191822A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000002955 isolation Methods 0.000 title abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000003989 dielectric material Substances 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 17
- 230000035515 penetration Effects 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 230000003287 optical effect Effects 0.000 claims description 9
- 238000000206 photolithography Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 abstract description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000004075 alteration Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Definitions
- the present invention relates to a shallow trench isolation method for a semiconductor wafer.
- LOCOS localized oxidation isolation
- shallow trench isolation methods are used for isolating the MOS transistors within the semiconductor wafer.
- a SiO 2 layer field oxide layer
- crystal defects associated with generating a field oxide layer with the LOCOS method which include a bird's beak deformity that can affect neighboring components and destroy the integrity of the integrated circuit.
- FIGS. 1 to 6 show the prior art shallow trench isolation method for a semiconductor wafer.
- a semiconductor wafer 10 comprises a Si substrate 14 , a pad oxide layer 16 formed over the Si substrate 14 , and a pad nitride layer 18 deposited above the pad oxide layer 16 .
- the pad oxide layer 16 and pad nitride layer 18 are used as a mask or sacrificial layer during the ion implantation or heat diffusion process which is followed by photolithography and etching to form a plurality of shallow trenches 12 on the surface of the semiconductor wafer 10 .
- CVD chemical vapor deposition
- Si(OC 2 H 5 ) 4 tetra-ethyl-ortho-silicate TEOS
- Poly-Silicon layer is used as a mask.
- CMP chemical mechanical polishing
- the Poly-Silicon 24 and TEOS layer 20 remaining on the surface of the semiconductor wafer 10 is etched with reactive ion etching or magnetically enhanced reactive ion etching techniques.
- the Poly-Silicon 24 remaining after this procedure serves as a mask over the shallow trench 12 .
- several remaining overhangs 26 are formed above the shallow trenches 12 .
- the remaining TEOS layer 20 and several overhangs 26 are then adjusted to form a tighter structure of solid SiO 2 .
- CMP is performed to eliminate the remaining overhangs 26 and to polish the surface of the semiconductor wafer 10 making it flat as shown in FIG. 5 .
- the pad oxide layer 16 and pad nitride layer 18 are stripped by etching. As shown in FIG. 6 , only Si substrate 14 and several shallow trenches 12 of TEOS remain on the surface of semiconductor wafer 10 .
- the overhangs 26 do not work perfectly as masks; therefore, the surface of TEOS in the shallow trench 12 becomes etched. If the shallow trench 12 is big, the surface of TEOS etched is big, and a dish 28 is generated on the surface. The wider the surface, the more severe the dishing which can affect the semiconductor wafer 10 . Also, when depositing the film layer, a focusing problem will occur when transferring patterns.
- the present invention relates to a method for electrically isolating shallow trenches between components on the surface of a semiconductor wafer comprising:
- FIG. 1 to FIG. 6 show the prior art shallow trench isolation method of a semiconductor wafer.
- FIG. 7 to FIG. 11 show a method of forming dummies according to the present invention.
- FIG. 12 to FIG. 14 show another method of forming dummies according to the present invention.
- FIG. 15 to FIG. 17 show a shallow trench isolation method of a semiconductor wafer according to the present invention.
- the present invention relates to a shallow trench isolation method of a semiconductor wafer.
- the method involves first separating large shallow trenches into multiple trenches of smaller width by generating several dummies followed by filling the shallow trenches with dielectric material. Please refer to FIG. 7 to FIG. 11 .
- FIG. 7 to FIG. 11 show a method of forming dummies according to the present invention.
- a semiconductor wafer 30 comprises a Si substrate 34 , a pad oxide layer 36 composed of SiO 2 formed over the Si substrate 34 , and a pad nitride layer 38 composed of Si 3 N 4 deposited over the pad oxide layer 36 .
- shallow isolation trenches are formed on the semiconductor wafer 30 .
- Shallow trenches with widths greater than about 2 ⁇ m are used for generating dummies.
- a plurality of photoresists 32 is applied on the surface of the semiconductor wafer 30 to determine the positions of the shallow trenches by performing photolithography and etching. Then, the surface of the semiconductor wafer 30 is etched. As shown in FIG. 8 , the pad oxide layers 36 and pad nitride layers 38 not covered by photoresists 32 are etched to the Si substrate 34 .
- photolithography and etching are used to place several photoresists 40 at a uniform distance on the surface of the Si substrate 34 .
- the surface of the Si substrate 34 not covered by photoresists 40 is etched.
- several small shallow trenches 42 , 44 are formed on the surface of the Si substrate 34 .
- all photoresists 32 on the surface of the semiconductor wafer 30 are etched.
- a small shallow trench 44 and a big shallow trench 46 are formed on the surface of the semiconductor wafer 30 , and the shallow trench 46 is separated into several small shallow trenches 42 separated by a uniform distance by several dummies 48 .
- the preferred height of the dummy is around 300 ⁇ to 500 ⁇ .
- FIG. 12 shows the second method of forming dummies according to the present invention.
- one mask photo is used to place an optical mask 60 above the semiconductor wafer 30 and to expose and transfer patterns by using different light penetration capability on the optical mask 60 .
- the surface of the semiconductor wafer 30 comprises a Si substrate 34 , a pad oxide layer 36 , a pad nitride layer 38 and a negative photoresist layer 62 .
- the optical mask 60 comprises a plurality of areas (the space parts) of which the light penetration capability is 100%, a plurality of areas (the parts with oblique lines) of which the light penetration capability is 0% and a plurality of areas (the parts with horizontal lines) of which the light penetration capability is between 0% to 100%; therefore, the corresponding photoresists 64 are either completely dissolved, not dissolved at all or partly dissolved on the negative photoresist layer 62 of semiconductor wafer 30 and used as masks. Thus, after etching is repeated, the semiconductor wafer 30 with a plurality of dummies and shallow trenches, as shown in FIG. 11 , is made.
- FIG. 13 and FIG. 14 show the third method of forming dummies according to the present invention and are similar with the second method shown in FIG. 12 .
- a plurality of photoresists 72 is generated by exposing with different degrees of decomposition on the semiconductor wafer 30 twice.
- Three groups of photoresists 72 are formed on the surface of semiconductor wafer 30 and are used as masks when etching. As shown in FIG. 13 , the method requires being exposed twice.
- a plurality of undissolved photoresists 72 are applied to the surface of semiconductor wafer 30 by using an optical mask 70 with areas with light penetration capability of 100% (the space parts) and areas with light penetration capability of 0% (the parts with oblique lines).
- the photoresists 74 that determine the positions of dummies and new shallow trenches are partly dissolved by using another optical mask 80 (as shown FIG. 14 ) comprising both areas with light penetration capability of 100% (the space parts) and 0% (the parts with oblique lines).
- the semiconductor wafer 30 with a plurality of dummies and shallow trenches as shown in FIG. 11 is made.
- FIGS. 15 to 17 show a shallow trench isolation method of a semiconductor wafer according to the present invention.
- a TEOS layer 50 is deposited over the surface of the semiconductor wafer 30 by performing CVD.
- the atoms in the TEOS layer 50 are rearranged by annealing to reduce the defect density of the TEOS layer 50 and to tighten the structure of SiO 2 .
- the TEOS layer 50 deposited over the surface of the semiconductor wafer 30 is a flat surface.
- FIG. 16 shows polishing of the surface of the pad nitride layers 38 of the semiconductor wafer 30 .
- the pad oxide layers 36 and pad nitride layers 38 are etched.
- FIG. 17 only Si substrate 34 and several shallow trenches 42 comprising TEOS are on the surface of semiconductor wafer 30 which is an intact plane, and the dishing on the surface of TEOS in each shallow trench 42 can be avoided.
- the shallow trench isolation method according to the present invention is to first generate several dummies in the bigger shallow trenches to separate the bigger shallow trenches into several shallow trenches with smaller widths to make the surface of the TEOS layer 50 deposited over the surface of the semiconductor wafer 30 flat.
- the TEOS layer 50 is directly annealed without performing reactive ion etching or magnetically enhanced reactive ion etching. The result is an intact plane as the surface of the semiconductor wafer 30 . Without dishing, the semiconductor wafer 30 will not be affected electrically and there will be no focusing problems when transferring patterns.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Element Separation (AREA)
Abstract
The present invention relates to a shallow trench isolation method of a semiconductor wafer. This method can prevent dishing phenomenon from occurring over the surface of some wider shallow trenches when a chemical-mechanical polishing method is used to polish the surface of the dielectric material filled in each shallow trench. The method comprises: (1) choosing the shallow trenches with widths greater than a predetermined size and generating at least one dummy in each chosen shallow trench to form a plurality of new trenches with widths less than the predetermined size; (2) covering the surface of the semiconductor wafer with dielectric material to form a dielectric layer; (3) condensing the dielectric layer; (4) polishing the surface of the dielectric layer filled in all the shallow trenches to align the surface of the dielectric material with the surface of the components on the semiconductor wafer.
Description
- This application is a division of application Ser. No. 09/187,197 filed on Nov. 3, 1998.
- 1. Field of the Invention
- The present invention relates to a shallow trench isolation method for a semiconductor wafer.
- 2. Description of the Prior Art
- Each MOS transistor component on a semiconductor wafer must be well isolated from neighboring components to prevent interference or short circuiting. In general, localized oxidation isolation (LOCOS) and shallow trench isolation methods are used for isolating the MOS transistors within the semiconductor wafer. Using the LOCOS method a SiO2 layer (field oxide layer) is formed with an intra-transistor distance of several thousand angstroms by oxidizing the Si substrate of a semiconductor wafer at a high temperature. However, there are always crystal defects associated with generating a field oxide layer with the LOCOS method which include a bird's beak deformity that can affect neighboring components and destroy the integrity of the integrated circuit.
- At present, the most commonly used isolation method for isolating MOS transistors in semiconductor processing less than 0.25 μm is shallow trench isolation. Although this method effectively achieves electrical isolation by filling dielectric material in the shallow trench between any two neighboring components within the semiconductor wafer, there is still a possibility of the “dishing” phenomenon occurring on the surface of shallow trench. This may affect the electrical performance of the semiconductor wafer. Please refer to FIGS. 1 to 6. FIGS. 1 to 6 show the prior art shallow trench isolation method for a semiconductor wafer. As shown in
FIG. 1 , asemiconductor wafer 10 comprises aSi substrate 14, apad oxide layer 16 formed over theSi substrate 14, and apad nitride layer 18 deposited above thepad oxide layer 16. Thepad oxide layer 16 andpad nitride layer 18 are used as a mask or sacrificial layer during the ion implantation or heat diffusion process which is followed by photolithography and etching to form a plurality ofshallow trenches 12 on the surface of thesemiconductor wafer 10. - Afterwards, chemical vapor deposition (CVD) is performed to deposit a Si(OC2H5)4 (tetra-ethyl-ortho-silicate TEOS) layer and a Poly-Silicon layer in the proper order. As shown in
FIG. 2 , the TEOSlayer 20 covers the entire surface of thesemiconductor wafer 10 and is used as a dielectric layer, and the Poly-Silicon layer 22 is used as a mask. - At this point, the unnecessary parts of the Poly-
Silicon layer 22 are eliminated and the surface of thesemiconductor wafer 10 is polished by chemical mechanical polishing (CMP). As shown inFIG. 3 , the Poly-Silicon 24 in the overlying dishes above the correspondingshallow trenches 12 remain. This makes the surface of the semiconductor wafer 10 flat. - Please refer to
FIG. 4 . The Poly-Silicon 24 and TEOSlayer 20 remaining on the surface of thesemiconductor wafer 10 is etched with reactive ion etching or magnetically enhanced reactive ion etching techniques. The Poly-Silicon 24 remaining after this procedure serves as a mask over theshallow trench 12. After etching, severalremaining overhangs 26 are formed above theshallow trenches 12. Theremaining TEOS layer 20 andseveral overhangs 26 are then adjusted to form a tighter structure of solid SiO2. - CMP is performed to eliminate the
remaining overhangs 26 and to polish the surface of thesemiconductor wafer 10 making it flat as shown inFIG. 5 . Finally, thepad oxide layer 16 andpad nitride layer 18 are stripped by etching. As shown inFIG. 6 , onlySi substrate 14 and severalshallow trenches 12 of TEOS remain on the surface ofsemiconductor wafer 10. - When performing CMP and back etching shown in
FIG. 5 andFIG. 6 , theoverhangs 26 do not work perfectly as masks; therefore, the surface of TEOS in theshallow trench 12 becomes etched. If theshallow trench 12 is big, the surface of TEOS etched is big, and a dish 28 is generated on the surface. The wider the surface, the more severe the dishing which can affect thesemiconductor wafer 10. Also, when depositing the film layer, a focusing problem will occur when transferring patterns. - It is therefore a primary objective of the present invention to provide a shallow trench isolation method of a semiconductor wafer where dishing does not occur to solve the above mentioned problem.
- In a preferred embodiment, the present invention relates to a method for electrically isolating shallow trenches between components on the surface of a semiconductor wafer comprising:
-
- choosing shallow trenches with widths greater than a predetermined size on the surface of the semiconductor wafer and generating at least one dummy in each chosen shallow trench to form a plurality of new shallow trenches with widths less than the predetermined size;
- forming a dielectric layer over the surface of the semiconductor wafer, wherein the dielectric material of the dielectric layer fills each shallow trench on the surface of the semiconductor wafer;
- condensing the dielectric layer; and
- performing a planarization process to polish the surface of the semiconductor wafer for aligning the surface of the dielectric layer inside each shallow trench with the surface of each component on the semiconductor wafer.
- It is an advantage of the present invention that there is no dishing so the semiconductor wafer will not be affected electrically and there will be no focusing problems when transferring patterns.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIG. 1 toFIG. 6 show the prior art shallow trench isolation method of a semiconductor wafer. -
FIG. 7 toFIG. 11 show a method of forming dummies according to the present invention. -
FIG. 12 toFIG. 14 show another method of forming dummies according to the present invention. -
FIG. 15 toFIG. 17 show a shallow trench isolation method of a semiconductor wafer according to the present invention. - The present invention relates to a shallow trench isolation method of a semiconductor wafer. The method involves first separating large shallow trenches into multiple trenches of smaller width by generating several dummies followed by filling the shallow trenches with dielectric material. Please refer to
FIG. 7 toFIG. 11 .FIG. 7 toFIG. 11 show a method of forming dummies according to the present invention. As shown inFIG. 7 , asemiconductor wafer 30 comprises aSi substrate 34, apad oxide layer 36 composed of SiO2 formed over theSi substrate 34, and apad nitride layer 38 composed of Si3N4 deposited over thepad oxide layer 36. First, shallow isolation trenches are formed on thesemiconductor wafer 30. Shallow trenches with widths greater than about 2 μm are used for generating dummies. A plurality ofphotoresists 32 is applied on the surface of thesemiconductor wafer 30 to determine the positions of the shallow trenches by performing photolithography and etching. Then, the surface of thesemiconductor wafer 30 is etched. As shown inFIG. 8 , thepad oxide layers 36 andpad nitride layers 38 not covered byphotoresists 32 are etched to theSi substrate 34. - As shown in
FIG. 9 , photolithography and etching are used to placeseveral photoresists 40 at a uniform distance on the surface of theSi substrate 34. Then, the surface of theSi substrate 34 not covered byphotoresists 40 is etched. As shown inFIG. 10 , several smallshallow trenches Si substrate 34. Finally, allphotoresists 32 on the surface of thesemiconductor wafer 30 are etched. As shown inFIG. 11 , a smallshallow trench 44 and a bigshallow trench 46 are formed on the surface of thesemiconductor wafer 30, and theshallow trench 46 is separated into several smallshallow trenches 42 separated by a uniform distance byseveral dummies 48. In addition, the preferred height of the dummy is around 300 Å to 500 Å. - Also, because of different degrees of exposure (the areas on the optical mask with different light penetration capability), a plurality of dummies is generated at the bottom of the chosen shallow trenches at the time the shallow trenches are first formed. Please refer to
FIG. 12 .FIG. 12 shows the second method of forming dummies according to the present invention. In this scheme, one mask photo is used to place anoptical mask 60 above thesemiconductor wafer 30 and to expose and transfer patterns by using different light penetration capability on theoptical mask 60. The surface of thesemiconductor wafer 30 comprises aSi substrate 34, apad oxide layer 36, apad nitride layer 38 and anegative photoresist layer 62. Theoptical mask 60 comprises a plurality of areas (the space parts) of which the light penetration capability is 100%, a plurality of areas (the parts with oblique lines) of which the light penetration capability is 0% and a plurality of areas (the parts with horizontal lines) of which the light penetration capability is between 0% to 100%; therefore, the correspondingphotoresists 64 are either completely dissolved, not dissolved at all or partly dissolved on thenegative photoresist layer 62 ofsemiconductor wafer 30 and used as masks. Thus, after etching is repeated, thesemiconductor wafer 30 with a plurality of dummies and shallow trenches, as shown inFIG. 11 , is made. - Please refer to
FIG. 13 andFIG. 14 .FIG. 13 andFIG. 14 show the third method of forming dummies according to the present invention and are similar with the second method shown inFIG. 12 . In the third method, a plurality ofphotoresists 72 is generated by exposing with different degrees of decomposition on thesemiconductor wafer 30 twice. Three groups ofphotoresists 72, completely dissolved, undissolved and partly dissolved, are formed on the surface ofsemiconductor wafer 30 and are used as masks when etching. As shown inFIG. 13 , the method requires being exposed twice. First, a plurality ofundissolved photoresists 72 are applied to the surface ofsemiconductor wafer 30 by using anoptical mask 70 with areas with light penetration capability of 100% (the space parts) and areas with light penetration capability of 0% (the parts with oblique lines). Next, thephotoresists 74 that determine the positions of dummies and new shallow trenches are partly dissolved by using another optical mask 80 (as shownFIG. 14 ) comprising both areas with light penetration capability of 100% (the space parts) and 0% (the parts with oblique lines). After etching, thesemiconductor wafer 30 with a plurality of dummies and shallow trenches as shown inFIG. 11 is made. - Please refer to FIGS. 15 to 17. FIGS. 15 to 17 show a shallow trench isolation method of a semiconductor wafer according to the present invention. After the
dummies 48 and small shallow trenches are formed, aTEOS layer 50 is deposited over the surface of thesemiconductor wafer 30 by performing CVD. The atoms in theTEOS layer 50 are rearranged by annealing to reduce the defect density of theTEOS layer 50 and to tighten the structure of SiO2. When a plurality ofdummies 48 are filled in the bigshallow trench 46, the difference between the length of theTEOS layer 50 deposited over the bigshallow trench 46 and the length of theTEOS layer 50 deposited over the other parts of the surface of thesemiconductor wafer 30 is reduced. Therefore, theTEOS layer 50 deposited over the surface of thesemiconductor wafer 30 is a flat surface. - After tightening the
TEOS layer 50, the surface ofsemiconductor wafer 30 is polished by performing CMP.FIG. 16 shows polishing of the surface of the pad nitride layers 38 of thesemiconductor wafer 30. Finally, the pad oxide layers 36 and pad nitride layers 38 are etched. As shown inFIG. 17 , onlySi substrate 34 and severalshallow trenches 42 comprising TEOS are on the surface ofsemiconductor wafer 30 which is an intact plane, and the dishing on the surface of TEOS in eachshallow trench 42 can be avoided. - Compared with the prior art, the shallow trench isolation method according to the present invention is to first generate several dummies in the bigger shallow trenches to separate the bigger shallow trenches into several shallow trenches with smaller widths to make the surface of the
TEOS layer 50 deposited over the surface of thesemiconductor wafer 30 flat. At the same time, theTEOS layer 50 is directly annealed without performing reactive ion etching or magnetically enhanced reactive ion etching. The result is an intact plane as the surface of thesemiconductor wafer 30. Without dishing, thesemiconductor wafer 30 will not be affected electrically and there will be no focusing problems when transferring patterns. - Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (5)
1. A method for forming electrically isolating shallow trenches between components on the surface of a semiconductor wafer comprising:
(a) providing a semiconductor substrate having at least a first-type trench region used to form a first-type trench, and a second-type trench region used to form a second-type trench, the first-type trench having a width greater than a predetermined value that is greater than a width of the second-type trench;
(b) forming a first photoresist pattern on the semiconductor substrate exposing the first-type trench region and the second-type trench region, and at least a second photoresist pattern on the first-type trench region, the second photoresist pattern having a smaller height than the first photoresist pattern;
(c) etching the first-type trench region and the second-type trench region to form the first-type trench and the second-type trench with the first photoresist pattern as a mask, and to form at least one dummy at a bottom of the first-type trench with the second photoresist pattern as a mask;
(d) stripping the first photoresist pattern and the second photoresist pattern;
(e) forming a dielectric layer over the surface of the semiconductor substrate, wherein the dielectric material of the dielectric layer fills the first-type trench and the second-type trench on the surface of the semiconductor substrate;
(f) condensing the dielectric layer; and
(g) performing a planarization process to polish the surface of the semiconductor wafer for aligning the surface of the dielectric layer inside each of the first-type trench and the second-type trench with the surface of each component on the semiconductor substrate.
2. The method of claim 1 further comprising:
forming a photoresist layer over the semiconductor wafer; and
utilizing an optical mask of different sets of light penetration capability to perform a photolithography process on the photoresist layer for simultaneously forming the first photoresist pattern and the second photoresist pattern in the photoresist layer.
3. The method of claim 1 further comprising:
forming a photoresist layer over the semiconductor wafer;
exposing the photoresist layer to light through a first optical mask of different sets of light penetration capability to define the first photoresist pattern;
exposing the photoresist layer to light through a second optical mask of different sets of light penetration capability to define the second photoresist pattern; and
developing the photoresist layer to form the first photoresist pattern and the second pattern.
4. The method of claim 1 wherein the predetermined value is about 2 μm.
5. The method of claim 1 wherein a preferred height of any dummy is around 300 Å to 500 Å.
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US10/908,438 US20050191822A1 (en) | 1998-11-03 | 2005-05-12 | Shallow Trench Isolation Method for a Semiconductor Wafer |
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US09/187,197 US7045435B1 (en) | 1998-11-03 | 1998-11-03 | Shallow trench isolation method for a semiconductor wafer |
US10/908,438 US20050191822A1 (en) | 1998-11-03 | 2005-05-12 | Shallow Trench Isolation Method for a Semiconductor Wafer |
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US09/187,197 Division US7045435B1 (en) | 1998-11-03 | 1998-11-03 | Shallow trench isolation method for a semiconductor wafer |
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US09/187,197 Expired - Lifetime US7045435B1 (en) | 1998-11-03 | 1998-11-03 | Shallow trench isolation method for a semiconductor wafer |
US10/908,438 Abandoned US20050191822A1 (en) | 1998-11-03 | 2005-05-12 | Shallow Trench Isolation Method for a Semiconductor Wafer |
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US09/187,197 Expired - Lifetime US7045435B1 (en) | 1998-11-03 | 1998-11-03 | Shallow trench isolation method for a semiconductor wafer |
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Cited By (4)
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US20080217714A1 (en) * | 2007-03-07 | 2008-09-11 | Omar Zia | Semiconductor device having tiles for dual-trench integration and method therefor |
US8796150B2 (en) | 2011-01-24 | 2014-08-05 | International Business Machines Corporation | Bilayer trench first hardmask structure and process for reduced defectivity |
US20180190538A1 (en) * | 2016-12-29 | 2018-07-05 | United Microelectronics Corp. | Method of fabricating sti trench |
EP3944288A4 (en) * | 2019-03-20 | 2022-11-16 | Kabushiki Kaisha Toshiba | Semiconductor wafer and method of manufacturing semiconductor device |
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US20050014364A1 (en) * | 2003-07-18 | 2005-01-20 | Infineon Technologies North America Corp. | Method of suppressing the effect of shining spots present at the edge of a wafer |
US7268687B2 (en) * | 2004-03-23 | 2007-09-11 | 3M Innovative Properties Company | Radio frequency identification tags with compensating elements |
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US20080217714A1 (en) * | 2007-03-07 | 2008-09-11 | Omar Zia | Semiconductor device having tiles for dual-trench integration and method therefor |
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US8796150B2 (en) | 2011-01-24 | 2014-08-05 | International Business Machines Corporation | Bilayer trench first hardmask structure and process for reduced defectivity |
US20180190538A1 (en) * | 2016-12-29 | 2018-07-05 | United Microelectronics Corp. | Method of fabricating sti trench |
US10192777B2 (en) * | 2016-12-29 | 2019-01-29 | United Microelectronics Corp. | Method of fabricating STI trench |
EP3944288A4 (en) * | 2019-03-20 | 2022-11-16 | Kabushiki Kaisha Toshiba | Semiconductor wafer and method of manufacturing semiconductor device |
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