KR20030058641A - Method for manufacturing transistor of semiconductor device - Google Patents
Method for manufacturing transistor of semiconductor device Download PDFInfo
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- KR20030058641A KR20030058641A KR1020010089165A KR20010089165A KR20030058641A KR 20030058641 A KR20030058641 A KR 20030058641A KR 1020010089165 A KR1020010089165 A KR 1020010089165A KR 20010089165 A KR20010089165 A KR 20010089165A KR 20030058641 A KR20030058641 A KR 20030058641A
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- layer
- polycrystalline silicon
- gate electrode
- forming
- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 102
- 239000011229 interlayer Substances 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 230000001105 regulatory effect Effects 0.000 claims description 5
- 238000011109 contamination Methods 0.000 abstract description 5
- 239000000969 carrier Substances 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009812 interlayer coupling reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 트랜지스터 및 그의 제조 방법에 관한 것으로, 특히 리플레이스먼트(Replacement) 공정을 사용하여 금속 게이트 전극을 형성하는 공정에 있어서, 금속층 둘레에 다결정 실리콘층이 형성된 게이트 전극을 형성하므로 소자의 수율 및 신뢰성을 향상시키는 반도체 소자의 트랜지스터 및 그의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor of a semiconductor device and a method of manufacturing the same. In particular, in the process of forming a metal gate electrode by using a replacement process, the device is formed by forming a gate electrode having a polycrystalline silicon layer around the metal layer. The present invention relates to a transistor of a semiconductor device and a method of manufacturing the same, which improve the yield and reliability thereof.
도 1a 내지 도 1d는 종래 기술에 따른 트랜지스터의 제조 방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a transistor according to the prior art.
도 1a를 참조하면, 소자분리 영역에 소자분리막(12)이 형성되며 p형인 반도체 기판(11) 상부에 산화막(13), 다결정 실리콘층 및 감광막(도시하지 않음)을 순차적으로 형성한다.Referring to FIG. 1A, an isolation layer 12 is formed in an isolation region, and an oxide layer 13, a polycrystalline silicon layer, and a photoresist layer (not shown) are sequentially formed on the p-type semiconductor substrate 11.
그리고, 상기 감광막을 게이트 전극이 형성될 부위에만 남도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 감광막을 마스크로 상기 다결정 실리콘층 및 산화막(13)을 선택 식각한 다음. 상기 감광막을 제거한다. 이때, 상기 식각된 다결정 실리콘층으로 더미(Dummy) 게이트 전극(15)을 형성한다.And selectively exposing and developing the photoresist film so as to remain only at the site where the gate electrode is to be formed, and then selectively etching the polycrystalline silicon layer and the oxide film 13 using the selectively exposed and developed photoresist film as a mask. The photosensitive film is removed. In this case, a dummy gate electrode 15 is formed of the etched polycrystalline silicon layer.
이어, 상기 더미 게이트 전극(15)을 마스크로 n형 불순물 이온을 주입하고 드라이브-인(Drive-in) 공정을 실시하여 상기 더미 게이트 전극(15) 양측의 반도체 기판(11) 표면 내에 소오스/드레인 영역(17)을 형성한다.Subsequently, n-type impurity ions are implanted using the dummy gate electrode 15 as a mask, and a drive-in process is performed to form a source / drain in the surface of the semiconductor substrate 11 on both sides of the dummy gate electrode 15. The region 17 is formed.
도 1b에서와 같이, 상기 더미 게이트 전극(15)을 포함한 전면에 층간절연막(19)을 형성하고, 상기 더미 게이트 전극(15)을 식각 방지막으로 하는 화학적 기계 연마 방법에 의해 상기 층간 절연막(19)을 평탄 식각하여 상기 더미 게이트 전극(15)을 노출시킨다.As shown in FIG. 1B, an interlayer insulating film 19 is formed on the entire surface including the dummy gate electrode 15, and the interlayer insulating film 19 is formed by a chemical mechanical polishing method using the dummy gate electrode 15 as an etch stop layer. Planar etching is performed to expose the dummy gate electrode 15.
도 1c에서와 같이, 상기 노출된 더미 게이트 전극(15)과 산화막(13)을 제거하여 반도체 기판(11)을 노출시킨다.As shown in FIG. 1C, the exposed dummy gate electrode 15 and the oxide layer 13 are removed to expose the semiconductor substrate 11.
도 1d에서와 같이, 상기 노출된 반도체 기판(11) 상부에 게이트 산화막(21)을 성장시킨다.As shown in FIG. 1D, the gate oxide layer 21 is grown on the exposed semiconductor substrate 11.
그리고, 상기 게이트 산화막(21)을 포함한 층간 절연막(19) 상부에 텅스텐층을 형성하고, 상기 층간 절연막(19)을 식각 방지막으로 하는 화학적 기계 연마 방법에 의해 상기 텅스텐층을 식각하여 게이트 전극(23)을 형성한다.The tungsten layer is etched by a chemical mechanical polishing method in which a tungsten layer is formed on the interlayer insulating film 19 including the gate oxide film 21, and the interlayer insulating film 19 is an etch stop layer. ).
그러나, 종래의 반도체 소자의 트랜지스터 및 그의 제조 방법은 리플레이스먼트 공정을 사용하여 금속 게이트 전극을 형성하는 공정에 있어서 다음과 같은 이유에 의해 소자의 수율 및 신뢰성이 저하되는 문제점이 있었다.However, the transistor of the conventional semiconductor device and its manufacturing method have a problem that the yield and reliability of the device are deteriorated in the step of forming a metal gate electrode using a replacement process for the following reasons.
첫째, 게이트 전극의 금속층이 노출되어 금속에 의한 오염 가능성 및 후속 공정에 제약이 따르고 핫 캐리어(Hot carrier)에 대한 신뢰성을 향상시키기 위한 게이트 전극의 선택 산화 공정이 불가능하다.First, the metal layer of the gate electrode is exposed, thereby limiting the possibility of contamination by the metal and subsequent processes, and it is impossible to perform a selective oxidation process of the gate electrode to improve reliability of the hot carrier.
둘째, 상기 금속층의 노출을 방지하기 위해 캡(Cap) 절연막을 형성할 경우 층간 커플링 캐패시턴스가 증가한다.Second, when the cap insulating film is formed to prevent the metal layer from being exposed, the interlayer coupling capacitance increases.
셋째, 문턱 전압 조절 이온 주입 영역과 소오스/드레인 영역간에 중첩되는 영역이 존재하여 접합 캐패시턴스(Capacitance)가 크고 핫 캐리어에 대한 신뢰성이저하된다.Third, an overlapping region exists between the threshold voltage regulation ion implantation region and the source / drain region, resulting in high junction capacitance and low reliability of the hot carrier.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 리플레이스먼트 공정을 사용하여 금속 게이트 전극을 형성하는 공정에 있어서, 금속층 둘레에 다결정 실리콘층이 형성된 게이트 전극을 형성하므로, 금속의 오염을 방지하고 후속 공정에 제약이 없으며, 핫 캐리어에 대한 신뢰성을 향상시키는 반도체 소자의 트랜지스터 및 그의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, in the process of forming a metal gate electrode using a replacement process, forming a gate electrode formed with a polycrystalline silicon layer around the metal layer, thereby preventing metal contamination An object thereof is to provide a transistor of a semiconductor device and a method of manufacturing the same, which are not limited to subsequent processes and improve reliability of hot carriers.
도 1a 내지 도 1d는 종래 기술에 따른 트랜지스터의 제조 방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a transistor according to the prior art.
도 2a 내지 도 2g는 본 발명의 실시 예에 따른 트랜지스터의 제조 방법을 도시한 단면도.2A to 2G are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
11, 31 : 반도체 기판12, 32 : 소자분리막11, 31: semiconductor substrate 12, 32: device isolation film
13 : 산화막15 : 더미 게이트 전극13 oxide film 15 dummy gate electrode
17 : 소오스/드레인 영역19, 47 : 층간 절연막17 source / drain regions 19, 47 interlayer insulating film
21, 33 : 게이트 산화막23 : 게이트 전극21, 33: gate oxide film 23: gate electrode
35 : 제 1 다결정 실리콘층37 : 제 1 질화막35 first polycrystalline silicon layer 37 first nitride film
39 : 열산화막41 : 저농도 불순물 영역39: thermal oxide film 41: low concentration impurity region
43 : 산화막 스페이서45 : 고농도 불순물 영역43: oxide spacer 45: high concentration impurity region
49 : 문턱 전압 조절 이온 주입 영역51 : 제 2 다결정 실리콘층49 threshold voltage control ion implantation region 51 second polycrystalline silicon layer
53 : 텅스텐층55 : 제 3 다결정 실리콘층53 tungsten layer 55 third polycrystalline silicon layer
이상의 목적을 달성하기 위한 본 발명은 반도체 소자의 트랜지스터에 있어서, 중앙부보다 에지부가 두껍게 형성된 게이트 절연막, 내측에 금속층이 구비된 다결정 실리콘으로 상기 게이트 절연막 상부에 형성된 게이트 전극 및 상기 게이트 전극 양측의 반도체 기판에 형성된 소오스/드레인 불순물 영역을 포함하는 반도체 소자의 트랜지스터를 제공하는 것과,The present invention for achieving the above object is a transistor of a semiconductor device, the gate insulating film having a thicker edge portion than the center portion, the gate electrode formed on the gate insulating film made of polycrystalline silicon having a metal layer inside the semiconductor substrate on both sides of the gate electrode Providing a transistor of a semiconductor device comprising a source / drain impurity region formed in
상기 게이트 절연막은 산화막, 질화막 또는 Ta2O5층으로 형성되는 것을 특징으로 한다.The gate insulating film is formed of an oxide film, a nitride film or a Ta 2 O 5 layer.
그리고, 본 발명은 게이트 전극이 형성될 부위의 반도체 기판 상부에 게이트 절연막/제 1 다결정 실리콘층/하드 마스크층의 적층 구조물을 형성하는 단계, 상기 제 1 다결정 실리콘층의 측벽과 에지부에 열산화막을 성장시키는 단계, 상기 하드 마스크층을 포함한 제 1 다결정 실리콘층 측벽에 절연막 스페이서를 형성하고, 상기 제 1 다결정 실리콘층 양측의 반도체 기판 표면 내에 LDD 구조의 소오스/드레인 불순물 영역을 형성하는 단계, 전면에 층간 절연막을 형성하고 평탄 식각하여 상기 하드 마스크층을 노출 시키는 단계, 상기 하드 마스크층을 제거하고, 채널 영역에 문턱 전압 조절 이온 주입 영역을 형성하는 단계, 전면에 제 2 다결정 실리콘층과 금속층을 순차적으로 형성하고, 상기 금속층을 에치백하는 단계 및 전면에 제 3 다결정 실리콘층을 형성한 후, 상기 층간 절연막을 식각 방지막으로 상기 제 2, 제 3 다결정 실리콘층을 평탄 식각하여 상기 금속층 둘레에 제 1, 제 2, 제 3 다결정 실리콘층이 형성된 게이트 전극을 형성하는 단계를 포함하는 반도체 소자의 트랜지스터 제조 방법을 제공하는 것과,The present invention also provides a method of forming a stack structure of a gate insulating film, a first polycrystalline silicon layer, and a hard mask layer on a semiconductor substrate at a portion where a gate electrode is to be formed, and a thermal oxide layer on sidewalls and edges of the first polycrystalline silicon layer. Forming an insulating film spacer on sidewalls of the first polycrystalline silicon layer including the hard mask layer, and forming a source / drain impurity region having an LDD structure in a semiconductor substrate surface on both sides of the first polycrystalline silicon layer; Forming an interlayer insulating film on the substrate to expose the hard mask layer by removing the hard mask layer, forming a threshold voltage control ion implantation region in a channel region, and forming a second polycrystalline silicon layer and a metal layer on the entire surface thereof. Forming sequentially, etching back the metal layer and forming a third polycrystalline silicon layer on the front surface. And forming a gate electrode having the first, second, and third polycrystalline silicon layers formed around the metal layer by etching the second and third polycrystalline silicon layers using the interlayer insulating layer as an etch stop layer. Providing a method for manufacturing a transistor of the device,
상기 게이트 절연막을 산화막, 질화막 또는 Ta2O5층으로 형성하는 것을 특징으로 한다.The gate insulating film is formed of an oxide film, a nitride film or a Ta 2 O 5 layer.
본 발명의 원리는 리플레이스먼트 공정을 사용하여 금속 게이트 전극을 형성하는 공정에 있어서, 금속층 둘레에 다결정 실리콘층이 형성된 게이트 전극을 형성하므로, 게이트 전극의 금속층이 다결정 실리콘층에 의해 캡핑되므로 금속의 오염을 방지하고 후속 공정에 제약이 없고, 게이트 전극의 선택 산화 공정이 가능하여 게이트 전극 양쪽 에지(Edge)부의 산화막 두께가 중앙부보다 두꺼워 핫 캐리어에 대한 신뢰성을 향상시키고, 또한 문턱 전압 조절 이온 주입 영역과 소오스/드레인 영역간에 중첩되지 않아 최대 전계 값을 낮추어 접합 캐패시턴스가 작고 핫 캐리어에 대한 신뢰성을 향상시키는 발명이다.The principle of the present invention is to form a gate electrode having a polycrystalline silicon layer around the metal layer in the process of forming a metal gate electrode using a replacement process, so that the metal layer of the gate electrode is capped by the polycrystalline silicon layer so that It prevents contamination, and there is no restriction in the subsequent process, and the selective oxidation process of the gate electrode is possible, so that the thickness of the oxide on both edges of the gate electrode is thicker than the center portion, which improves the reliability of the hot carrier, and also the threshold voltage control ion implantation region. The invention does not overlap between the and source / drain regions, thereby lowering the maximum electric field value, thereby reducing the junction capacitance and improving reliability of the hot carrier.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2g는 본 발명의 실시 예에 따른 트랜지스터의 제조 방법을 도시한 단면도이다.2A to 2G are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention.
도 2a를 참조하면, 소자분리 영역에 소자분리막(32)이 형성되며 p형인 반도체 기판(31) 상부에 게이트 산화막(33), 제 1 다결정 실리콘층(35) 및 제 1 질화막(37)을 순차적으로 형성한다. 이때, 상기 게이트 산화막(33) 대신에 질화막 또는 Ta2O5층으로 형성할 수 있다.Referring to FIG. 2A, the device isolation layer 32 is formed in the device isolation region, and the gate oxide layer 33, the first polycrystalline silicon layer 35, and the first nitride layer 37 are sequentially formed on the p-type semiconductor substrate 31. To form. In this case, the gate oxide layer 33 may be formed of a nitride layer or a Ta 2 O 5 layer.
그리고, 게이트 전극용 마스크를 사용한 사진 식각 공정에 의해 상기 제 1 질화막(37), 제 1 다결정 실리콘층(35) 및 게이트 산화막(33)을 식각한다.The first nitride film 37, the first polycrystalline silicon layer 35, and the gate oxide film 33 are etched by a photolithography process using a gate electrode mask.
도 2b를 참조하면, 전면의 선택 열산화 공정으로 상기 제 1 다결정 실리콘층(35)의 측벽과 에지부에 열산화막(39)을 성장시킨다.Referring to FIG. 2B, a thermal oxide film 39 is grown on sidewalls and edges of the first polycrystalline silicon layer 35 by a selective thermal oxidation process on the entire surface.
도 2c를 참조하면, 상기 제 1 다결정 실리콘층(35)을 마스크로 저 농도, 저 에너지의 n형 불순물 이온을 주입하고 드라이브-인 공정을 실시하여 상기 제 1 다결정 실리콘층(35) 양측의 반도체 기판(31) 표면 내에 저농도 불순물 영역(41)을 형성한다.Referring to FIG. 2C, semiconductors on both sides of the first polycrystalline silicon layer 35 are implanted by implanting n-type impurity ions having low concentration and low energy using the first polycrystalline silicon layer 35 as a mask and performing a drive-in process. A low concentration impurity region 41 is formed in the surface of the substrate 31.
그리고, 상기 제 1 다결정 실리콘층(35)을 포함한 전면에 산화막을 형성하고, 에치백하여 상기 제 1 다결정 실리콘층(35) 양측의 반도체 기판(31) 상부에 산화막 스페이서(43)를 형성한다.An oxide film is formed on the entire surface including the first polycrystalline silicon layer 35 and etched back to form an oxide spacer 43 on the semiconductor substrate 31 on both sides of the first polycrystalline silicon layer 35.
이어, 상기 산화막 스페이서(43)를 포함한 제 1 다결정 실리콘층(35)을 마스크로 고 농도, 고 에너지의 n형 불순물 이온을 주입하고 드라이브-인 공정을 실시하여 상기 산화막 스페이서(43)를 포함한 제 1 다결정 실리콘층(35) 양측의 반도체 기판(31) 표면 내에 고농도 불순물 영역(45)을 형성한다.Subsequently, a high concentration and high energy n-type impurity ions are implanted using the first polycrystalline silicon layer 35 including the oxide film spacer 43 as a mask, and a drive-in process is performed to produce the first spacer including the oxide film spacer 43. 1 A high concentration impurity region 45 is formed in the surface of the semiconductor substrate 31 on both sides of the polycrystalline silicon layer 35.
여기서, 상기 저농도 불순물 영역(41)과 고농도 불순물 영역(45)으로 LDD 구조의 소오스/드레인 불순물 영역을 형성한다.Here, a source / drain impurity region having an LDD structure is formed of the low concentration impurity region 41 and the high concentration impurity region 45.
도 2d를 참조하면, 상기 제 1 다결정 실리콘층(35)을 포함한 전면에 층간 절연막(47)을 형성하고, 상기 제 1 질화막(37)을 식각 방지막으로 하는 화학적 기계 연마 방법에 의해 상기 층간 절연막(47)을 평탄 식각한다.Referring to FIG. 2D, an interlayer insulating film 47 is formed on the entire surface including the first polycrystalline silicon layer 35 and the first insulating film 37 is formed by the chemical mechanical polishing method using the first nitride film 37 as an etch stop layer. 47) is etched flat.
도 2e를 참조하면, 상기 노출된 제 1 질화막(37)을 제거하고, 이온 주입 공정으로 전면에 문턱 전압 조절 이온을 주입하고 드라이브 인 공정을 실시하여 문턱 전압 조절 이온 주입 영역(49)을 형성한다. 이때, 상기 문턱 전압 조절 이온의 에너지를 조절하여 채널 영역의 가운데에는 표면에 도펀트(Dopant)가 집중되게 하고 채널 영역의 양쪽 끝 영역에는 상기 열산화막(39)에 의해 블로킹(Blocking)이 되도록 한다.Referring to FIG. 2E, the exposed first nitride layer 37 is removed, a threshold voltage regulating ion is implanted into the entire surface by an ion implantation process, and a drive in process is performed to form a threshold voltage regulating ion implantation region 49. . At this time, the dopant is concentrated on the surface in the center of the channel region by controlling the energy of the threshold voltage regulating ions and blocking is performed by the thermal oxide film 39 at both end regions of the channel region.
도 2f를 참조하면, 상기 층간 절연막(47)을 포함한 전면에 제 2 다결정 실리콘층(51)과 텅스텐층(53)을 순차적으로 형성하고, 상기 텅스텐층(53)을 에치백한다.Referring to FIG. 2F, a second polycrystalline silicon layer 51 and a tungsten layer 53 are sequentially formed on the entire surface including the interlayer insulating layer 47, and the tungsten layer 53 is etched back.
도 2g를 참조하면, 상기 텅스텐층(53)을 포함한 제 2 다결정 실리콘층(51) 상부에 제 3 다결정 실리콘층(55)을 형성한 후, 상기 층간 절연막(47)을 식각 방지막으로 하는 화학적 기계 연마 방법에 의해 상기 제 2, 제 3 다결정실리콘층(51,55)을 평탄 식각한다. 이때, 상기 텅스텐층(53) 둘레에 제 1, 제 2, 제 3 다결정 실리콘층(35,51,55)층이 형성된 게이트 전극을 형성한다.Referring to FIG. 2G, after the third polycrystalline silicon layer 55 is formed on the second polycrystalline silicon layer 51 including the tungsten layer 53, the chemical interlayer insulating film 47 is used as an etch stop layer. The second and third polysilicon layers 51 and 55 are etched flat by the polishing method. In this case, a gate electrode having first, second, and third polycrystalline silicon layers 35, 51, and 55 layers formed around the tungsten layer 53 is formed.
본 발명의 반도체 소자의 트랜지스터 및 그의 제조 방법은 다마신 공정을 사용하여 금속 게이트 전극을 형성하는 공정에 있어서, 금속층 둘레에 다결정 실리콘층이 형성된 게이트 전극을 형성하므로, 다음과 같은 이유에 의해 소자의 수율 및 신뢰성을 향상시키는 효과가 있다.In the transistor of the semiconductor device of the present invention and a method of manufacturing the same, in the step of forming a metal gate electrode using a damascene process, a gate electrode having a polycrystalline silicon layer is formed around the metal layer. There is an effect of improving the yield and reliability.
첫째, 게이트 전극의 금속층이 다결정 실리콘층에 의해 캡핑(Capping)되므로 금속의 오염을 방지하고 후속 공정에 제약이 없다.First, the metal layer of the gate electrode is capped by the polycrystalline silicon layer to prevent contamination of the metal and there is no restriction on subsequent processes.
둘째, 게이트 전극의 선택 산화 공정이 가능하여 게이트 전극 양쪽 에지부의 산화막 두께가 중앙부보다 두꺼워 핫 캐리어에 대한 신뢰성을 향상시킨다.Second, the selective oxidation process of the gate electrode is possible, so that the thickness of the oxide film at both edges of the gate electrode is thicker than the center portion, thereby improving reliability of the hot carrier.
셋째, 문턱 전압 조절 이온 주입 영역과 소오스/드레인 영역간에 중첩되지 않아 최대 전계 값을 낮추어 접합 캐패시턴스가 작고 핫 캐리어에 대한 신뢰성을 향상시킨다.Third, there is no overlap between the threshold voltage regulating ion implantation region and the source / drain region, thereby lowering the maximum electric field value, resulting in small junction capacitance and improved reliability for hot carriers.
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| DE19946437A1 (en) * | 1999-09-28 | 2001-04-12 | Infineon Technologies Ag | Ferroelectric transistor |
| KR100313605B1 (en) * | 1999-10-07 | 2001-11-09 | 김영환 | A semiconductor device and fabricating method thereof |
| US6174776B1 (en) * | 1999-10-22 | 2001-01-16 | United Microelectronics Corp. | Method for forming gate contact in complementary metal oxide semiconductor |
| JP2001196581A (en) * | 2000-01-17 | 2001-07-19 | Oki Electric Ind Co Ltd | Semiconductor device and manufacturing method of semiconductor device |
| KR20010109677A (en) * | 2000-06-01 | 2001-12-12 | 윤종용 | Fabrication method of MOS transistor in semiconductor device and MOS transistor fabricated thereby |
| KR100363097B1 (en) * | 2001-01-06 | 2002-12-05 | 삼성전자 주식회사 | Contact structure reduced contact resistance between substrate and contact pad |
-
2001
- 2001-12-31 KR KR10-2001-0089165A patent/KR100506055B1/en not_active IP Right Cessation
-
2002
- 2002-12-27 US US10/329,680 patent/US6838326B2/en not_active Expired - Fee Related
- 2002-12-27 JP JP2002381110A patent/JP4134720B2/en not_active Expired - Fee Related
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2004
- 2004-04-01 US US10/814,289 patent/US6844602B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101044380B1 (en) * | 2004-01-08 | 2011-06-29 | 매그나칩 반도체 유한회사 | Method of manufacturing semiconductor device |
| KR101068136B1 (en) * | 2004-04-02 | 2011-09-27 | 매그나칩 반도체 유한회사 | method for forming a gate electrode of semiconductor device |
| KR100670925B1 (en) * | 2005-08-01 | 2007-01-19 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
| CN109728015A (en) * | 2017-10-30 | 2019-05-07 | 三星电子株式会社 | The imaging sensor of settling time with reduction |
| CN109728015B (en) * | 2017-10-30 | 2023-10-24 | 三星电子株式会社 | Image sensor with reduced setup time |
Also Published As
| Publication number | Publication date |
|---|---|
| US20030122202A1 (en) | 2003-07-03 |
| US20040183137A1 (en) | 2004-09-23 |
| JP2003289143A (en) | 2003-10-10 |
| KR100506055B1 (en) | 2005-08-05 |
| JP4134720B2 (en) | 2008-08-20 |
| US6838326B2 (en) | 2005-01-04 |
| US6844602B2 (en) | 2005-01-18 |
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