A7 B7 ^11240 五、發明説明（ (―)技術領域A7 B7 ^ 11240 V. Description of the invention ((―) Technical field
Hi, nn In —^ϋ HI HI I ^ .n nn In Kn In ^ (請先閲讀背面之注意事項再填寫本頁) 本發明所揭露的是關於積體電路（Integrated Circuit ; 1C)之電性活動區 (Active Area)的製造方法（Manufacturing Method)。 „ (二)發明背景 到目前爲止，在全世界的積體電路製造領域，例如金氧半場效電晶體（Metal· Oxide Semiconductor Field Effect Transistor ; MOSFET)積體電路及雙載子電晶體 (Bipolar)積體電路，大部份都仍然使用所謂的局部矽氧化隔離技術（LOCal I Oxidation of Silicon Isolation ; LOCOS Isolation)來形成隔離積體電路電性元件所; 需的厚氧化層，稱爲場氧化層（Field Oxide)。E. Kooi等人在美國專利第丨 3970486號便詳細的描述了這種【局部矽氧化隔離技術】，其製程方法如下列。首! 先，在P型矽半導體晶圓（Silicon Semiconductor Wafer)表面形成二氧化矽墊層_ (Pad Oxide)與氮化矽層（Silicon Nitride)，接著，利用傳統的微影技術和鈾刻 技術制定所述【二氧化矽墊層】與【氮化矽層】的圖案，去除光阻後，將所述 【P型矽半導體晶圓】置於高溫之氧氣環境中，以所述【氮化矽層】圖案作爲氧 化保護罩（Oxidation Mask)來保護電性活動區（Active Area)免於受到氧化，然 後，利用熱氧化技術在P型矽半導體基板上成長所述【場氧化層】，其厚度介於 3000埃到6000埃之間。 通常，所述傳統【局部矽氧化隔離技術】在形成【場氧化層】之前’都需 要進行P型雜質植入步驟，例如，將硼離子(B11)植入所述【場氧化層】下方 之所述【P型矽半導體晶圓】，以形成淡攙雜區域（Lightly DoPed Region)，以防止在所述【場氧化層】底下之【P型矽半導體晶圓】太早形成反 轉層（Inversion Layer)，如此，可提高所述【場氧化層】之電性隔離效果。一 般而言，在形成【場氧化層】之前進行硼離子（B11)植入時，其離子佈値劑量 (Implantation Dose)介於1E13到5E13原子/平方公分之間，離子佈値能量 (Implantation Energy)介於 25 到 50 Kev 之間。 經濟部中央榡準局員工消費合作社印製 問題是，在高溫之氧氣環境中成長所述【場氧化層】時’所述p型雜質會 向旁側擴散（Lateral Diffusion)侵蝕至所述【氮化矽層】圖案下方之【電性活動 區】，造成【電性活動區】面積減小，無法進行金氧半場效電晶體積體電路或雙 載子電晶體積體電路的製作。 爲了解決所述『旁側擴散』的問題，形成【電性活動區】之傳統製程是藉 著在所述【二氧化矽墊層】與【氮化矽層】圖案的兩側形成『介電層側壁子』 (Dielectric Space)，再進行P型雜質植入，茲圖1到圖8說明如下。…… 本紙張尺度適用中國國家標準（CNS ) A4規格（210'乂297公嫠） 311240 A7 B7 五、發明説明（） 首先，在晶格方位（100)的p型矽半導體晶圓2上形成一層二氧化矽墊層4 (Pad Oxide)，其厚度介於1〇〇到500埃之間，所述【二氧化矽墊層4】通常是 熱氧化（Thermal Oxidized)所述『P型矽半導體晶圓2』而形成，其氧化溫度約 1000°C。然後，形成一層【氮化砍層6】，所述【氮化砂層6】是利用低壓化學氣 相沉積法（Low Pressure Chemical Vapor Deposition ; LPCVD )形成，其反應溫度約 760°C，反應氣體是SiH2Cl2和NH3，反應壓力約350 mili-torr，其厚度介於1000 到2000埃之間，如圖1所示。 接著，利用光學微影技術（Optical Lithography)形成光阻圖案8，如圖2所 示，再利用電獎餓刻技術蝕去所述【二氧化砂墊層4】與【氮化矽層6】，如圖3 所示，最後利用氧氣電漿和硫酸去除所述『光阻圖案8』，如圖4所示。所述【電 漿鈾刻】是利用磁場增強式活性離子式電漿触刻（Magnetic Enhanced Reactive Ion aching ; MERIE)或傳統的活性離子式電漿蝕刻技術（Reactive Ion Etching ; RIE) 來完成，其反應氣體一般是CF4和CHF3等氟類氣體。 接著，沉積一層介電層10，如圖5所示，並對所述【介電層10】進行單向 性的回蝕刻（AnisotropicalEtchback)，以在所述【二氧化矽墊層4A】與【氮化矽 層6A】圖案之兩側產生【介電層側壁子10A】，如圖6所示。所述【介電層 10】通常是利用低壓化學氣相沉積法形成之無攙雜的二氧化砂（Undoped Silicon Dioxide)，其反應氣體是四已基砂酸鹽（TetraEthOxySilane ; TEOS)，其反應溫度 約720 °C，反應壓力則介於200到300 mili-torr之間，其厚度則介於800到2500埃 之間。所述『單向性的回蝕刻』也是利用磁場增強式活性離子式電漿餓刻（Magnetic Enhanced Reactive Ion Etching ; MERIE)或傳統的活性離子式電漿蝕刻技術 (Reactive Ion Etching ; RIE)來完成，其反應氣體一般也是CF4和CHF3等氟類氣 體。 ... 然後’以所述【介電層側壁子10A】作爲離子植入保護罩（Ionlmolantation Mask) ’進行P型雜質植入步驟丨丨，將硼離子（B11)植入所述【p型矽半導體晶 圓2】’以形成p-淡攙雜區域12 (Lightly Doped Region)，如圖7所示。所述 經濟部中央樣準局貝工消費合作社印製 |二!--I —1 — —^1 » ...... II— 1 1^1 m In，一SJ (請先閱讀背面之注意事項再填寫本頁) 『P_淡攙雜區域』可以防止在所述【場氧化層】底下之所述【P型矽半導體晶圓 2】太早形成反^層（Inversi〇n Layer)，如此，可提高所述【場氧化層】之電性隔離 效果。一般而言’所述P型雜質植入，其離子佈値劑量（Implantation Dose)介於 1E13到5E13原子/平方公分之間，離子佈値能量（Imp丨Energy )介於25到 50 Kev之間。 本纸張尺度適用中國國家梂準（CNS > M規格（2丨〇><297公釐） ^11240 A7 經濟部中央標準局貝工消費合作社印製 B7 五、發明説明（） 然後，將所述【P型矽半導體晶圓2】置放在富含氧氣的高溫環境中，以所述 【氮化矽層6A】圖案作爲氧化保護罩（Oxidation Mask)來形成場氧化層12 (Field Oxide )，其氧化溫度介於950°C到1 l〇〇°C之間，氧化時間介於150到450 分鐘之間，長成之『場氧化層16』厚度介於3000到6000埃之間，最後，利用熱憐 酸溶液（Hot Phosphorus Acid)去除所述【氮化矽層6A】圖案，再利用稀釋氫氟酸 溶液（Diluted Hydrofluoric Acid )去除所述【二氧化矽墊層4A】，『電性活動區 18』、『場氧化層16』和『P-淡攙雜區域14』於焉完成，如圖8所示。 由以上說明可知，傳統製程形成『電性活動區』的『介電層側壁子』 (Dielectric Space )之詳細步驟如下列： 【一】化學淸洗·， 【二】以低壓化學氣相沉積法（Low Pressure Chemical Vapor Deposition ; LPCVD) 形成之介電層（Dielectric); 【三】以粒子缺陷檢查儀（Particle Defect Inspector)掃猫所述介電層表面之粒子分 佈情況； 【四】利用電漿蝕刻技術對所述介電層進行垂直單向性的回蝕刻（Anisotropically Etchback)以形成『介電層側壁子』（Dielectric Spacer)。 問題是，完成上述傳統製程步驟之八吋晶圓機器設備均相當昂貴，每台機器設 備從新臺幣3000萬元到6000萬都有。以世界先進積體電路公司（Vanguard International Semiconductor)之0.5微米一仟六佰萬位元堆叠式動態隨機存取記憶體 (16MB Stack DRAM)爲例子，步驟【一】之化學淸洗是使用過氧化氫、硫酸和稀 釋氫氟酸等化學品，步驟【二】是利用低壓化學氣相沉積法（Low Pressure Chemical Vapor Deposition ; LPCVD)形成一層二氧化砂層（Silicon Dixoide)，步驟【三】是 利用『粒子缺'陷檢查儀』來檢查所沉積之介電層是否有反應不良而產生粒子，步驟 【四】是以CF4、CHF3和Ar等含氟氣體作爲反應氣體，再利用磁場增強式活性離 子式電漿餓刻技術（Magnetic Enhanced Reactive Ion Etching ; MERIE)對『二氧化砂 層』進行垂直單向性的回蝕刻以形成『二氧化矽側壁子』。表一詳列了上述傳統製 程步驟之每片製造成本。後面將會分析，因而大幅增加積體電路之製造成本，另一 方面，製程步驟太多亦導至積體電路的良率下降。 本紙张尺度適用中國國家標準（CNS ) A4規格（210 X297公釐） n HI I n^— nn UK * —^n '一-SJ (請先閲讀背面之注意事項再填寫本I) 經濟部中央標準局員工消費合作社印製 五、發明説明（） 【表一】.傳統『介電層側壁子』之八吋晶圓每片製造成本· (單位：新臺幣元） _ 化學淸洗 二氧化矽層沉積 粒子缺陷檢查 電漿蝕刻 固定成本 17.9 93.1 132.7 67.7 變動成本 1.5 12.4 19.74 9.9 間接材料成本 23.2 12.9 0 32.7 小計 42.6 118.4 152.4 110.3 每片總成本 423.7 本發明提出了一種利用自旋塗佈式玻璃薄膜側壁子（SOG Spacer)形成『電性 活動區』的方法，此方法簡易，其製造成本僅爲傳統『介電層側壁子』之28%，如 表二所列，故適合積體電路的大量生產。 — 【表二】.本發明之『自旋塗佈式玻璃薄膜側壁子』之八吋晶圓每片製造成本. (單位：新臺幣元） 白旋塗佈式玻璃薄膜塗佈 自旋塗佈式玻璃薄膜固化 固定成本 32 54 變動成本 2.2 5.9 間接材料成本 22.4 3 小計 56.6 62.9 每片總成本 119.5 (三)發明的簡要說明 本發明的主要目的是提供一種形成積體電路（Integrated Circuit ; 1C )『電性活 動區』（Active Area )的方法。 本發明之主要製程如下列。首先，在矽半導體晶圓上形成一層二氧化矽墊層 (Pad Oxide)和【氮化砍層】。接著，利用光學微影技術（Optical Lithography)形 成光阻圖案，再所述『光阻圖案』作爲蝕刻保護罩（Etch Mask)，利用電漿蝕刻技 柿Ϊ蝕去所述【二氧化矽墊層】與【氮化矽層】以形成圖案，再利用氧氣電漿和硫酸 去除所述『光阻圖案』。接著，形成一層未經固化處理（Uncured)的自旋塗佈式玻 璃膜（Spin-On-Glass ; SOG)，所述未經固化處理的『自旋塗佈式玻璃膜』將分佈 於所述【二氧化矽墊層】與【氮化矽層】圖案的側面（Sidewall)、上表面（Top Surface)。然後，對『自旋塗佈式玻璃膜』進行固化處理（Cure)，並旋即進行P 型雜質植入步驟以形成P-淡攙雜區域（Lightly Doped Region )。 本紙張尺度適用中國國家橾準（CNS ) A4规格（210X297公釐） flvn I tAH ^^^^1 n^i m^i K I I I tn *一 (請先閲讀背面之注意事項再填商本頁) Μ Β7 ^11240 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 最後，將所述【矽半導體晶圓】置放在富含氧氣的高溫環境中’以所述【氮化 货層】圖案作爲氧化保護罩（Oxidation Mask)來形成場氧化層（HeW Oxide)，然 溪’利用熱憐酸溶液（Hot Phosphorus Acid)去除所述【氮化砂層】圖案’利用稀釋 氫氟酸溶液（Diluted Hydrofluoric Acid)去除所述【二氧化砂墊層】圖案，『電性活 動區』、『場氧化層』和『P-淡攙雜區域』於焉完成。 (四）圖示的簡要說明 圖1到圖8是先前技藝（Prior Art)之製程橫截面示意圖； 圖9到15是本發明之實施例的製程橫截面示意圖。 (五)發明的詳細說明 參考圖9。首先，在電阻値約2.5 ohm-cm、晶格方位（100)的P型砂半導體 晶圓30上形成一層二氧化矽墊層32 (Pad Oxide)，其厚度介於100到500埃之 間，所述【二氧化矽墊層32】通常是熱氧化（Thermal Oxidized)所述『P型砂半導 體晶圓30』而形成，其氧化溫度約1000°C。然後，形成一層【氮化矽層34】， 所述【氮化矽層34】是利用低壓化學氣相沉積法（Low Pressure Chemical Vapor Deposition ; LPCVD)形成，其反應溫度約760°C，反應氣體是SiH2Cl2和NH3，反 應壓力約350 mili-torr，其厚度介於1000到2000埃之間，如圖9所示。 經濟部中央標準局員工消費合作社印袋 接著，利用光學微影技術（OpticalLithography)形成光阻圖案36，如圖10所 示，再利用電漿蝕刻技術蝕去所述【二氧化矽墊層32】與【氮化矽層34】，如圖 11所示，使成爲【二氧化矽墊層32A】與【氮化砂層34A】圖案，最後利用氧氣 電漿（OxygenPlasma)和硫酸溶液去除所述『光阻圖案36』，如圖12所示。所述 對所^【二氧化矽墊層32】與【氮化矽層34】之【電漿蝕刻】是利用磁場增強式 活性離子式電槳餓刻（Magnetic Enhanced Reactive Ion Etching ; MERIE )或電子迴旋 共振電漿餽刻（Electron Cyclotron Resonance ; ECR)或傳統的活性離子式電漿餓刻 技術（Reactive Ion Etching ; Rffi)，在次微米積體電路技術領域，一般是利用【磁 場增強式活性離子式電漿蝕刻】來完成，其反應氣體是CF4和CHF3等氟類氣體。 接著，形成一層未經固化處理（Uncured)的自旋塗佈式玻璃膜40 (Spin-On-Glass ; SOG) ， 所述未經固化處理的 【自旋塗佈式玻璃膜 40】 分佈於所述 【二氧化 矽墊層32A】與【氮化矽層34A】圖案的側面（Sidewall)和上表面（Top Surface)，如圖13所示。。所述【自旋塗佈式玻璃膜40】的材質以含有Si-0鍵 結的Siloxane type較理想，其被半導體工業界廣汎應用的商業化產品有由美國Allied Chemical公司所生產的ACCUGLASS自旋塗佈式玻璃膜。. ' 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） SH240 五、發明説明（） 接著，對所述未經固化處理的【自旋塗佈式玻璃膜40】進行低溫烘烤處理 (.Low Temperature Baking)，所述【低溫供烤處理】之供烤溫度介於.100°C到300 °C之間，烘烤時間介於〇.5分鐘到2分鐘之間。然後，進行高溫固化處理（High TempbratureCuring)，所述『高溫固化處理』之固化溫度介於400°C到425°C之 間，固化時間介於30分鐘到60分鐘之間。所述【自旋塗佈式玻璃膜40】在所述 【二氧化矽墊層32A】與【氮化矽層34A】圖案的側面（Sidewall)形成具有內凹 形狀的自旋塗佈式玻璃膜側壁子40A ( Spacer with Concave Profile )，所述呈內凹形 狀的側壁子40A在靠近所述【二氧化矽墊層32A】與【氮化矽層34A】圖案的厚 度較厚，在遠離所述【二氧化矽墊層32】與【氮化矽層34】圖案的位置之厚度則 快速變薄。 然後，以所述【自旋塗佈式玻璃膜側壁子40A】作爲離子植入保護罩（Ion Imolantation Mask)，進行P型雜質植入步驟41，將硼離子（Bll )植入所述【P 型石夕半導體晶圓30】，以形成P-淡攙雜區域42 (Lightly Doped Region)，如圖 14所示。所述『P_淡攙雜區域42』可以防止在【場氧化層】底下之所述【P型矽 半導體晶圓30】太早形成反轉層（InversionLayer)，如此，可提高【場氧化層】之 電性隔離效果。一般而言，所述P型雜質植入，其離子佈値劑量（Implantation Dose)介於1E13到5E13原子/平方公分之間，離子佈値能量（Implantation Energy)介於25到50 Kev之間。當然，在進行所述【P型雜質植入41】之前，也 可以利用電漿蝕刻技術對所述『自旋塗佈式薄膜40』進行垂直單向性的回蝕刻 (AnisotropicallyEtchback)，以去除一部份的所述『二氧化砂墊層32A』和『氮化 矽層34A』圖案的上表面（Top Surface)之所述『自旋塗佈式薄膜』。 然後，將所述【P型矽半導體晶圓30】置放在富含氧氣的高溫環境中，以所述 【氮化矽層.34A】圖案作爲氧化保護罩（Oxidation Mask)來形成場氧化層46 (Field Oxide )，其氧化溫度介於950°C到1100°C之間，氧化時間介於150到450 分鐘之間，長成之『場氧化層46』厚度介於3000到6000埃之間，最後，利用熱 磷酸溶液（Hot Phosphorus Acid)去除所述【氮化矽層34A】圖案，再利用稀釋氫氟 酸溶液（Diluted Hydrofluoric Acid)去除所述【二氧化矽墊層32A】，『電性活動區 48』、『場氧化層46』和『P-淡攙雜區域44』於焉完成，如圖15所示。 經濟部中央標準局貝工消費合作社印裝 (請先閱讀背面之注意事項再填寫本頁) 【表一】所列，傳統『介電層側壁子』之八吋晶圓每片製造成本是新臺幣 423.7元’而如【表二】所列，本發明之『自旋塗佈式玻璃薄膜側壁子』之八吋晶圓 每片製造成本則是新臺幣119.5元，因此，本發明之方法節省每片製造成本約新臺 幣304元。以一仟六佰萬位元堆疊式動態隨機存取記憶體製程（16MB Stack DRAM)爲例子，其生產週期約3個月（Cycle Time)，若工廠之月產能是30000 片晶圓，則其在製品（Wafer In Process ; WIP)大約有3X30000片晶圓= 90000片 晶圓’ 一年處理的晶圓約有12X90000片晶圓=1080000片晶圓，故每_可節省新 臺幣1080000X304 = 328320000元，亦即，每年大約可節省新臺幣三億三仟萬元。 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐）Hi, nn In — ^ ϋ HI HI I ^ .n nn In Kn In ^ (please read the precautions on the back before filling out this page) The invention discloses the electrical properties of integrated circuits (Integrated Circuit; 1C) Manufacturing Method of Active Area. "(2) Background of the invention So far, in the field of integrated circuit manufacturing worldwide, such as metal oxide semiconductor field effect transistor (MOSFET) integrated circuits and bipolar transistors (Bipolar) Most of the integrated circuits still use the so-called local silicon oxide isolation technology (LOCal I Oxidation of Silicon Isolation; LOCOS Isolation) to form the electrical components of the isolated integrated circuit; the thick oxide layer required, called the field oxide layer (Field Oxide). E. Kooi et al. Described this [local silicon oxide isolation technology] in detail in U.S. Patent No. 3970486, and its manufacturing process is as follows. First! First, in the P-type silicon semiconductor wafer ( Silicon Semiconductor Wafer) is formed on the surface of the silicon dioxide pad layer _ (Pad Oxide) and silicon nitride layer (Silicon Nitride), then, using traditional lithography technology and uranium engraving technology to develop the [silicon dioxide pad layer] and [ After removing the photoresist pattern of the silicon nitride layer, place the [P-type silicon semiconductor wafer] in a high temperature oxygen environment, and use the pattern of the silicon nitride layer as oxidation protection (Oxidation Mask) to protect the electrical active area from being oxidized, and then use thermal oxidation technology to grow the [field oxide layer] on the P-type silicon semiconductor substrate with a thickness ranging from 3000 Angstroms to 6000 Angstroms Generally, the traditional [local silicon oxide isolation technology] requires a P-type impurity implantation step before forming the [field oxide layer], for example, implanting boron ions (B11) into the [field oxide layer] [P-type silicon semiconductor wafer] mentioned below to form a lightly doped region (Lightly DoPed Region) to prevent the [P-type silicon semiconductor wafer] under the [field oxide layer] from forming an inversion too early Layer (Inversion Layer), in this way, the electrical isolation effect of the [field oxide layer] can be improved. Generally speaking, when boron ions (B11) are implanted before the formation of the [field oxide layer], the ion distribution dose (Implantation Dose) is between 1E13 to 5E13 atoms per square centimeter, and the ion implantation energy is between 25 to 50 Kev. The printing problem of the Employee Consumer Cooperative of the Central Bureau of Economics of the Ministry of Economic Affairs is that the high temperature When the [field oxide layer] is grown in a gaseous environment, the p-type impurities will diffuse laterally (Lateral Diffusion) and erode to the [electrically active region] under the [silicon nitride layer] pattern, resulting in Sexual Activity Area] The area is reduced, making it impossible to fabricate a metal-oxygen half-field transistor volume circuit or a double carrier transistor volume circuit. In order to solve the "side diffusion" problem, the traditional process of forming the [electrically active area] is to form a "dielectric" on both sides of the [silicon dioxide pad layer] and [silicon nitride layer] patterns "Dielectric Space", and then implantation of P-type impurities, as shown in Figures 1 to 8 below. …… This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 'x 297 gong) 311240 A7 B7 V. Description of invention () First, it is formed on a p-type silicon semiconductor wafer 2 with a lattice orientation (100) A silicon dioxide pad layer 4 (Pad Oxide), the thickness of which is between 100 and 500 angstroms, the [silicon dioxide pad layer 4] is usually thermal oxidation (Thermal Oxidized) of the "P-type silicon semiconductor Wafer 2 is formed and its oxidation temperature is about 1000 ° C. Then, a layer of [nitride cutting layer 6] is formed, the [nitriding sand layer 6] is formed by low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition; LPCVD), the reaction temperature is about 760 ° C, and the reaction gas is SiH2Cl2 and NH3, the reaction pressure is about 350 mili-torr, and its thickness is between 1000 and 2000 Angstroms, as shown in Figure 1. Next, use optical lithography (Optical Lithography) to form a photoresist pattern 8, as shown in FIG. 2, and then use electrical award etching technology to etch away the [Sand dioxide pad layer 4] and [Silicon nitride layer 6] As shown in FIG. 3, finally use oxygen plasma and sulfuric acid to remove the "photoresist pattern 8", as shown in FIG. 4. The [plasma uranium engraving] is accomplished by using magnetic field enhanced active ion plasma etching (MERIE) or traditional active ion plasma etching technology (Reactive Ion Etching; RIE), which The reaction gas is generally fluorine gas such as CF4 and CHF3. Next, a dielectric layer 10 is deposited, as shown in FIG. 5, and the [dielectric layer 10] is anisotropically etched back (AnisotropicalEtchback), so that the [silicon dioxide pad layer 4A] and [ [Silicon Nitride Layer 6A] [Dielectric Side Wall Sub 10A] is generated on both sides of the pattern, as shown in FIG. 6. The [dielectric layer 10] is usually undoped silicon dioxide (Undoped Silicon Dioxide) formed by low-pressure chemical vapor deposition, the reaction gas is TetraEthOxySilane (TEOS), and the reaction temperature At about 720 ° C, the reaction pressure is between 200 and 300 mili-torr, and its thickness is between 800 and 2500 Angstroms. The "unidirectional etch back" is also completed by using Magnetic Enhanced Reactive Ion Etching (MERIE) or traditional reactive ion plasma etching technology (Reactive Ion Etching; RIE) , The reaction gas is generally fluorine gas such as CF4 and CHF3. ... Then 'use the [dielectric layer sidewall 10A] as an ion implantation protection mask (Ionlmolantation Mask)' to perform a P-type impurity implantation step, and implant boron ions (B11) into the [p-type Silicon semiconductor wafer 2 'to form a p-light doped region 12 (Lightly Doped Region), as shown in FIG. 7. Printed by the Beige Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs | II! --I —1 — — ^ 1 »...... II— 1 1 ^ 1 m In, an SJ (please read the back page first Note: Please fill out this page again. "P_Light Doped Area" can prevent the [P-type silicon semiconductor wafer 2] under the [field oxide layer] from forming an inverse layer (Inversion Layer) too early, In this way, the electrical isolation effect of the [field oxide layer] can be improved. Generally speaking, for the P-type impurity implantation, the ion implantation dose is between 1E13 and 5E13 atoms / cm 2, and the ion implantation energy is between 25 and 50 Kev . This paper scale is applicable to the Chinese National Standard (CNS > M specifications (2 丨 〇 > < 297 mm) ^ 11240 A7 Printed by the Ministry of Economic Affairs, Central Standards Bureau, Beigong Consumer Cooperative B7. Invention description () Then, Place the [P-type silicon semiconductor wafer 2] in a high-temperature environment rich in oxygen, and use the [Silicon Nitride Layer 6A] pattern as an oxidation protection mask to form a field oxide layer 12 (Field Oxide), the oxidation temperature is between 950 ° C and 1100 ° C, the oxidation time is between 150 and 450 minutes, and the thickness of the grown "field oxide layer 16" is between 3000 and 6000 Angstroms Finally, use hot Phosphorus Acid to remove the [Silicon Nitride Layer 6A] pattern, and then use a diluted hydrofluoric acid solution (Diluted Hydrofluoric Acid) to remove the [Silicon Dioxide Pad 4A], " The electrical active area 18 "," field oxide layer 16 "and" P-light doped area 14 "were completed in Yan, as shown in Figure 8. As can be seen from the above description, the traditional process forms the" electrical active area " The detailed steps of "Dielectric Space" are as follows: [一] Chemistry Washing, [2] Dielectric layer formed by Low Pressure Chemical Vapor Deposition (LPCVD); [3] Scanning the dielectric with a Particle Defect Inspector The distribution of particles on the surface of the layer; [4] Using plasma etching technology to vertically etch the dielectric layer (Anisotropically Etchback) to form a "dielectric spacer" (Dielectric Spacer). The problem is, The 8-inch wafer machinery and equipment that complete the above traditional process steps are quite expensive, and each machine equipment ranges from NT $ 30 million to 60 million. Take the world's advanced integrated circuit company (Vanguard International Semiconductor) 's 0.5 micron 1.6 thousand One million bit stacked dynamic random access memory (16MB Stack DRAM) is used as an example. The chemical washing in step [1] uses chemicals such as hydrogen peroxide, sulfuric acid, and diluted hydrofluoric acid. The step [2] uses Low Pressure Chemical Vapor Deposition (LPCVD) to form a layer of silicon dioxide (Silicon Dixoide), steps [3] Use the "particle defect trap tester" to check whether the deposited dielectric layer is poorly reacted to generate particles. Step [4] uses CF4, CHF3 and Ar and other fluorine-containing gases as reactive gases, and then uses magnetic field to enhance the activity The ion enhanced plasma active etching technology (Magnetic Enhanced Reactive Ion Etching; MERIE) performs vertical unidirectional etch back on the "sand dioxide layer" to form the "silicon dioxide sidewalls". Table 1 details the manufacturing cost of each piece of the above traditional process steps. It will be analyzed later, which greatly increases the manufacturing cost of the integrated circuit. On the other hand, too many process steps also lead to a decrease in the yield of the integrated circuit. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X297 mm) n HI I n ^ — nn UK * — ^ n '一 -SJ (please read the precautions on the back before filling in this I) Ministry of Economic Affairs Printed by the Bureau of Standards and Staff Consumer Cooperative V. Description of the invention () [Table 1]. Manufacturing cost per wafer of 8-inch wafers in traditional "dielectric side walls" (Unit: NTD) _ Chemical Washing Dioxide Silicon layer deposition particle defect inspection plasma etching fixed cost 17.9 93.1 132.7 67.7 variable cost 1.5 12.4 19.74 9.9 indirect material cost 23.2 12.9 0 32.7 subtotal 42.6 118.4 152.4 110.3 total cost per piece 423.7 The present invention proposes a spin-coated glass The method of forming the "electrically active area" by the thin film sidewall (SOG Spacer) is simple. Its manufacturing cost is only 28% of the traditional "dielectric sidewall", as listed in Table 2, so it is suitable for integrated circuits. Mass production. — 【Table 2】. The manufacturing cost of each piece of 8-inch wafer of "spin-coated glass film sidewall" of the present invention. (Unit: NTD) White spin-coated glass film spin coating Fixed cost of cloth glass film curing 32 54 Variable cost 2.2 5.9 Indirect material cost 22.4 3 Subtotal 56.6 62.9 Total cost per piece 119.5 (3) Brief description of the invention The main purpose of the present invention is to provide an integrated circuit (Integrated Circuit; 1C ) "Electrical Active Area" (Active Area) method. The main process of the present invention is as follows. First, form a pad layer of silicon dioxide (Pad Oxide) and [nitride cutting layer] on the silicon semiconductor wafer. Next, use optical lithography (Optical Lithography) to form a photoresist pattern, and then use the "photoresist pattern" as an etch protection mask (Etch Mask), using plasma etching technology to remove the [silicon dioxide pad layer ] And [silicon nitride layer] to form a pattern, and then use oxygen plasma and sulfuric acid to remove the "photoresist pattern". Next, a layer of uncured spin-on-glass (Spin-On-Glass; SOG) is formed, and the uncured "spin-on-glass" film will be distributed in the [Silicon dioxide pad layer] and [Silicon nitride layer] patterns on the side (Sidewall) and top surface (Top Surface). Then, the "spin-coated glass film" is cured, and immediately a P-type impurity implantation step is performed to form a P-lightly doped region (Lightly Doped Region). The paper size is applicable to China National Standard (CNS) A4 (210X297mm) flvn I tAH ^^^^ 1 n ^ im ^ i KIII tn * 1 (please read the precautions on the back and fill in this page) Μ Β7 ^ 11240 V. Description of invention () (please read the notes on the back before filling in this page) Finally, place the [Silicon Semiconductor Wafer] in a high temperature environment rich in oxygen ' Cargo layer] The pattern is used as an Oxidation Mask to form a field oxide layer (HeW Oxide). Ranxi 'removes the [nitride sand layer] pattern using a hot phosphoric acid solution (Hot Phosphorus Acid). The pattern utilizes diluted hydrofluoric acid. The solution (Diluted Hydrofluoric Acid) removes the [Sand dioxide cushion] pattern, and the "electrically active area", "field oxide layer" and "P-light doped area" are completed. (4) Brief description of the drawings Figures 1 to 8 are schematic cross-sectional views of the prior art (Prior Art); Figures 9 to 15 are schematic cross-sectional views of the process according to an embodiment of the present invention. (5) Detailed description of the invention Refer to FIG. 9. First, a silicon dioxide pad layer 32 (Pad Oxide) with a thickness between 100 and 500 Angstroms is formed on a P-type sand semiconductor wafer 30 with a resistance value of about 2.5 ohm-cm and a lattice orientation (100) The [silicon dioxide pad layer 32] is usually formed by thermal oxidation (Thermal Oxidized) of the "P-type sand semiconductor wafer 30", and its oxidation temperature is about 1000 ° C. Then, a layer of [silicon nitride layer 34] is formed, the [silicon nitride layer 34] is formed by low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition; LPCVD), the reaction temperature is about 760 ° C, and the reaction gas It is SiH2Cl2 and NH3, the reaction pressure is about 350 mili-torr, and its thickness is between 1000 and 2000 Angstroms, as shown in Figure 9. The printed bag of the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. Then, optical photolithography (OpticalLithography) was used to form the photoresist pattern 36, as shown in FIG. With [Silicon Nitride Layer 34], as shown in FIG. 11, make the pattern of [Silicon Dioxide Pad 32A] and [Nitride Sand Layer 34A], and finally remove the "light The resist pattern 36 "is shown in FIG. The [plasma etching] of the [silicon dioxide pad layer 32] and the [silicon nitride layer 34] is to use magnetic field enhanced active ion electroplating (Magnetic Enhanced Reactive Ion Etching; MERIE) or electronic Cyclotron resonance plasma feeding (Electron Cyclotron Resonance; ECR) or traditional reactive ion plasma etching (Reactive Ion Etching; Rffi), in the field of submicron integrated circuit technology, generally use [magnetic field enhanced active ion Type plasma etching] to complete, the reaction gas is fluorine gas such as CF4 and CHF3. Next, an uncured spin-on-glass (SOG) glass film 40 (Spin-On-Glass; SOG) is formed, and the uncured [spin-on-glass glass film 40] is distributed in all The side wall (Sidewall) and top surface (Top Surface) of the pattern of the [silicon dioxide pad layer 32A] and the [silicon nitride layer 34A] are described, as shown in FIG. 13. . The material of the [spin-coated glass film 40] is preferably a Siloxane type containing Si-0 bonds. Commercialized products widely used in the semiconductor industry include ACCUGLASS manufactured by Allied Chemical Company of the United States. Spin coating glass film. 'This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) SH240 V. Description of the invention () Next, the non-cured [spin-coated glass film 40] is baked at low temperature (Low Temperature Baking), said [low temperature baking treatment] the baking temperature is between .100 ° C and 300 ° C, and the baking time is between 0.5 minutes and 2 minutes. Then, a high temperature curing treatment (High TempbratureCuring) is performed. The curing temperature of the "high temperature curing treatment" is between 400 ° C and 425 ° C, and the curing time is between 30 minutes and 60 minutes. The [spin-coated glass film 40] forms a spin-coated glass film having a concave shape on the side wall (Sidewall) of the patterns of the [silicon dioxide pad layer 32A] and the [silicon nitride layer 34A] Side wall sub 40A (Spacer with Concave Profile), the concave side wall sub 40A is thicker near the [silicon dioxide pad layer 32A] and [silicon nitride layer 34A] patterns, and farther away from the The thickness of the positions of the [silicon dioxide pad layer 32] and the [silicon nitride layer 34] pattern becomes thinner rapidly. Then, using the [spin-coated glass film side wall 40A] as an ion implantation protection mask (Ion Imolantation Mask), perform a P-type impurity implantation step 41, and implant boron ions (Bll) into the [P Type Shixi Semiconductor Wafer 30] to form a P-lightly doped region 42 (Lightly Doped Region), as shown in FIG. 14. The "P_light doped region 42" can prevent the [P-type silicon semiconductor wafer 30] under the [field oxide layer] from forming an inversion layer (InversionLayer) too early, so that the [field oxide layer] can be improved The electrical isolation effect. Generally speaking, for the P-type impurity implantation, the ion implantation dose is between 1E13 and 5E13 atoms / cm 2, and the ion implantation energy is between 25 and 50 Kev. Of course, before performing the [P-type impurity implantation 41], the plasma spin technique may also be used to perform vertical unidirectional etch back (AnisotropicallyEtchback) on the "spin-coated film 40" to remove a Part of the "spin coating film" on the top surface of the "Sand dioxide pad layer 32A" and "Silicon nitride layer 34A" patterns. Then, the [P-type silicon semiconductor wafer 30] is placed in a high-temperature environment rich in oxygen, and the [silicon nitride layer. 34A] pattern is used as an oxidation protection mask to form a field oxide layer 46 (Field Oxide), the oxidation temperature is between 950 ° C and 1100 ° C, the oxidation time is between 150 and 450 minutes, and the thickness of the grown "field oxide layer 46" is between 3000 and 6000 Angstroms Finally, use hot phosphoric acid solution (Hot Phosphorus Acid) to remove the [silicon nitride layer 34A] pattern, and then use dilute hydrofluoric acid solution (Diluted Hydrofluoric Acid) to remove the [silicon dioxide pad layer 32A], "Electric The sexual activity area 48 "," field oxide layer 46 "and" P-light doping area 44 "were completed in Yan, as shown in Figure 15. Printed by Beigong Consumer Cooperative of Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) [Table 1] listed, the traditional "dielectric layer side wall" 8-inch wafer manufacturing cost is new NTD 423.7 'and as listed in [Table 2], the manufacturing cost of the 8-inch wafer of the "spin-coated glass film sidewall" of the present invention is NTD 119.5. Therefore, the present invention The method saves about NT $ 304 per manufacturing cost. Taking the 16MB Stack DRAM (16MB Stack DRAM) as an example, its production cycle is about 3 months (Cycle Time). If the factory's monthly production capacity is 30,000 wafers, then its WIP (Wafer In Process; WIP) has about 3X30000 wafers = 90,000 wafers'. The wafers processed in a year are about 12X90000 wafers = 1.08 million wafers, so every _ can save NT $ 1080000X304 = 328320000 Yuan, that is, about NT $ 330 million can be saved each year. This paper scale is applicable to China National Standard (CNS) A4 (210X297mm)