TW209313B - - Google Patents

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TW209313B
TW209313B TW081103295A TW81103295A TW209313B TW 209313 B TW209313 B TW 209313B TW 081103295 A TW081103295 A TW 081103295A TW 81103295 A TW81103295 A TW 81103295A TW 209313 B TW209313 B TW 209313B
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Texas Instruments Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/306Lead-in-hole components, e.g. affixing or retention before soldering, spacing means

Description

Λ 6 Π 6 2〇93i3 五、發明説明(/) 本發明係有關半導體裝置,尤指一棰記德裝置之 (請先閲讀背而.之注意半項#墦1,4頁) 高密度封裝。 高速計算顯像糸統經常推動資料儲存之技術狀態。 目前,具有兩個以上之處理器之顯像糸統及電腦糸統需 要能超越傳统封裝能力之資料輸入輸出率。 為能完成高資料率,處理器與記億行列間之物理距 離必須保持最小值,以防止信號延遲。使用傳統封裝之 大型記憶行列其通過置(through-put)傑由處理器與記 億晶Η間之最長信號線決定之(假定記億晶片能以和處 理器相同之時鐘率運轉,通常為50 mhz以上)。下述之 記億行列封裝能解決有關記憶器密度與距離之問題。 經濟部屮央標準而β工消许合作杜印製 本發明係一種記億行列之高密度封裝技術。各記億 器封裝上之散熱座構造係作為散熱座、裝配工具及工具 介面。如聚亞胺之絶緣材料係放置在晶片兩侧,充作緊 密安裝之半導體裝置間之絶綠。此種封裝對於通孔安裝 及表面安裝皆能適用。多數痼裝置安裝在一起,以供測 試及預燒。安装具偽用以於測試及預燒時將裝置固定, 並作為裝置行列之散熱座。此種封裝不僅適用於記億晶 片,而且適用於任何使用相同封裝形式因素之半導體驅 動器/ S輯電路。 本發明所呈現之技術進步性及其目的,可由下列參 照附圖之較佳實施例之說明及申請專利範圍所提出之新 本紙張尺度边用中國國家標毕(CNS)T4規格(210X297公龙) 209313 A 6 Π 6 五、發明説明(y) 圖圖 角視 等前 之之 列置 行裝 。置裝 瞭裝安 明億面 於記表 臻係傑 而 12 點圖圖 特 親 裝 體 導 半 至 線 引 直 ; 垂 圖由 視的 ; 側同 圖 之不 視 置種 前 裝兩 之 裝示 合 安顯 组 面傜 孔 表3b.,通 係與件係 33a觸4 圖圖接圖 之 置 置 圖搭 C 面 裝 意之11表 之 示上部採 中 之置端係 具 置裝的置 裝 裝至寸裝 安 ; 億連尺中 定 列 記12小其 固 行·,。體線較-/ 億圖用導接有圖 .,座 .,記大作半連具視 圖熱 圖之放簧之藉得前 視散 視妥之彈座傾14之 側於 俯裝接之熱數線裝 之置 之已連座散多引封 合種 罩種裝熱有有各之 組一 掩一安散備具 。明 孔示 接示面示裝1014發 通顯 焊顯表顯未置線本 傜係 偽係 係像偽 裝引傺 56 789101 億之 2 圖圖;圖圖圖 圖圖記13圖 列 各墊 行 。接 請 先 間 ifi 背 fi 注 意 項 m 页 經濟部屮央標準局β工消费合作社印製 裝及 ο » 圖 } 視示 側所 之圖 置如 裝 ί 6 妥 1 装座 己熱 個散 兩之 示上 顯侧 係頂 3 其 圖於 而裝 -安 式有 方具 装10 安置 之 側 底 置 装15 至板 連路 上 線 i 在 裝 安 法 裝 安 面 表 0 係 置 裝 本紙5fc尺度逍用中as家標準(CHS)TM規格(210X297公;《:) 五、發明説明(>) 經濟部屮央標準而β工消#合作社印製 圖3係 裝特點。各 前侧上之塗 刨上之塗層 與相鄰裝置 係使散熱座 表面。絶線 置1 Q之搭接 。圖3a僳圖 圖3 b係 置1 D上之接 法或膠帶自 於將各 電路板15。 (未圖示) 圖4僳 附接有引線 15。電路板 些艏例中將 圖5偽 引線14、較 圖6係 放大倒視圖,以詳細顯示各裝置及其表面安 裝置1Q具有設於背側上之絶緣塗層17及設於 層18。绝緣塗層得為,例如聚亞胺。裝置背 17係用以於兩値裝置接觸時防止裝置之背面 之正.面形成短路。裝置前侧上之絶绪塗層18 16與裝置絶緣,並可作為引線14之絶緣安裝 材料層21偽放置在搭接線12、搭接線12至裝 墊13之接頭,及搭接線12至引線14之接頭上 3所示電線搭接之放大圖。 顯示引線14搭接於裝置10之另一種方式。裝 觸塊12a傜連至引線14a。此種方法為TAB方 動結合方法。 裝置表面安裝時,引線14偽藉回流焊料連至 焊料20將引線14接至電路板15上之像焊接墊 之電接頭。 安裝於通孔組合中之裝置之前視圖。裝置10 14。引線14之較小面積端11延伸貫穿電路板 上之金屬化開口延伸貫穿該電路板,而且某 開口罨鍍。 圖4所示組合之側視圖。所示焊料2 Q形成於 小引線端11及電路板15之開口等之周圍。 顯示安裝於散熱座/固定安裝具31上之装置 先 閲 in 背 而 之 注 意 項 裝 玎 線 b紙5fc尺度逍用中a B家標準(CNS)甲4規格(210x297公;it) 209抑 Λ fi Ιϊ 6 五、發明説明 (氺) 經濟部屮央楛準局ex工消费合作杜印製 之列部绨结可-在 焊得 常 其置之 6 置於背 置行端絶33則而留 ,溝ifl〇通 ,裝用^1裝係32 装將之它劑,然仍 如槽 S 度 圖為所 示口罩 各而14其接上。偽 譬。ΤΑ厚 面作時 I。 顯開掩 將中線或黏列開常 。溝如之 斷可上 上傜之自 得34引瓷溫行移通 例槽纳罩 横亦板 115其32傜 ,薄,陶高置3131實錮容掩 之罩路 板 ,罩料 配槽又由藉裝具具 個20於棰 列掩電纟基圖掩焊 名 裝之。得得在裝置 一備易此 行接於 在大。。 以部中3231留安安 之具溝。 之焊連固定放ΟΦ大 予頂31罩具停將 ,32列槽線 成。焊 ^ 固之40放 3031具掩裝擬後中 罩 一之引 形中14Μ 置分口以 列具裝該安不之當 掩毎寸之 所32線 裝部開1ί 行裝安,與31上程 接,尺Is10S 引an之到之41 之安定中32具板過 焊列種ID1置掩將31中圈32分 10定固32軍裝路燒 示行此 4 裝接及座32示·罩部 置固 \ 罩掩安電預 所列 傾焊作熱罩所掩之 裝於座掩接如在及 681S10。 八入操散掩 8 入15 將置熱接焊假接試 画有011為^ 由插合。於圖插板 能安散焊。。焊測 偽具X3寸^; 係偽組具裝偽14路 為16於入成起14之 。73213尺f814列裝安9線電 。座裝插製 一線置上圖罩如之01圖線行安將圖引近 列熱安得料在引裝列 掩例用? 引02定並οέ鄱 行散3011材合於於行 接為所约 中10固-10其 請先 閲 ifi背 而 之 注 意 項 再 1 訂 線 本紙尺度边用中BS家標準(CNS)T4規格(210X297公;《:) A β It 6 五、發明説明(<) 面施加並擠入孔41中直至形成一個新月形物(meniscus) 。再將上述總成與基板上之圖型對準並置於基板上。使 焊料回流至開口中以將引線14端部結合在電路板15上。 假如偽使用通孔黏接劑,則引線14將穿經電路板15 (未 圖示)而無需使用焊接掩罩。 圖10傜顯示圔8之散熱座31a。散熱座31a得被張開 以將各裝置之散熱座16固定於槽溝31b中。將腿部31c、 31 d張開或分開以將散熱座16插入槽溝31b中。當拉開腿 部時,腿部3 1 c、3 1 d將自” a ”移動至” b ”。於釋放腿部 31c、31d時,散熱座及附接於其上之裝置將固持定位於 腿部3 1 C與3 1 d之間。 自半導體楔具製造至將行列安裝在電路板上之行列 封裝製法係如下述。 經濟部屮央榀準劝卩工消费合作杜印製
先 間 讀 背 而 之 注 意 事 項 I 於形成含有半導體裝置之半導體模後,將如7^及 Pd之塗層障壁金屬噴鍍或沈積在半導體裝置之搭接墊上 。將含有半導體裝置之晶圓之背面塗敷以像聚亞胺之絶 綠材料,再將晶圓鋸切以使傾別装置分離。使用像黏接 劑之安装材料將引線(如圖1之引線14)安裝在裝置之 绝緣表面上。將搭接線附接於搭接墊及引線I 4。此時, .將搭接線及接頭塗佈以聚亞胺,俾遮蔽及保護該搭接線 及接頭。再將引線框修整成型,俾製成引線[4及散熱座 1 6 (圖2 )。得使用‘膠帶自動結合法(T A B ;如圖3 b所 本紙張尺度逍用中ffl國家楳毕(CNS) Τ4規格(210x297公龙) Λ (5 Η 6 209313 五、發明説明(4) 示),以取代電線結合法。 再使用如圖6所示之安裝具,以將裝置組合於多裝 置封裝中。其後,將裝置行列予以测試及預燒,以辨認 瑕疵裝置(若有時)。行列中之任何不良裝置均可自安 装具移開,而更換以另一行列之良好裝置。再將優良裝 置行列放置在電路板上,利用焊料回流法予以结合,以 將行列電連於電路板。 本發明之封装提供了行列散熱,供模組式測試及預 燒用之安裝具,裝置之修理更換容易,高密度裝置,及 將不同之半導體裝置混裝成低成本組合之能力。 (請先閲讀背而之注意帘項頁) 裝· 訂 線- 經濟部屮央標準而β工消赀合作社印奴 -8 - 本紙張尺度边用中ffl國家楳準(CNS)甲4規格(210x297公龙)

Claims (1)

  1. 2〇93i3 B7 C7 _ !)7 六、申锜專利範園 經濟部中央標準局Μ工消1f合作杜印製 M半 型 電置對 作於散 表 通 之 音固 晶自 圖 體裝成 傜接之 用 用 置 錫 @ 蓋値 定 積各列 具焊後 利 利 裝 焊^ 覆數 ·,界 値將行 裝線上 偽 係 體 將數 線 複線之 兩以件 安引板 線 線 導 於多 引 有引線及少用觸 該個路 引 引 半 -將 式 具之引以至並接 中數電 中 中 中 中來 立 各伸數.,述 ,之 其多於 其 其 其 其用 直 其延複列前偽上 ,將接 , , , ,罩 之 ,型述行將關板 裝,焊 裝。裝。裝 裝掩 列 置圃前件以接路 封時列 封上封上封。封接 行 裝定與觸用鄰電 之燒行 之板之板之佈之焊 置 體界依接,密與 項預置 項路項路項塗項一 裝 導依一之具緊成 1 及裝 1 電 1 電 1 以 1 有 體 半緣有置裝成置 第試將 第在第在第予第 ’ 導 式邊具配安持安 圍測及 圍合圍合圍胺圍時 半:體一 ,型的固線 範置, 範结範结範亞範上 度括積之板圖開互引。利裝前 利術利術利聚利線 密包値置路之移相値型專體板 專技專技專以專引 高,兩裝電應可置數圖請導路。請裝請装請偽請在 種装少髏個對個裝複之申半電座申安申安申側申加 一 封至導一成一路之應如為該熱如面如孔如兩如施. . · . . . 1 2 3 4 5 6 (請无聞請背面之注意事項再填寫本百) 木紙尺度適川t W W家標-;MCNS) τ Ί规格(210 X 297公犮) 20931^ B7 CT ___ D7 六、申請專利範® 經濟部中央標準局Μ工消費合作社印製 時體 數 半 半。熱 片 半 圖 至並接 流導 多 該 述座散 晶 自 定 述-之 回半 許 為 前熱及 蓋 値 界 前偽上 料定 容 成 與散線 覆 數 ·,之 及將關板 焊固 可 一 自之引 線 複線線 以座接路 於便 一 含 一伸一 引 有引引 ;熱鄰電 中以 含 包 含延含 式 具之痼;座散密與 其用 包 復 包緣包 立 各伸數列熱該緊成 ,作 , , .邊, 直 其延複行散由成置 装同 装。裝。裝一裝 之 -型述件之經持安 封共 封罩封座封S封 列 置圖前觸上以固線 之座 之掩之熱之之之 行 装定與接置用互引 G 項熱 項接項散項立項 。置 體界依之裝 ,相艏10 1 散 1 焊 1 之 1 對 1 框裝 導依一置體具置數 -。第與 第之第分第相第線體 半緣有配導裝裝複 型圍軍 圍中圍部圍緣圍引導 式邊具型半安路之 圖範掩 範其範一範邊範之半:體一 ,圖該之電置 定利接 利經利之利之利成度括積之板之各開醱裝 限專焊 專穿専裝專置專形密包個置路應在移積各 一請一 。請線謫封請裝請之高,兩裝電對設可個將 成申有置申引申塍申體申由種裝少體镔成附個兩以 定如,裝如個如導如導如座一封至導一型一 一少用 • « · · · ♦ 0 12 7 8 9 1 1 1 (請先閱讀背面之注意事項再填寫本百) 本紙張尺度適;丨丨t W W家標準(CNS)Τ4規格(210X297公犮) 入7 2〇9糾 B? ^ C7 _D7_ 六、申ϋ專利範園 觸件行列成對應之圖型。 13. —種用以安裝半導體裝置行列之散熱式安装具,包 括: 一 U形本賭; 一對構成為該U形本醱之一部分之睡部,此對腿部 於移動分開後僳可回復至原來位置;以及 複數値槽溝,此等槽溝係可於該等腿部移動分開時 張開以容纳半導體裝置,並可於該等腿部被容許移 動至原來位置時将半導體裝置固定於該等槽溝中者 0 ................................^ .................^..............................訂......(..........^........V.. « (請先聞讀背面之注意事項再填寫本頁) 經濟部中夬標苹局Μ工消費合作社印製 木紙張尺度適川中W W家標羋(CNS) τ Ί规格(210 X 297公兌)
TW081103295A 1991-01-14 1992-04-28 TW209313B (zh)

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EP0595021A1 (en) * 1992-10-28 1994-05-04 International Business Machines Corporation Improved lead frame package for electronic devices
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US5399902A (en) * 1993-03-04 1995-03-21 International Business Machines Corporation Semiconductor chip packaging structure including a ground plane
KR19990026510A (ko) * 1997-09-25 1999-04-15 윤종용 외장형 히트 싱크를 구비하는 수직실장형 반도체 패키지 모듈
RU2176134C2 (ru) 1998-07-02 2001-11-20 Закрытое акционерное общество "Техно-ТМ" Трехмерный электронный модуль и способ его изготовления
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