DE69202064T2 - Chipgehäuse mit Vertikalanschlüssen. - Google Patents

Chipgehäuse mit Vertikalanschlüssen.

Info

Publication number
DE69202064T2
DE69202064T2 DE69202064T DE69202064T DE69202064T2 DE 69202064 T2 DE69202064 T2 DE 69202064T2 DE 69202064 T DE69202064 T DE 69202064T DE 69202064 T DE69202064 T DE 69202064T DE 69202064 T2 DE69202064 T2 DE 69202064T2
Authority
DE
Germany
Prior art keywords
vertical connections
chip housing
chip
housing
connections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69202064T
Other languages
English (en)
Other versions
DE69202064D1 (de
Inventor
Anthony M Chiu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69202064D1 publication Critical patent/DE69202064D1/de
Publication of DE69202064T2 publication Critical patent/DE69202064T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/306Lead-in-hole components, e.g. affixing or retention before soldering, spacing means
DE69202064T 1991-01-14 1992-01-14 Chipgehäuse mit Vertikalanschlüssen. Expired - Fee Related DE69202064T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US64066791A 1991-01-14 1991-01-14

Publications (2)

Publication Number Publication Date
DE69202064D1 DE69202064D1 (de) 1995-05-24
DE69202064T2 true DE69202064T2 (de) 1995-08-17

Family

ID=24569212

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69202064T Expired - Fee Related DE69202064T2 (de) 1991-01-14 1992-01-14 Chipgehäuse mit Vertikalanschlüssen.

Country Status (5)

Country Link
EP (1) EP0495629B1 (de)
JP (1) JP3164391B2 (de)
KR (1) KR100260276B1 (de)
DE (1) DE69202064T2 (de)
TW (1) TW209313B (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0595021A1 (de) * 1992-10-28 1994-05-04 International Business Machines Corporation Verbesserte Leiterrahmenpackung für elektronische Schaltungen
KR950012925B1 (ko) * 1992-12-31 1995-10-23 삼성전자주식회사 반도체 리이드 프레임
US5399902A (en) * 1993-03-04 1995-03-21 International Business Machines Corporation Semiconductor chip packaging structure including a ground plane
KR19990026510A (ko) * 1997-09-25 1999-04-15 윤종용 외장형 히트 싱크를 구비하는 수직실장형 반도체 패키지 모듈
RU2176134C2 (ru) 1998-07-02 2001-11-20 Закрытое акционерное общество "Техно-ТМ" Трехмерный электронный модуль и способ его изготовления
US7759242B2 (en) 2007-08-22 2010-07-20 Qimonda Ag Method of fabricating an integrated circuit
RU2635852C2 (ru) 2013-01-31 2017-11-16 Пэк Тек - Пэкиджинг Текнолоджиз Гмбх Микросхемная сборка и способ изготовления микросхемной сборки

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3421133A (en) * 1967-03-02 1969-01-07 Cts Corp Mounting bracket for electrical component
DE2257888A1 (de) * 1972-11-25 1974-05-30 Licentia Gmbh Abschlussleiste fuer steckbare bauelemente
JPS6273650A (ja) * 1985-09-27 1987-04-04 Hitachi Ltd 電気部品
US4726776A (en) * 1986-06-10 1988-02-23 Amp Incorporated Socket for zig-zag inline package

Also Published As

Publication number Publication date
EP0495629B1 (de) 1995-04-19
TW209313B (de) 1993-07-11
JPH04315460A (ja) 1992-11-06
JP3164391B2 (ja) 2001-05-08
EP0495629A1 (de) 1992-07-22
DE69202064D1 (de) 1995-05-24
KR920015492A (ko) 1992-08-27
KR100260276B1 (ko) 2000-07-01

Similar Documents

Publication Publication Date Title
MX9200680A (es) Surtidor.
NO913676D0 (no) Ledekile - sammenstilling.
DE69205406T2 (de) Verbinderanordnung.
DE69206287T2 (de) Pumpenanordnung.
DE69203428T2 (de) Verbinder.
FI920336A (fi) Anordning foer bildande av en lucka i en stroem av oeverlappade produkter.
DE58900451D1 (de) Loetverbindung.
DE69205139D1 (de) Steckverbinder.
DE69203605D1 (de) Gekapselter Filz.
NL194178B (nl) Halfgeleidergeheugeneenheid.
DE69203171T2 (de) Verbinder.
DE69203253D1 (de) IC-Chipstruktur.
DE69203841D1 (de) Verbindungsvorrichtung.
DE68923778D1 (de) Halbleitermodul.
NO913199L (no) Monteringsanordning.
DE69202064D1 (de) Chipgehäuse mit Vertikalanschlüssen.
NL194628B (nl) Halfgeleiderelement.
DE68910327T2 (de) Halbleiteranordnung.
DE69014067T2 (de) Wasserstopmodul.
DE69105033T2 (de) Chipstruktur.
DE69204382T2 (de) Elektrisch verbindbares Modul.
DE69203364D1 (de) Verbinder.
DE69201785D1 (de) Verbinder.
DE69111052T2 (de) Gehäusestruktur.
ES1019648Y (es) Luminaria.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee