544835 5894twf.d〇c / ◦〇 A7 經濟部智慧財產局員工消費合作社印製 五、考务明說明（f ) 本發明是有關於一種覆晶型態的半導體封裝 特別是有關於〜種半導體封裝結構的銲墊設計。口 ，且 在半導體產業中，積體電路的生產，主要分爲三個階 『砂晶片的製造、積體電路的製作、以及積體電路的封 )aykage)等。積體電路的封裝就是完成積體電路成品 的最後步驟。封裝的目的在於提供晶片與印刷電路板 (printed clrcuit b〇ard，pCB)或其他是到元件之間的電 f生連接的媒介，以及提供保護晶片的功用。 在完成半導體製程以後，晶片係由晶圓切割形成，一 搬在晶片上會有銲墊（bonding pad)，用以作爲提供晶片 梭測的測試點，並作爲晶片與其他元件間連接的端點。爲 了連接晶片和其他元件，通常會在銲墊上形成凸塊 (bump)，作爲與導線連接的媒介。 請參照第1圖，其繪示爲習知的一種封裝結構簡示圖， 在晶片100上有銲墊丨〇2，銲墊1〇2上具有凸塊104，而 在晶片上100銲墊102以外的其他區域覆蓋有一層保護膜 106。在封裝之後必須進行最後的測試，最終測試可以銲 墊1Q2接上凸塊104之前進行，也可以在形成凸塊之 後進行。在形成凸塊104以後進行測試的話，探針1〇8將 會直接接觸到凸塊104上，探針108的尖端容易對凸塊 造成損傷，且尖銳的探針108與球形的凸塊丨〇4接觸不易’ 在測試過程中容易造成誤測（over-kill)。然而’若在凸 塊形成之前，進行測試的話，凸塊與銲墊之間連接的錯誤 就無法察覺，且尖銳的探針也會對銲墊造成刮痕（probe 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ---- 訂--------h線， 544835 A7 B7 894twf。d〇 c / 0 〇 6 五、考爹明說明（Λ ) mark)，而影響後續在銲墊上形成凸塊的可靠度。 有鑑於止[：，本發明提供一種銲墊設計，利用電路探針 進行的最終測試可在凸塊形成之後進行，並不會影響到凸 瑰的品質。 本發明提出一種銲墊設計，在於原有連接凸塊的銲墊 之外’增加测試銲墊用以在測試進行時與探針做接觸’測 言式銲墊與連接凸塊的銲墊之間以導線連接，如此探針不會 舌1J傷連接凸塊的銲墊，也不會損害凸塊。 使用本發明提出的銲墊設計，可以使用原本的探針卡 進行電性測試，無須設計改變探針卡的設計。且測試是在 潮試鍵上進行，探針造成的刮痕是在測試鍵上，並不會出 現在凸塊或是與凸塊相接的銲墊上，因此不會影響凸塊的 形成與其可靠度。此外，測試鍵上沒有凸塊，因此測試探 針可以輕易放置在測試鍵上，不會因爲滑動而造成誤載誤 方夕的狀況。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 了文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1圖，繪示爲習知的一種封裝結構簡示圖；以及 第2圖繪示依照本發明一較佳實施例的一種銲墊設計 糸吉構簡示圖； 第3圖繪示依照本發明一較佳實施例的另一種銲墊設 言十結構簡示圖； 4 本紙張尺度iS用中國國家標準（CNS)A4規格（210 X 297公砮） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 褒--------訂---------線— ------------------------ 經濟部智慧財產局員工消費合作社印製 544835 5 894twf .doc / 006 _B7 _ 五、号务明說明（3 ) 屬4圖繪示爲依照本發明一較佳實施例的銲墊設計佈 局上視圖；以及 第5圖繪示依照本發明一較佳實施例銲墊設計的另一 種佈局上視圖。 圖示標記說明： 100，200，400 晶片 102, 202 銲墊 104, 204, 402 凸塊 106，206，214 保護膜 108, 210 探針 208 用以作爲測試銲墊的區域 212 重新配置層 212a, 404a，404b 測試墊 212b 連接凸塊的銲墊 406a，404b 連接線 貫~施例 本發明针對襲之銲墊設計的缺點，設計一個新的佈局’ 在原本連接凸塊的接合墊之外，增加一測試墊，進行測試 日寺探針係與測試墊作接觸，因此無須擔心接合墊或凸塊因 爲測試時與探針接觸而造成損害，因此不管在凸塊形成之 前，或在凸塊形成於接合墊上之後，均可進行晶片級的測 言式（wafer level testing)0 第2圖繒示依照本發明一較佳實施例的一種銲墊設計 糸吉構簡示圖。在晶片200上有一層接合墊202，接合墊202 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------訂·--------· (請先閱讀背面之注意事項再填寫本頁) 544835 A7 B7 5894twf.doc/006 五、名务明說明（洋） 上覆蓋有一層保護膜206。其中保護膜206暴露出兩處的 接合墊202，一處係用以使形成的凸塊204與接合墊202 相連接，而另一處暴露出來的區域208係用以作爲一測試 墊，在進行晶圓級的測試步驟時，可以將探針210放置在 此測試墊上進行測試。 第3圖繪示依照本發明一較佳實施例的另一種銲墊設 言十結構簡示圖。其中凸塊204並沒有直接放置在接合墊202 上，而是有一層重置層 212(redistributed layer, RDL) 自接合墊202連接出來，晶片200、接合墊202與重置層 212之間具有保護膜，用以將接合墊202與重置層212的 其他區域區隔並包覆起來，而在重置層212上有兩區域 212a、212b未被保護層214覆蓋。其中一個區域212a或 2 12b係用以作爲一測試鍵，而另一區域212b或21 2a則用 以作爲連接凸塊204的接合墊。 第4圖繪示爲依照本發明一較佳實施例的銲墊設計饰 局上視圖。在晶片400上有多個凸塊402，呈陣列的排列 狀態配置於晶片400的中央，而相對於每一個凸塊402， 其側邊皆有一測試鍵404a，測試鍵404a與凸塊402間以 導線406a作電性連接。相對於習知的銲墊設計，在凸塊402 偾J邊並沒有與凸塊電性連接的測試墊存在，因此進行晶圓 級的測試時，測試的探針均需直接與凸塊作接觸，尖銳的 探針因爲會對凸塊造成損害。 第5圖繪示依照本發明一較佳實施例銲墊設計的另一 種佈局上視圖。其中，測試鍵404b係分布於晶片400兩 6 本紙張尺度用中國國家標準（CNS)A4規格（210 X 297公釐） ^--------訂---------^ I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 544835 5 8 94twf . d〇c / 〇〇6 A7 ----- B7 五、名泰明說明（夕） 俱1J ’而凸塊402係呈陣列的排列方式分布於晶片400的中 央’測試墊404b也是透過導線406b與凸塊402作電性連 接。 在電子產品日漸趨向於輕、薄、短小、低成本與高效 冃匕的文求下’覆晶（f 1 i P c h i p)的封裝技術廣泛的被採用， 習知的覆晶封裝係將凸塊設置在晶片的中央，因此早期用 於作晶圓測試的探針卡將不適用於此覆晶結構上，陣列牌 白勺的探針卡並不容易製作，會增加製程上的困難度。 而第5圖繪示的本發明之一種佈局，其測試鍵404b仍 分布於晶片400的兩側，因此可以沿用習知的探針卡，無 須設計新的探針卡，且探針放置於測試鍵上，與凸塊並不 會接觸，不會影響凸塊的形成與產生。 也因爲湏(1試鍵與凸塊的位置不同，因此不會在與凸塊 連接的接合塾上產生刮痕，無須擔心影響形成凸塊的可靠 度，而在連接凸塊以後，仍可進行電路測試與雷射修補的 歩·驟，無須擔心損傷凸塊。 使用本發明提出的銲墊設計，可以使用原本的探針卡 進行電性測言式，無須設計改變探針卡的設計。且測試是在 損(J試鍵上進行，探針造成的刮痕是在測試鍵上’並不會出 現在凸塊或是與凸塊相接的銲墊上，因此不會影響凸塊的 形成與其可靠度。此外，測試鍵上沒有凸塊，因此測試探 針可以輕易方夕置在測試鍵上，不會因爲滑動而造成誤載誤 Μ的狀況。 雖然本發明已以一較佳實施例揭露如上，然其並非用 7 本紙張尺度1¾用中國國家標準（CNS)A4規格（210 X 297公釐） I I— --------I I — — — — — — — I (請先閱讀背面之注意事項再填寫本頁) 544835 5 894twf .doc / 006 A7 B7 五、号务明說明（ό ) 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 兩申和範圍內，當可作各種之更動與潤飾，因此本發明之保 言蒦範圍當視後附之申請專利範圍所界定者爲準。 ----------- ^--------訂---------線· (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用令國國家標準（CNS)A4規格（210x 297公釐）544835 5894twf.d〇c / ◦〇A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Statement of Examination (f) The present invention relates to a semiconductor package of flip-chip type, and in particular to ~ semiconductor packages. Structural pad design. In the semiconductor industry, the production of integrated circuits is mainly divided into three stages: "sand wafer manufacturing, integrated circuit manufacturing, and integrated circuit sealing." The packaging of the integrated circuit is the final step to complete the finished integrated circuit. The purpose of packaging is to provide a chip and a printed circuit board (printed clrcuit board, pCB) or other media that are electrically connected to the components, and to provide the function of protecting the chip. After the semiconductor process is completed, the wafer is formed by dicing the wafer. As soon as it is moved on the wafer, there will be bonding pads, which are used as test points to provide wafer shuttle testing and as endpoints for the connection between the wafer and other components. . In order to connect the chip and other components, bumps are usually formed on the pads as a medium for connecting the wires. Please refer to FIG. 1, which is a schematic diagram of a conventional package structure. There are solder pads on the wafer 100, bumps 104 on the pads 102, and pads 100 on the wafers. The other regions are covered with a protective film 106. The final test must be performed after packaging. The final test can be performed before the pad 1Q2 is connected to the bump 104, or after the bump is formed. If the test is performed after the bump 104 is formed, the probe 108 will directly contact the bump 104, and the tip of the probe 108 may easily damage the bump, and the sharp probe 108 and the spherical bump 丨 〇 4 Not easy to contact 'It is easy to cause over-kill during the test. However, 'If the test is performed before the bump is formed, the connection error between the bump and the pad cannot be detected, and the sharp probe will cause scratches on the pad (probe 3 This paper applies to Chinese national standards. (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) ---- Order -------- h-line, 544835 A7 B7 894twf.d〇c / 0 〇6 V. Kao Deming's description (Λ) mark), which affects the reliability of the subsequent formation of bumps on the pad. In view of the above [:], the present invention provides a solder pad design. The final test using the circuit probe can be performed after the bump is formed without affecting the quality of the bump. The present invention proposes a solder pad design, in addition to the original solder pad connected to the bumps, 'adding test pads to make contact with the probe during the test', the test pad and the solder pads connecting the bumps Wires are used to connect the probes in this way, so that the probes will not hurt the solder pads that connect the bumps, nor will they damage the bumps. By using the pad design proposed by the present invention, the original probe card can be used for electrical testing without designing and changing the design of the probe card. And the test is performed on the test key. The scratches caused by the probe are on the test key and will not appear on the bumps or the pads connected to the bumps, so the formation of the bumps and its reliability will not be affected. degree. In addition, there are no bumps on the test key, so the test probe can be easily placed on the test key, and it will not cause misload due to sliding. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, Wen Wen cites a preferred embodiment and describes it in detail with the accompanying drawings as follows: Brief description of the drawings: Figure 1, FIG. 2 is a schematic diagram of a conventional package structure; and FIG. 2 is a schematic diagram of a solder pad design according to a preferred embodiment of the present invention; FIG. 3 is a diagram of a preferred structure according to the present invention; Another example of a solder pad design in the embodiment is ten structural schematic diagrams; 4 This paper size iS uses the Chinese National Standard (CNS) A4 specification (210 X 297 cm) (Please read the precautions on the back before filling this page) Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau 褒 -------- Order --------- Line--------------------- ---- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 544835 5 894twf .doc / 006 _B7 _ V. No. Description (3) belongs to Figure 4 shows the pad design according to a preferred embodiment of the present invention Layout top view; and FIG. 5 shows another layout top view of a pad design according to a preferred embodiment of the present invention. Description of pictographs: 100, 200, 400 wafers 102, 202 pads 104, 204, 402 bumps 106, 206, 214 protective films 108, 210 probes 208 are used as areas for test pads 212 reconfiguration layer 212a, 404a, 404b test pads 212b solder pads connected to bumps 406a, 404b connection line ~ Example The present invention designs a new layout to address the shortcomings of the pad design, in addition to the bonding pads that originally connected the bumps, Add a test pad to make the test. The temple probe is in contact with the test pad, so there is no need to worry about the damage of the bonding pad or the bump due to the contact with the probe during the test, so no matter before the bump formation or the bump formation After the bonding pads, wafer level testing (wafer level testing) can be performed. Figure 2 shows a schematic diagram of a solder pad design according to a preferred embodiment of the present invention. There is a layer of bonding pad 202 on the wafer 200, and the bonding pad 202 5 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -------- Order · ------- -· (Please read the precautions on the back before filling out this page) 544835 A7 B7 5894twf.doc / 006 V. Ming Wu Ming Instructions (foreign) is covered with a protective film 206. The protective film 206 exposes two bonding pads 202. One is used to connect the formed bump 204 to the bonding pad 202, and the other exposed area 208 is used as a test pad. During the wafer-level test step, the probe 210 may be placed on the test pad for testing. Fig. 3 is a schematic diagram showing the structure of another solder pad design according to a preferred embodiment of the present invention. The bump 204 is not directly placed on the bonding pad 202, but has a redistribution layer 212 (RDL) connected from the bonding pad 202. The chip 200, the bonding pad 202, and the reset layer 212 are protected. A film for separating and covering the bonding pad 202 from other areas of the reset layer 212, and two areas 212 a and 212 b on the reset layer 212 are not covered by the protective layer 214. One of the areas 212a or 2 12b is used as a test key, and the other area 212b or 21 2a is used as a bonding pad for connecting the bumps 204. FIG. 4 is a top view of a pad design decoration according to a preferred embodiment of the present invention. There are a plurality of bumps 402 on the wafer 400, which are arranged in an array in the center of the wafer 400. With respect to each bump 402, there is a test key 404a on the side, and the test key 404a and the bump 402 are spaced between them. The lead 406a is electrically connected. Compared with the conventional pad design, there is no test pad electrically connected to the bump on the side of the bump 402 偾 J, so when testing at the wafer level, the test probes need to directly contact the bump. The sharp probe will cause damage to the bumps. FIG. 5 is a top view of another layout of a pad design according to a preferred embodiment of the present invention. Among them, the test keys 404b are distributed on the wafer 400. The paper size uses the Chinese National Standard (CNS) A4 specification (210 X 297 mm). ^ -------- Order --------- ^ I (Please read the notes on the back before filling out this page) Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 544835 5 8 94twf. D〇c / 〇〇6 A7- --- B7 V. Ming Taiming's description (Xi) 1J 'The bumps 402 are distributed in the array in the center of the chip 400' The test pad 404b is also electrically connected to the bumps 402 through the wires 406b. With the increasing demand for electronic products to be lighter, thinner, shorter, lower cost, and more efficient, the flip-chip (f 1 i P chip) packaging technology is widely used. The conventional flip-chip packaging system will bump It is set in the center of the wafer, so the probe cards used for wafer testing in the early days will not be suitable for this flip-chip structure. The probe cards for array cards are not easy to make, which will increase the difficulty in the process. In the layout of the present invention shown in FIG. 5, the test keys 404b are still distributed on both sides of the wafer 400, so the conventional probe card can be used, without designing a new probe card, and the probe is placed in the test On the key, there is no contact with the bump, and it will not affect the formation and generation of the bump. Also, because the position of 湏 (1 test key and the bump is different, there will be no scratches on the joint 与 connected to the bump, there is no need to worry about affecting the reliability of the formation of the bump, and it can still be performed after connecting the bump The steps of circuit testing and laser repairing do not need to worry about damaging the bumps. Using the pad design proposed by the present invention, the original probe card can be used for electrical testing without the need to design and change the design of the probe card. The test is performed on the test key (J test key, the scratches caused by the probe are on the test key 'and will not appear on the bump or the pad connected to the bump, so it will not affect the formation of the bump and the Reliability. In addition, there are no bumps on the test key, so the test probe can be easily placed on the test key, and it will not cause misloading and error due to sliding. Although the present invention has been disclosed in a preferred embodiment As above, but it does not use 7 paper sizes 1¾ using China National Standard (CNS) A4 (210 X 297 mm) II — -------- II — — — — — — — I (Please read first Note on the back, please fill out this page) 544835 5 894twf .doc / 006 A7 B7 Fifth, the number of instructions (ό) to limit the present invention, anyone skilled in this art, without departing from the spirit and scope of the present invention, should be able to make various changes and retouching, so this The scope of the guarantee of the invention shall be determined by the scope of the attached patent application. ----------- ^ -------- Order --------- Line · (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives This paper is sized to the national standard (CNS) A4 (210x 297 mm)