JP2003218178A - Semiconductor device and semiconductor chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the internal information and the information of the way of the operation of an LSI from being illegally analyzed in the state of an LSI chip by abusing an inspection circuit and a pad for an inspection used for the inspection of respective internal circuits at the time of a semiconductor device in a wafer state before being divided into the LSI chips for an IC card. <P>SOLUTION: The pad 314 for the inspection for operating the inspection circuit 313 inspecting the internal circuit 312 of a first LSI region 311 on a wafer is arranged in a second LSI region 321 which is a different LSI region close to the LSI region 311. After performing the inspection by using the pad 314 for the inspection and the inspection circuit 313, a scribe region 103 is scribed so as to cut off the first LSI region 311 into the LSI chip of a single body. At the time, since inspection wiring 316 is cut off, the pad 314 for the inspection and the inspection circuit 313 connected by the inspection wiring 316 are disconnected. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device divided into semiconductor chips such as an IC card LSI chip mounted on an IC card and the semiconductor chip thereof.
More specifically, the present invention relates to measures for protecting information stored in each semiconductor chip and information on the operation of each semiconductor chip.

[0002]

2. Description of the Related Art In recent years, IC cards equipped with semiconductor chips have begun to spread rapidly. For example, in the telephone industry, IC telephone cards have already been introduced, and
In the railway industry, commercialization of IC commuter pass system is planned. In addition, practical applications in various fields such as electronic money and identification are being studied.

An LSI chip for an IC card is a CPU,
It has an internal circuit composed of a semiconductor memory and the like, and generally also has an inspection circuit for inspecting these internal circuits. Then, in a wafer state before being divided into a plurality of LSI chips, the internal circuit can be inspected by using the inspection pad provided for each inspection circuit.

Now, referring to FIG. 7, a conventional semiconductor device will be described. When inspecting the internal circuit 2 formed in each LSI area 1 on a wafer, the LSI area 1 is to be inspected.
Using the upper inspection pad 4, the inspection circuit 3 on the same LSI area 1 is operated. That is, the internal circuit 2 is operated by inputting data from the outside to the inspection circuit 3 using the inspection pad 4, and based on the data output from the internal circuit 2 to the inspection pad 4 via the inspection circuit 3. It is designed to inspect whether the LSI operates normally.

[0005]

However, in the above-described conventional semiconductor device, it is possible to operate the internal circuit 2 of the LSI by using the inspection pad 4 even after being divided into the LSI chips. Internal circuit 2
There is a possibility that important information such as personal information and identification number stored in the semiconductor memory therein may be easily read or written, and information such as how the LSI operates may be illegally analyzed.

The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device having a pad for inspecting an internal circuit formed in each region on a wafer and divided into a plurality of semiconductor chips. In the above, by devising the arrangement of the inspection pad, it is possible to prevent the information inside the semiconductor chip from being illegally analyzed by using the inspection pad.

[0007]

In order to achieve the above object, in the present invention, attention is paid to the fact that a semiconductor device is divided into a plurality of semiconductor chips. By disposing the semiconductor device in a region different from the region where the internal circuit is formed, the internal circuit and the inspection pad are separated when the semiconductor device is divided into a plurality of regions.

Specifically, in the invention of claim 1, as a semiconductor device, the semiconductor device is arranged in at least one of a plurality of regions set on a wafer, and data is input / output to / from the outside. And an inspection wiring for connecting the inspection pad and an internal circuit formed in the region other than the region where the inspection pad is arranged.

In the above structure, when each area on the wafer is cut into individual semiconductor chips after the inspection of the internal circuit performed using the inspection pad, the area on the wafer where the internal circuit is formed, Since the area on the wafer in which the inspection pad corresponding to the internal circuit is arranged is different from each other, the inspection wiring connecting the internal circuit and the inspection pad is cut. As a result, in the state of the semiconductor chip, it is impossible to operate the internal circuit by using the inspection pad, and it is possible to prevent the information inside the semiconductor chip from being illegally analyzed.

According to a second aspect of the invention, there is provided a dummy pad according to the first aspect of the invention, the dummy pad being provided in a region where the inspection pad is arranged and not connected to an internal circuit in the entire region.

According to a third aspect of the present invention, in the second aspect of the present invention, a dummy wiring which is provided between the internal circuit and the dummy pad and which does not connect the internal circuit and the dummy pad is provided.

According to a fourth aspect of the present invention, in the first aspect of the present invention, the area where the inspection pad is arranged is used as an inspection area, and on the other hand, the area around the inspection area is located close to the inspection area. LS in which internal circuits are formed
I area. The inspection pads are provided for the internal circuits of the plurality of LSI areas, and the inspection wirings are provided with the inspection pads and the internal circuits corresponding to the inspection pads, respectively. It shall be provided so as to connect with.

According to a fifth aspect of the invention, in the fourth aspect of the invention, the internal wiring is provided on the basis of the input / output of data to / from the outside which is provided on each inspection wiring and is performed via the inspection pad. When a plurality of inspection circuits for inspecting a circuit are provided, it is assumed that the plurality of inspection circuits are arranged in each LSI area.

According to a sixth aspect of the invention, in the fourth aspect of the invention, when a plurality of inspection circuits are provided as in the case of the fifth aspect of the invention, the plurality of inspection circuits are arranged in the inspection area. It has been done.

According to a seventh aspect of the invention, a semiconductor chip is obtained by dividing the semiconductor device according to the first to sixth aspects into a plurality of regions.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows the configuration of a semiconductor device according to a first embodiment of the present invention.

In the figure, reference numeral 311 denotes a first LSI area set on the wafer.
11 includes an internal circuit 312 and an inspection circuit 313 for inspecting the internal circuit 312.

On the other hand, reference numeral 321 in FIG.
11 is a second LSI area which is adjacent to the first LSI area 311 and is different from the first LSI area 311. In the second LSI area 321, data is input from the outside to the inspection circuit 313 on the first LSI area 311 or An inspection pad 314 for outputting the data from the inspection circuit 313 to the outside is provided.

Reference numeral 316 is an inspection wiring, and this inspection wiring 316 is an internal circuit 312 of the first LSI area 311.
And the inspection pad 314 on the second LSI area 321 are connected via the inspection circuit 313 on the first LSI area 311. 103 is the first LSI
This is a scribe area set on the wafer between the area 311 and the second LSI area 321, and this scribe area 103 is for separating the LSI in which the internal circuit 312 is formed in the first LSI area 311 into a single LSI chip. belongs to.

A process for inspecting the internal circuit 312 of the first LSI area 311 in the semiconductor device configured as described above will be described.

First, data is externally input to the inspection circuit 313 on the first LSI area 311 by using the inspection pad 314 on the second LSI area 321, thereby operating the internal circuit 312, and the data is inspected by the inspection circuit 313. Output to the outside through the inspection pad 314.

After the inspection is completed, the scribe area 103 is cut, and the LSI having the internal circuit 312 formed in the first LSI area 311 is cut into a single LSI chip. At this time, since the portion of the inspection wiring 316 between the inspection circuit 313 and the inspection pad 314 straddles the scribe region 103, the inspection wiring 316 is also cut.

Therefore, according to this embodiment, when the first LSI area 311 of the semiconductor device is separated into a single LSI chip, the inspection circuit 313 on the first LSI area 311 and the inspection pad on the second LSI area 321 are separated. 31
Since the inspection wiring 316 is disconnected between the inspection circuit 4 and the wiring 4, the inspection circuit 313 of the LSI chip cannot be operated by using the inspection pad 314 in the state of the LSI chip. Therefore, the inspection circuit 313 is used. It is possible to prevent a situation in which information inside the LSI is illegally obtained.

Further, the inspection pad 314 is connected to the first LSI.
Instead of the scribe area 103 around the area 311, the second
Since it is arranged in the LSI area 321, only the inspection wiring 316 exists in the scribe area 103. Therefore, such an inspection pad does not exist as compared with the case where the inspection pad is arranged in the scribe area 103. The area of the scribe region 103 can be reduced accordingly.

In the above embodiment, the internal circuit 312 of the first LSI area 311 is described, but it is optional whether or not the internal circuit is formed in the second LSI area 321.

(Second Embodiment) FIG. 2 shows the structure of a semiconductor device according to a second embodiment of the present invention.

In the present embodiment, the dummy pads 315 are provided in the second LSI area 321 together with the inspection pads 314. The dummy pads 315 and the first LSI are provided.
Between the inspection circuit 313 on the area 311 and the dummy pads 31 opened on the scribe area 103.
5 is not connected to the inspection circuit 313, or a dummy wiring 317 which is connected but does not reach the internal circuit 312 of the first LSI region 311 is provided. In addition,
The other configuration is the same as that of the first embodiment, and thus the description is omitted.

Therefore, according to this embodiment, the first L
A dummy pad 315 is provided in the second LSI area 321 adjacent to the SI area 311, and the dummy pad 315 and the first pad 315 are provided.
Inspection circuit 313 on LSI area 311 to first LSI
A dummy wiring 317 is provided between the area 311 and the internal circuit 312.
Since the first LSI region 311 is cut out into a single LSI chip, the inspection wiring 3 in which the connection between the inspection circuit 313 and the inspection pad 314 is cut off is provided.
16 via the internal circuit 312 of the first LSI area 311
However, the presence of the dummy pad 315 and the dummy wiring 317 makes the analysis even more difficult, and it is possible to prevent the information inside the LSI from being illegally obtained by using the inspection circuit 313.

(Third Embodiment) FIGS. 3 to 5 show the structure of a semiconductor device according to a third embodiment of the present invention.

In this embodiment, a plurality of substantially rectangular regions are arranged on the wafer of the semiconductor device in the vertical direction (vertical direction of each drawing) and in the horizontal direction (horizontal direction of each drawing). It is set. Of these areas, 301 is an inspection area dedicated to inspection in which no internal circuit is formed,
In the vertical and horizontal directions of this inspection area 301, the first
-Fourth four LSI areas 311, 321, 331, 3
41 are arranged adjacent to each other. These one inspection area 301 and four LSI areas 311, 321, 33
1, 341 constitutes an inspection unit 401, and the inspection is performed with the inspection unit 401 as one unit.
The plurality of inspection units 401 are set in the arrangement shown in FIG.

In FIG. 3, reference numeral 312 is an internal circuit formed in the first LSI area 311. Also, 313 is
The inspection circuit 313 is provided in the first LSI area 311, and the inspection circuit 313 is for inspecting the internal circuit 312 of the first LSI area 311. 322 is the second L
Reference numeral 323 denotes an internal circuit of the SI area 321, and reference numeral 323 denotes an inspection circuit provided in the second LSI area 321 for inspecting the internal circuit 322. 332 is the third LSI area 3
31 is an internal circuit, and 333 is an internal circuit 332 thereof.
Is an inspection circuit provided in the third LSI area 331 for inspecting. Reference numeral 342 is an internal circuit of the fourth LSI area 341, and reference numeral 343 is an inspection circuit provided in the fourth LSI area 341 for inspecting the internal circuit 342.

On the other hand, 314 and 315 are respectively
In the inspection area 301, the inspection pad and the dummy pad are provided on the side closest to the first LSI area 311 (the upper side in FIG. 3). The inspection pad 314 is the first
This is for inspecting the internal circuit 312 of the LSI area 311, and the reference numeral 316 indicates the inspection pad 314 and the internal circuit 312 of the inspection circuit 313 on the first LSI area 311.
It is the inspection wiring that is connected via. In contrast, 31
Numeral 7 is a dummy wiring which is arranged so as to pass through the inspection circuit 313 between the dummy pad 315 and the internal circuit 312, but does not actually connect the dummy pad 315 and the internal circuit 312.

Reference numerals 324 and 325 respectively denote a test pad and a dummy pad provided on the side closest to the second LSI area 321 (right side in FIG. 3) in the test area 301. The inspection pad 324 is the second LSI.
The area 321 is for inspecting the internal circuit 322, and 326 is the inspection pad 324 and the internal circuit 32.
2 is an inspection wiring for connecting the wirings 2 and 2 via the inspection circuit 323 on the second LSI area 321. In contrast, 327 is
Although it is arranged between the dummy pad 325 and the internal circuit 322 so as to pass through the inspection circuit 323, it is actually a dummy wiring that does not connect the dummy pad 325 and the internal circuit 322.

Reference numerals 334 and 335 are a test pad and a dummy pad provided on the side closest to the third LSI area 331 (lower side in FIG. 3) in the test area 301. The inspection pad 334 is the third LSI.
This is for inspecting the internal circuit 332 in the region 331, and 336 is the inspection pad 334 and the internal circuit 33.
2 is an inspection wiring for connecting the wirings 2 and 3 via the inspection circuit 333 on the third LSI area 331. In contrast, 337 is
Although it is arranged between the dummy pad 335 and the internal circuit 332 so as to pass through the inspection circuit 333, it is actually a dummy wiring that does not connect the dummy pad 335 and the internal circuit 332.

Reference numerals 344 and 345 respectively denote a test pad and a dummy pad provided on the side closest to the fourth LSI area 341 (left side in FIG. 3) in the test area 301. The inspection pad 344 is the fourth LSI.
The internal circuit 342 in the area 341 is inspected, and the reference numeral 346 indicates the inspection pad 344 and the internal circuit 34.
2 is an inspection wiring for connecting the wirings 2 and 2 via the inspection circuit 343 on the fourth LSI area 341. In contrast, 347 is
Although it is arranged so as to pass through the inspection circuit 343 between the dummy pad 345 and the internal circuit 342, it is actually a dummy wiring that does not connect the dummy pad 345 and the internal circuit 342.

In the semiconductor device configured as described above, the first to fourth four LSI areas 311, 321, 3
Internal circuits 312, 322, 332, 34 of 31, 341
2 is inspected, the inspection pads 314, 324, 334, 344 on the inspection area 301 are used respectively, and the inspection circuits 313, 323, 333 on the first to fourth LSI areas 311, 321, 331, 341 are used. This is performed by operating each 343.

Therefore, according to the present embodiment, after the inspection is completed, the scribe area 103 is scribed to obtain four Ls.
When the SI areas 311, 321, 331, 341 are cut into individual LSI chips, respectively, the inspection circuits 313, 3
23, 333, 343 and inspection pads 314, 32
Inspection wiring 31 for connecting 4,334 and 344, respectively
6, 326, 336, 346 are also cut, so that the inspection pads 314, 324, 334, 344 after scribing
It becomes impossible to operate the inspection circuits 313, 323, 333, 343 by using, and thus it is possible to prevent the information of the internal circuits 312, 322, 332, 342 of those LSI chips from being analyzed.

Further, the dummy pad 3 is formed in the inspection area 301.
15, 325, 335, 345 are provided, and the dummy wiring 31 is provided on the inspection wirings 316, 326, 336, 346.
Since 7,327,337,337 and 347 are provided side by side, even if the inspection area 301 and the LSI areas 311, 321, 331, 341 are combined after scribing, the inspection circuits 313, 323, 333, 343 and the inspection area It becomes difficult to analyze each relationship with the pad 314, 324, 334, 344.

Further, in the inspection area 301, four LSI areas 311, 321 adjacent to the inspection area 301 are provided.
Internal circuits 312, 322, 332, 3 of 331, 341
Inspection pads 314, 324, 3 for inspecting 42
34 and 344 are provided, and these four regions 301 and 31 are provided.
Since 1,321,331,341 are set as the inspection unit 401, the four LSI areas 311, 321, 33
1,341 can be inspected at the same time, and as a result, the inspection speed can be improved.

(Fourth Embodiment) FIG. 6 shows the structure of a semiconductor device according to a fourth embodiment of the present invention. This embodiment is similar to the third embodiment, and one inspection device is used. The area 301 and the first to fourth LSI areas 311 and 3 adjacent to the inspection area 301 in the vertical and horizontal directions.
21, 331, 341 constitute the inspection unit 401, and the LSI areas 311, 321, 331, 34
1 internal circuits 312, 322, 332, 342 for inspection pads 314, 324, 334, 344
Are arranged in the inspection area 301.

This embodiment is different from the third embodiment in that the inspection circuits 313, 323, 333, 343 for inspecting the internal circuits 312, 322, 332, 342 of the LSI areas 311, 321, 331, 341 respectively, LS
This is a point that is arranged not in the I areas 311, 321, 331, 341 but in the inspection area 301.

Further, the dummy wirings 317, 327, 33
7 and 347 are basically dummy pads 315 and 32.
5,335,345 and corresponding LSI areas 311,3
Internal circuits 312, 322, 33 of 21, 331, 341
However, the dummy pads 315, 325, 335, 345 are preferable.
From the inspection circuit 313, 323, 333, 343 to the scribe area 103.
Similar to the case of 16, 326, 336, and 346, it is provided without interruption, and is opened between reaching the scribe region 103 and reaching the internal circuits 312, 322, 332, 342, and the dummy pad 315. , 3
25, 335, 345 and internal circuits 312, 322, 33
2, 342 are not connected.

Therefore, according to the present embodiment, after the inspection is completed, scribing is performed in the scribing area 103 to obtain four Ls.
When the SI areas 311, 321, 331, 341 are separated into individual units, the internal circuits 312, 322, 33
2, 342 and inspection circuits 313, 323, 333, 343
And inspection wirings 316, 326, 33 for respectively connecting
6 and 346 are cut, dummy wiring 317,
Due to the existence of 327, 337 and 347, the inspection circuits 313 and 32 are provided after the scribe as in the case of the fourth embodiment.
3,333,343 can be used to prevent each internal circuit 312, 322, 332, 342 of the LSI chip from being analyzed.

Further, in this embodiment, the inspection circuit 313,
323, 333, 343 in the LSI areas 311, 32
1, 331, and 341 are arranged in the inspection area 301, the safety after scribing is higher than in the case of the fourth embodiment, and the inspection circuit 3 is not provided.
LSI area 31 corresponding to 13,323,333,343
The areas of 1, 321, 331, and 341 can be reduced.

[0046]

As described above, according to the present invention, the inspection pad for inspecting the internal circuit is arranged in a region other than the region where the internal circuit inspected by using the inspection pad is formed. Thus, when the semiconductor device is divided into a plurality of semiconductor chips, it is possible to disconnect the inspection wiring between the inspection pad and the internal circuit, and thus the information inside the semiconductor chip can be used by using the inspection pad. It can be prevented from being obtained illegally.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing a configuration of a main part of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically showing a configuration of a main part of a semiconductor device according to a second embodiment of the present invention, which is equivalent to FIG.

FIG. 3 is a plan view schematically showing a configuration of a main part of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a plan view showing the structure of an inspection unit.

FIG. 5 is a plan view showing an arrangement of inspection units.

FIG. 6 is a view corresponding to FIG. 3 and schematically showing a configuration of a main part of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 7 is a diagram corresponding to FIG. 1 showing a configuration of a conventional semiconductor device.

[Explanation of symbols]

301 Inspection area (area) 311 First LSI area (area) 312 Internal circuit 313 Inspection circuit 314 Inspection pad 315 dummy pad 316 Inspection wiring 317 dummy wiring 321 Second LSI area (area) 322 Internal circuit 323 Inspection circuit 324 Inspection pad 325 dummy pad 326 Inspection wiring 327 dummy wiring 331 Third LSI area (area) 332 Internal circuit 333 inspection circuit 334 Inspection pad 335 dummy pad 336 inspection wiring 337 dummy wiring 341 Fourth LSI area (area) 342 Internal circuit 343 inspection circuit 344 Inspection Pad 345 dummy pad 346 inspection wiring 347 dummy wiring

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 2G132 AA00 AA01 AA08 AA18 AB01                       AK02 AK22 AL31                 4M106 AA01 AD01 AD06 DJ38                 5F033 MM21 UU03 VV01 VV07 VV12                       XX37                 5F038 BE10 CA10 CA13 CA18 CD10                       DF10 DT03 DT04 DT15 EZ20

Claims (7)

[Claims] 1. An inspection pad, which is arranged in at least one of a plurality of areas set on a wafer, for inputting and outputting data to and from the outside, the inspection pad, and the inspection pad. A semiconductor device comprising: an inspection wiring for connecting an internal circuit formed in the region other than the region where the pad is arranged. 2. The semiconductor device according to claim 1, further comprising a dummy pad which is provided in a region where the inspection pad is arranged and which is not connected to an internal circuit in the entire region. 3. The semiconductor device according to claim 2, further comprising a dummy wiring which is provided between the internal circuit and the dummy pad and which does not connect the internal circuit and the dummy pad. 4. The semiconductor device according to claim 1, wherein an area where the inspection pad is arranged is an inspection area, and a plurality of areas are disposed around the inspection area and in proximity to the inspection area. Is an LSI area in which an internal circuit is formed, the inspection pads are provided for the internal circuits of the plurality of LSI areas, and the inspection wiring is provided with the plurality of inspection pads and the inspection pad, respectively. A semiconductor device provided so as to be connected to the internal circuit corresponding to an inspection pad. 5. The semiconductor device according to claim 4, wherein a plurality of inspection circuits are provided on each inspection wiring and inspect an internal circuit based on input / output of data to / from the outside performed via an inspection pad. 2. A semiconductor device comprising the inspection circuit according to claim 1, wherein each of the plurality of inspection circuits is arranged in each LSI area. 6. The semiconductor device according to claim 4, wherein a plurality of inspection circuits are provided on each inspection wiring and inspect an internal circuit based on input / output of data to / from the outside performed via an inspection pad. 2. A semiconductor device comprising the inspection circuit according to claim 1, wherein the plurality of inspection circuits are arranged in an inspection area. 7. A semiconductor chip obtained by dividing the semiconductor device according to claim 1, 2, 3, 4, 5 or 6 into a plurality of regions.