JP2005030877A - Semiconductor integrated circuit device equipped with radio control test function - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To further reduce test costs in a semiconductor integrated circuit. <P>SOLUTION: A built-in test circuit and a radio communication circuit are mounted into a semiconductor integrated circuit device, and the built-in test circuit is controlled by a radio signal to execute test. It is possible to reduce the number of pins of a test interface since test input and output signals can be unwired by using this means. Therefore it is possible to reduce the test costs since probe cards or jigs such as test boards can be made inexpensive, contact is easily achieved to simultaneously test a large number of chips. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for facilitating a test of a semiconductor integrated circuit device, and more particularly to reducing the number of pins of a test interface for the purpose of reducing the test cost of a semiconductor integrated circuit device.
[0002]
[Prior art]
FIG. 1 shows a conventional configuration example of an interface for performing a test by connecting a semiconductor integrated circuit device having a built-in test circuit to an external test device. In FIG. 1, 1 is a semiconductor chip on which a semiconductor integrated circuit device is formed, 2 is a test access port control circuit compliant with the IEEE 1149.1 standard, 3 is a test interface pad, 13 is a built-in test circuit, and 14 is a test. The target circuit, 15 is a user signal pad of this apparatus, and 19a and 19b are power supply wirings. VCC and VSS are power sources, and TCK, TMS, TDI, and TDO are signals of the test access port control circuit 2.
[0003]
The built-in test circuit 13 is a circuit that tests whether the test target circuit 14 operates correctly, performs a function test in a low-speed cycle, an AC test in a high-speed cycle, etc. according to an input command, and outputs a test result. . Communication between the built-in test circuit 13 and the outside is performed by a serial signal via the test access port control circuit 2. In test access port control circuit 2, clock signal TCK and mode select signal TMS are used for state control of test access port control circuit 2, and data input TDI and data output TDO are used for transmission / reception of serial signals. Accordingly, in testing a semiconductor chip 1 on a wafer on which a plurality of semiconductor chips 1 are formed, it is not necessary to set up probe pins on a large number of pads 15, and probe pins need only be set up on six pads 3.
[0004]
Also, there is a report of a semiconductor device technology that returns information in a wireless and non-contact manner in response to an inquiry from an interrogator, not as a test technology for a semiconductor integrated circuit device. (For example, refer to Patent Document 1.) This semiconductor device includes a resonance circuit including an antenna coil and a capacitor, a power supply circuit that doubles rectifies a received microwave signal to obtain a power supply voltage, and a received microwave signal. Modulator that gives modulation, demodulator circuit that demodulates microwave signal to extract clock signal, amplifier that amplifies clock signal, ROM in which information for identifying semiconductor device is written, decode to read ROM contents bit by bit A circuit and a modulation circuit for modulating the read information into a microwave signal are provided. Disclosed is a technology in which the semiconductor chip is ultra-compact, and a mounting substrate on which the semiconductor chip is mounted can be freely attached to objects of various shapes such as boxes, bags, and cylinders, and identification information can be obtained without contact. ing.
[0005]
In addition, a pen-type reading device for efficiently reading information from a small non-contact recognition transponder such as the semiconductor device has been proposed. (For example, see Patent Document 2.)
In addition, a technique has been proposed in which IC Pin leakage current is tested in a non-contact manner using a boundary scan access conforming to the IEEE1149.1 standard. (For example, refer nonpatent literature 1.)
[Patent Document 1]
JP 2002-184872 A (Page 6-8, FIG. 1 and FIG. 6)
[Patent Document 2]
JP 2002-183676 A (page 2-3, FIG. 1)
[Non-Patent Document 1]
Stephen Sunter, Charles McDonald, Givargis Digital "Contactless Digital Testing of IC Pin Leakage Currents" International Test Conference 2001 IE
p. 204-210
[0006]
[Problems to be solved by the invention]
While the manufacturing costs of semiconductor integrated circuit devices are decreasing year by year due to process miniaturization and wafer diameter increase, testing must still be performed for each semiconductor integrated circuit device and for each function provided in the device. Test costs are not reduced. Therefore, the problem is that the ratio of the test cost to the total cost of the semiconductor integrated circuit device is increasing year by year.
[0007]
As a general solution for reducing the test cost, there is a method of mounting a built-in test circuit and a low pin test interface in a semiconductor integrated circuit device. For example, in the wafer test, an inexpensive test apparatus with a small number of channels and an inexpensive probe card with a small number of probe pins can be used by reducing the number of pins in the test interface. Also, when using a test device with a large number of channels and a probe card with a large number of probe pins, more semiconductor integrated circuit devices can be tested simultaneously by reducing the number of pins in the test interface. In any case, the test cost can be reduced. Therefore, in order to keep the test cost ratio constant, it is necessary to reduce the number of pins of the test interface year by year.
[0008]
However, in the first conventional example shown in FIG. 1, the standard of IEEE 1149.1, which is an existing low pin test interface technology, is adopted, but the number of pins of the test interface can be reduced to only 6 pins including the power supply. Absent.
[0009]
Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device having a further low pin test interface in order to reduce the test cost.
[0010]
It is another object of the present invention to provide a probe card for testing the semiconductor integrated circuit device and to provide a package including the semiconductor integrated circuit device.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor integrated circuit device according to the present invention includes a wireless communication circuit for controlling a built-in test circuit. A power generation circuit that generates power using a carrier wave of a radio signal transmitted from an external test device, and a memory that records an ID code and a test result of the circuit to be tested are provided. Test input / output by providing a function to collate the ID code sent from the outside with its own ID code, receive a command for itself, and send the test result of the circuit under test to the outside Since the signal can be wireless, the test interface can be reduced in number of pins.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals indicate the same or similar items.
<Embodiment 1>
FIG. 2 is a block diagram of the semiconductor integrated circuit device showing the first embodiment of the present invention. In FIG. 2, 11 is a semiconductor chip on which a semiconductor integrated circuit device is formed, 12 is a wireless communication circuit, 13 is a built-in test circuit, 14 is a test target circuit, 15 is a user signal pad of this device, and 16a and 16b are wireless. A signal, 17 is a power generation circuit, 18 is a storage device, and 19a and 19b are power supply wirings.
[0013]
The built-in test circuit 13 is a circuit that tests whether the test target circuit 14 operates correctly, performs a function test in a low-speed cycle, an AC test in a high-speed cycle, etc. according to an input command, and outputs a test result. . Communication between the built-in test circuit 13 and the outside is performed by wireless signals 16 a and 16 b via the wireless communication circuit 12. The power generation circuit 17 is a circuit that supplies power to the semiconductor chip 11 and generates power using a carrier wave of a radio signal 16a input from the outside. The storage device 18 is a device that stores a unique ID (IDentification) code given to each semiconductor chip 11. The ID code is added to the information of the radio signal 16b so that the semiconductor chip 11 that transmits the radio signal 16b can be specified when testing a wafer on which a plurality of semiconductor chips 11 are formed adjacent to each other. Conversely, if an ID code is added to the information of the radio signal 16a, a specific semiconductor chip 11 can be controlled.
[0014]
The specific configuration method of the wireless communication circuit 12 can be easily realized with a small area by applying an existing technology for RFID (Radio Frequency IDentification) instead of the barcode. For example, a specific configuration example thereof is disclosed in Patent Document 1. Patent Document 1 also mentions a specific configuration example of the power generation circuit 17 and the storage device 18 and a method of generating a clock signal supplied to the circuit 13. If the communication function of Patent Document 1 is applied, a test command and a test result can be transmitted and received wirelessly.
[0015]
In summary, since the semiconductor chip 11 includes the wireless communication circuit 12 and the power generation circuit 13, it is not necessary to raise any probe pins when testing a wafer on which a plurality of semiconductor chips 11 are formed. Number can be 0 pins.
<Embodiment 2>
FIG. 3 is a configuration diagram of a semiconductor integrated circuit device showing a second embodiment of the present invention. The only difference from the semiconductor integrated circuit device shown in FIG. 2 is that the power supply pads 20a and 20b are provided.
[0016]
The power pads 20a and 20b are used for power supply when the power generation circuit 17 cannot supply sufficient power to the semiconductor chip 11. For example, in a semiconductor chip with high power consumption such as a microprocessor having a high operating frequency, a large-capacity dynamic random access memory (DRAM), and a large area system-on-chip, if the power supply pads 20a and 20b are provided in advance, the test can be performed. In this case, probe pins need only be provided on the power supply pads 20a and 20b, and the number of pins of the test interface can be reduced to two.
[0017]
FIG. 4 is a configuration diagram of a test flow of the semiconductor integrated circuit device shown in FIGS. In FIG. 4, 21 is a function test, 22 is a first AC test, 23 is a scribing and packaging process, 24 is a DC test, and 25 is a second AC test. Reference numeral 26 denotes a wafer test in a state where a large number of semiconductor integrated circuit devices are formed on the wafer, and 27 denotes a package test in a state where the semiconductor integrated circuit devices are individually packaged.
[0018]
The wafer test 26 uses a built-in test circuit to perform a low-speed cycle function test 21 to detect a malfunction due to a stuck-at fault. Further, a high-speed AC test 22 is performed to detect a timing failure due to excessive device variations. In step 23, only semiconductor chips that pass the wafer test 26 are mounted on the package. In the package test 27, a test that is basically not possible with the built-in test circuit is performed using a test apparatus. In the DC test 24, an open or short defect of the pad 15 that has not been detected in the wafer test is detected together with an open or short defect of the package pin. Further, in the AC test 25, a timing failure between the pad 15 and the test target circuit 14 is detected. Eventually, a package that passes the package test 27 becomes a non-defective product.
[0019]
FIG. 5 is a first configuration diagram of a jig for testing the semiconductor integrated circuit device shown in FIG. In FIG. 5, 31 is a wafer to be tested, 32 is an antenna coil on a semiconductor chip, 33 is a probe card as a test jig, 34 is a region corresponding to the semiconductor chip 11, 35 is a monopole antenna, 36a and Reference numeral 36b denotes a power probe pin.
[0020]
The probe card 33 is a jig used for testing the wafer 31, and can test four semiconductor chips 11 simultaneously. Note that FIG. 5 is a perspective view seen from above, and the monopole antenna 35 and the probe pins 36 a and 36 b are located on the back side of the probe card 33.
[0021]
The specific configuration method of the antenna coil 32 and the monopole antenna 35 can be easily realized with a small area by applying the existing technology for RFID. For example, a specific configuration example is disclosed in Patent Document 1 and Patent Document 2.
[0022]
Using the above technique, the monopole antenna 35 can be realized with the same structure as the probe pins 36a and 36b. However, since the monopole antenna 35 does not need to be in contact with the semiconductor chip 11 and the positioning accuracy is low, there is no problem, so that it can be made cheaper than a probe card for a 3-pin test interface.
[0023]
FIG. 6 is a second block diagram of a jig for testing the semiconductor integrated circuit device shown in FIG. A significant difference from FIG. 5 is the arrangement of the antenna coil 32 and the monopole antenna 35. Since the antenna coil 32 is provided at the edge of the semiconductor chip 11, if the monopole antenna 35 is provided on the probe card 33 at the semiconductor chip boundary, the antenna coil 32 can communicate with the plurality of semiconductor chips 11. In FIG. 6, since the common monopole antenna 35 is provided at the boundary of the four semiconductor chips 11, it can be made cheaper than the probe card shown in FIG.
FIG. 7 is a configuration diagram of a semiconductor integrated circuit device showing a third embodiment of the present invention. The only difference from the semiconductor integrated circuit device shown in FIG. 3 is that it includes 91 nonvolatile storage devices. The nonvolatile storage device 91 may be provided separately from the storage device 18 that stores the ID code, or may be replaced. However, when replacing, power is supplied from the power generation circuit 17 so that the ID code can be read completely wirelessly. The main use of the nonvolatile storage device 91 is to record test results temporarily and permanently. By recording the test result on the semiconductor chip 11 itself, the burden on the test apparatus can be reduced and the test apparatus can be made inexpensive.
[0024]
Specific examples of the configuration of the nonvolatile memory device include a laser fuse, an antifuse, a flash memory, a ferroelectric memory (FeRAM), a magnetoresistive memory (MRAM), and a phase change memory.
<Embodiment 4>
FIG. 8 is a partial configuration diagram of a semiconductor integrated circuit device showing a fourth embodiment of the present invention. In FIG. 8, 14 is a test target circuit, 15 is a user signal pad of this apparatus, and 46 is an I / O wrap circuit. The I / O wrap circuit 46 includes an output tri-state buffer 41, an input buffer 42, and boundary scan registers 43 to 45. If the I / O wrap circuit 46 is combined with the built-in test circuit 13, a DC test can be performed. However, the user signal pads 15 to be tested are all bidirectional, and an I / O wrap circuit 46 is provided for each pad.
[0025]
Here, a DC test method using an I / O wrap circuit will be described. First, the pad 15 is charged to a high potential using the output buffer 41, and then the output buffer 41 is set to high impedance. At this time, the pad 15 becomes high impedance in a state where electric charges are charged. The potential of the pad 15 is monitored using the input buffer 42. If the pad 15 has a short circuit defect, the potential of the pad 15 can be detected in a short time. An open defect can be detected immediately because the pad 15 does not reach the desired potential. Details of the I / O wrap circuit are described in Non-Patent Document 1.
[0026]
FIG. 9 is a configuration diagram of a test flow of the semiconductor integrated circuit device partially shown in FIG. In FIG. 9, 28 is the first DC test and 29 is the second DC test. In the DC test 28, an open / short defect of the pad 15 is detected using the I / O wrap circuit 46. In the DC test 29, an open defect or a short defect of the package pin is detected. In the test flow shown in FIG. 4 when the I / O wrap circuit 46 is not mounted, a wasteful package is generated due to the defect of the pad 15, but the DC test can be performed by mounting the I / O wrap circuit 46. Therefore, the defect detection rate in the wafer test can be improved and the test cost can be reduced.
<Embodiment 5>
FIG. 10 is a configuration diagram of a semiconductor integrated circuit device showing a fifth embodiment of the present invention. In FIG. 10, 51 is a scribe area of the wafer, 52a and 52b are power supply wirings, 53 is a power switch, 54 is a switch control signal, and 55 is a power supply wiring for the circuit under test 14.
[0027]
If the power supply wirings 19a and 19b of the semiconductor chip 11 formed on the wafer are connected to each other via the power supply wirings 52a and 52b of the scribe region 51, probe pins are connected to the power supply pads 20a and 20b for each semiconductor chip 11. Since there is no need to stand, the average number of pins of the test interface can be set to 2 pins or 0 pins.
[0028]
However, if even one short defective semiconductor chip 11 is present, current concentrates on the chip, so that all the semiconductor chips 11 sharing the power source with the chip cannot be tested and are treated as defective products. Therefore, a switch 53 is provided for disconnecting the test target circuit 14 which has a large circuit scale and easily causes a short circuit failure from the power supply wiring 19a. At least when a short circuit failure caused by the circuit under test 14 occurs, the influence on other semiconductor chips can be eliminated, so that the yield is improved and the test cost can be reduced.
[0029]
11 is a cross-sectional configuration diagram of the power supply wiring shown in FIG. In FIG. 11, 56 is a via, 57 is an insulating layer, and 58 is a semiconductor substrate. The power supply wirings 19 a and 19 in the semiconductor chip 11 and the power supply wirings 52 a and 52 b in the scribe area 51 are connected via vias 56. The via 56 is a metal layer used to connect wiring between different wiring layers, and a material different from the wiring layer may be used. For this reason, even if foreign matter enters from the exposed portion of the power supply wiring 52 that appears due to the scribing of the semiconductor chip 11, it can be stopped by the via 56, leading to improved reliability. For example, copper wiring, which is now becoming mainstream, is covered with a barrier metal layer that prevents copper from diffusing into the semiconductor. However, since the barrier metal layer is also used for vias, Therefore, it can be expected to prevent foreign matter from entering.
[0030]
FIG. 12 is a configuration diagram of a jig for testing the semiconductor integrated circuit device shown in FIG. A significant difference from FIG. 6 is the arrangement of the power supply probe pins 36a and 36b. Since the semiconductor chip 11 shown in FIG. 10 has a common power supply between the chips, power can be supplied by setting probe pins on the power supply pads 20a and 20b of some of the semiconductor chips 11. In FIG. 12, since the power source is shared among the four semiconductor chips 11, the cost can be reduced compared to the probe card shown in FIG.
<Embodiment 6>
FIG. 13 is a configuration diagram of a semiconductor integrated circuit device showing a sixth embodiment of the present invention. In FIG. 13, 61 is a multichip package, and 62 is a semiconductor chip different from 11.
[0031]
When the semiconductor chip 11 having the wireless communication circuit 12 and the built-in test circuit 13 and the semiconductor chip 62 having no similar function are mixedly mounted in the multichip package 61, the semiconductor chip 62 is also wirelessly connected via the semiconductor chip 11. Can be tested. When only the built-in test circuit is mounted on the semiconductor chip 62, the test efficiency can be further increased. The advantage of not mounting the wireless communication circuit on the semiconductor chip is that the area overhead can be reduced, and the test cost can be reduced.
[0032]
The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various design changes can be made without departing from the spirit of the present invention. Of course. For example, in FIG. 5, FIG. 6, and FIG. 12, a probe card that can test four semiconductor chips at the same time has been described. However, if the area of the probe card is increased, the number of semiconductor chips that can be tested simultaneously can be increased from four. A large-area probe card covering the entire surface can be used to test wafers in a batch.
[0033]
【The invention's effect】
As is clear from the above-described embodiment, a built-in test circuit, a wireless communication circuit, and a power generation circuit are mounted in the semiconductor integrated circuit device of the present invention, and the built-in test circuit is controlled by a radio signal to perform a test. Since test I / O signals can be wireless, test interface pins can be eliminated. Further, when the power consumption of the circuit to be tested is large, it is only necessary to provide the power supply pad on the semiconductor chip, so that the number of pins can be reduced as compared with the conventional test interface.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a semiconductor integrated circuit device showing a conventional example.
FIG. 2 is a configuration diagram of a semiconductor integrated circuit device showing a first embodiment of the present invention.
FIG. 3 is a configuration diagram of a semiconductor integrated circuit device showing a second embodiment of the present invention;
4 is a configuration diagram of a test flow of the semiconductor integrated circuit device shown in FIGS. 2 and 3. FIG.
5 is a first configuration diagram of a jig for testing the semiconductor integrated circuit device shown in FIG. 3; FIG.
6 is a second block diagram of a jig for testing the semiconductor integrated circuit device shown in FIG. 3;
FIG. 7 is a configuration diagram of a semiconductor integrated circuit device showing a third embodiment of the present invention.
FIG. 8 is a partial configuration diagram of a semiconductor integrated circuit device showing a fourth embodiment of the present invention;
FIG. 9 is a configuration diagram of a test flow of the semiconductor integrated circuit device partially shown in FIG. 8;
FIG. 10 is a configuration diagram of a semiconductor integrated circuit device showing a fifth embodiment of the present invention;
11 is a cross-sectional configuration diagram of the power supply wiring shown in FIG. 10;
12 is a configuration diagram of a jig for testing the semiconductor integrated circuit device shown in FIG. 10;
FIG. 13 is a configuration diagram of a semiconductor integrated circuit device showing a sixth embodiment of the present invention;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip which shows a prior art example, 2 ... Test access port control circuit, 3 ... Pad for test interface, 11 ... Semiconductor chip which shows Example of this invention, 12 ... Wireless communication circuit, 13 ... Built-in test circuit, 14 ... Test target circuit, 15 ... User signal pad, 16a, 16b ... Radio signal, 17 ... Power generation circuit, 18 ... Storage device, 19a, 19b ... Power supply wiring, 20a, 20b ... Power supply pad, 21 ... Function test, 22, 25 ... AC test, 23 ... scribe and package process, 24, 28, 29 ... DC test, 26 ... wafer test, 27 ... package test, 31 ... wafer, 32 ... coil for antenna, 33 ... probe card, 34 ... semiconductor Chip area, 35 ... monopole antenna, 36a, 36b ... probe pin for power supply, 91 ... nonvolatile memory 41 ... Output tri-state buffer, 42 ... Input buffer, 43-45 ... Boundary scan register, 46 ... I / O wrap circuit, 51 ... Wafer scribe area, 52a, 52b ... Power supply wiring, 53 ... For power supply Switch, 54 ... Switch control signal, 55 ... Power supply wiring for circuit under test 14, 56 ... Via, 57 ... Insulating layer, 58 ... Semiconductor substrate, 61 ... Multichip package, 62 ... Semiconductor chip, VCC, VSS ... Power supply, TCK, TMS, TDI, TDO: Signals of the test access port control circuit 2

Claims (7)

Power is generated using a built-in test circuit, an antenna and wireless communication circuit that enable communication with the outside, a memory that records the test result of the ID code and the circuit under test, and a carrier wave input from the outside Power generation circuit
Power is generated by a wireless signal from the outside,
A semiconductor integrated circuit device characterized by collating an ID code sent from outside with its own ID code, receiving a command for itself, and transmitting a test result of a circuit under test to the outside. 2. The semiconductor integrated circuit device according to claim 1, further comprising a nonvolatile memory device capable of controlling reading or writing from the wireless communication circuit. 2. The semiconductor integrated circuit device according to claim 1, further comprising an I / O wrap circuit that can be controlled by the built-in test circuit for each pad of a signal that is normally used.
A semiconductor integrated circuit device, wherein each corresponding pad is driven by the I / O wrap circuit to be controlled to a high impedance, or the potential of each corresponding pad is captured. The semiconductor integrated circuit device according to claim 1.
A semiconductor integrated circuit device comprising: a power supply branch line connected to a common power supply line formed in a scribe region of the wafer when the semiconductor integrated circuit device is in a state of a chip formed on the wafer. The semiconductor integrated circuit device according to claim 4.
A power supply wiring network in the semiconductor integrated circuit device is connected to the power supply branch wiring through a via. The semiconductor integrated circuit device according to claim 5.
A semiconductor integrated circuit device comprising a switch for disconnecting the power supply wiring network and the common power supply wire in the semiconductor integrated circuit device. 7. A probe card for testing a wafer on which a plurality of semiconductor integrated circuit devices according to claim 1 are formed, comprising an antenna for performing wireless communication with the semiconductor integrated circuit device. Probe card.

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