JP2002190507A - Semiconductor wafer and manufacturing method of semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a configuration for enabling a semiconductor chip to be subjected to circuit inspection on a wafer, at the same time, to reduce ratio where a pad occupies for testings or eliminate the ratio to zero, and to prevent a semiconductor chip from being easily analyzed, after being used as a product. SOLUTION: In each of semiconductor chips 11, 12, 13, and so on separated by a scribe line 2 for arranging on the wafer, chip control circuits 21, 22, 23, and so on, signal I/O pads 31 to 39, and testing circuits 41, 42, and so on are arranged, and the signal I/O pads 31 to 39 are connected to the test circuit 41 of the mutually adjacent semiconductor chips 11, 12, and so on and to the chip control circuit 22, and are shared, thus eliminating the signal I/O pads exclusive for test, separating the semiconductor chips 11, 12, 13, and so on along the scribe line 2 for cutting, and hence electrically cutting off the test circuits 41, 42, and so on.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor wafer and a semiconductor chip.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of processes, the integration and function of integrated circuits have been rapidly advanced. As a representative, a specific system that used to be constructed by laying out a single memory, microcomputer, or analog product on a base,
The technology of system-on-chip, which is constructed by forming memories, microcomputers, analog circuits, and the like on the same silicon wafer, has rapidly advanced.

In general, as shown in FIG. 2, a plurality of multiple semiconductor integrated circuit chips 11 are arranged on a silicon wafer 1 via scribe lines 2, and each of the semiconductor integrated circuit chips 11 is formed. Are cut and separated along the scribe line 2 and packaged with a resin or the like to produce a product.

More specifically, as shown in FIG. 3, chip control circuits 21, 22, 23,... And chip control circuit signal input / output pads are provided for semiconductor integrated circuit chips 11, 12, 13,. 31-39 are arranged.

[0005] In order to predict and judge the quality of the product after the product is manufactured, it is necessary to store the memory in a wafer state before packaging.
The microcomputer and the analog circuit are individually inspected. At this time, the semiconductor integrated circuit chip 11 is provided with a test mode function different from the actual operation for the purpose of shortening the inspection time and improving the failure detection rate. , 12,13 ...
, And test circuit signal input / output pads 51 to 56... Are provided respectively.
Then, the signal input / output pads 51 to 56 for the test circuit
..Signal input by physically contacting a conductive needle with
Entry into test mode and test circuit 4
The semiconductor integrated circuit chips 11, 12, 13,... Are controlled by controlling 1, 42.

As shown in FIG. 4, there is also a wafer in which signal input / output pads 51 to 56... For test circuits are arranged in a scribe line 2.

[0007]

However, the semiconductor LS
Inspection and inspection of semiconductor LSI
Various issues in evaluation have surfaced. For example, as described above, a wafer for forming a system-on-chip requires pads and circuits dedicated to testing, and a circuit dedicated to testing decreases in area as the process becomes finer, while a pad for testing Requires a substantially constant area regardless of the miniaturization of the process so that the conductive needles can come into contact with each other, and it is assumed that this test pad affects the number of chips that can be obtained from one wafer.

In the wafer shown in FIG. 3, the test circuit signal input / output pads 51 to 56 are provided in the semiconductor integrated circuit chips 11, 12, 13,. As the process becomes finer, the semiconductor integrated circuit chips 11, 12, 1
Test circuit signal input / output pad 5 occupying 3 ...
The ratio of 1 to 56... In the wafer shown in FIG. 4, test circuit signal input / output pads 51 to 56.
Are arranged in the scribe line 2, so that the width of the scribe line 2 becomes larger than in the case where they are not arranged in the scribe line 2. Therefore,
How to reduce the ratio of test pads to semiconductor integrated circuit chips without lowering the conventional inspection efficiency will determine the area of semiconductor integrated circuit chips in the future and determine the number of semiconductor integrated circuit chips that can be taken from one wafer. .

On the other hand, magnetic cards such as credit cards and telephone cards have suffered many damages and troubles due to the ease of forgery and weak security, and the transition from magnetic cards to IC cards has been progressing rapidly. ing. However, among them, there are still many problems and issues regarding security in IC cards, and it is necessary to prevent a third party from decrypting the inside of the IC and illegally rewriting data.
Investigation of tamper-resistant technology, which is becoming more difficult, is underway.

In this regard, in the wafer shown in FIG. 3, the test circuit signal input / output pads 51 to 51 are added to the product after being cut along the scribe line 2 and packaged with resin or the like.
Since 56... Remain, it is possible for a third party to open the product and perform an electrical analysis of the semiconductor integrated circuit chips 11, 12, 13,..., Reading data inside the chip,
There is a risk that data may be illegally rewritten. This is a fatal problem in an IC card LSI for exchanging money information and the like.

The present invention has been made to solve the above-mentioned problems. Although the present invention has a configuration for inspecting a semiconductor integrated circuit chip on a wafer, the ratio of test pads can be reduced or eliminated, and the semiconductor device after commercialization is obtained. It is an object of the present invention to provide a semiconductor wafer that makes it difficult to analyze an integrated circuit chip.

[0012]

In order to solve the above problems, a semiconductor wafer according to the present invention comprises a plurality of semiconductor chips on which integrated circuits are formed, which are separated from each other by scribe lines and arranged in each semiconductor chip. In a semiconductor wafer in which a control signal line and a test signal line for an integrated circuit are arranged, the test signal line in each semiconductor chip is connected to the signal input / output of the control signal line in a semiconductor chip adjacent to the semiconductor chip. Connected to the test pad, a test signal is input / output via the signal input / output pad, and a circuit test is performed, thereby eliminating the need for a dedicated signal input / output pad for testing. The circuit inspection can be performed with the same efficiency and accuracy as before.

The test signal line is electrically cut off when each semiconductor chip is cut and separated, which makes it difficult for a third party to analyze the integrated circuit of the semiconductor chip after it is commercialized. In the method of manufacturing a semiconductor chip according to the present invention, a circuit test of each semiconductor chip is performed on the semiconductor wafer by inputting and outputting a test signal via a signal input / output pad in the semiconductor chip adjacent to the semiconductor chip. Cutting and separating the semiconductor wafer after the inspection along the scribe line, and recovering the semiconductor chips determined to be good in the inspection result. A semiconductor chip in which an integrated circuit is difficult to analyze can be obtained at a high yield.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. As shown in FIG. 1, in the semiconductor wafer according to the embodiment of the present invention, first, FIGS.
A plurality of semiconductor integrated circuit chips 11, 12, 13,... On which an integrated circuit for realizing a specific function is formed are separated and arranged by scribe lines 2, similarly to the conventional semiconductor wafer 1 described with reference to FIG. Have been. Each of the semiconductor integrated circuit chips 11, 12, 13,... Has a chip control circuit 21, 22, 2, 2 for controlling each integrated circuit.
, And chip control circuit signal input / output pads 31 to 33, 34 to 36, 37 to 39 connected to the chip control circuits 21, 22, 23,. Are arranged.

However, in this semiconductor wafer, the test circuit 4 in each of the semiconductor integrated circuit chips 11, 12, 13,...
., Respectively, pass through the scribe line 2 and pass through signal input / output pads 34 to 36, 3 for chip control circuits in the adjacent semiconductor integrated circuit chips 12, 13,.
7 to 39. In other words, within the illustrated range, the chip control circuit signal input / output pads 34 to 3
The chip control circuits 22, 23,.
And the test circuits 41, 42,...

The above semiconductor integrated circuit chips 11, 12, 1
The inspection method 3 will be described. First, the signal input / output pad 3 for the chip control circuit in the semiconductor integrated circuit chip 11
A chip control signal is input at 1-33, and the operation of the integrated circuit in the semiconductor integrated circuit chip 11 is controlled through the chip control circuit 21. At the same time, a test signal is input to the chip control circuit signal input / output pads 34 to 36 in the semiconductor integrated circuit chip 12, and the test signal is input through the test circuit 41 in the semiconductor integrated circuit chip 11. Of the operation of the integrated circuit is determined.

Next, a chip control signal is input to chip control circuit signal input / output pads 34 to 36 in the semiconductor integrated circuit chip 12, and the integrated circuit in the semiconductor integrated circuit chip 12 is input through the chip control circuit 22. Control the behavior of. At the same time, the semiconductor integrated circuit chip 1
3. Signal input / output pads 37 to 3 for the chip control circuit in 3
9, a test signal is input, and the semiconductor integrated circuit chip 1
The operation of the integrated circuit in the semiconductor integrated circuit chip 12 is determined through the test circuit 42 in the semiconductor integrated circuit chip 12.

Subsequently, the semiconductor integrated circuit chips 13 are inspected in the same manner as described above. By doing so, the integrated circuit can be inspected with the same efficiency and accuracy as before without arranging signal input / output pads dedicated to the test. Since the simultaneous inspection of the adjacent semiconductor integrated circuit chips 11, 12 or 12, 13 which share the chip control circuit signal input / output pad is not performed, there is no problem in the inspection.

All the semiconductor integrated circuit chips 11, 12,.
When the inspection of 13... Is completed, the semiconductor integrated circuit chips 11, 12, 13,... Are separated by cutting the semiconductor wafer along the scribe line 2, and the semiconductor integrated circuit chip 11 whose inspection result is determined to be good. , 12,13 ...
Is assembled for packaging.

In this way, when the semiconductor wafer is cut, the adjacent semiconductor integrated circuit chips 11, 1
The wiring made of aluminum or the like between 2, 13,..., That is, the connection wiring between the test circuit 41 and the signal input / output pads 34 to 36 for the chip control circuit, the test circuit 42 and the signal input / output pads 37 to 37 for the chip control circuit The connection wiring with 39 is cut at the same time. As a result, the packaged and commercialized semiconductor integrated circuit chip 11,
It is impossible to externally input a test signal to the test circuits 41, 42,... In 12, 13,..., And it becomes difficult to electrically analyze the semiconductor integrated circuit chips 11, 12, 13,.

In the above embodiment, the semiconductor integrated circuit chips 11, 12, 13,... Are sequentially inspected, but first, the semiconductor integrated circuit chips 11, 1,.
Inspection of 3 .... is performed, and then the semiconductor integrated circuit chip 12
It is naturally possible to inspect a plurality of semiconductor integrated circuit chips 11, 12, 13,.

[0022]

As described above, according to the present invention, each of the semiconductor chips separated and arranged by the scribe line is provided with a control signal line for controlling an integrated circuit in the chip and a control signal line for testing the integrated circuit. A test signal line and a signal input / output pad are arranged, and the signal input / output pad is connected to and shared with a control signal line and a test signal line of two adjacent semiconductor chips. As a result, it is possible to perform circuit inspection on a wafer with the same precision and efficiency as before while eliminating the need for dedicated test pads and increasing the number of chips. Circuit chips are difficult to electrically analyze by a third party.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an arrangement of semiconductor integrated circuit chips on a semiconductor wafer and a configuration thereof according to an embodiment of the present invention;

FIG. 2 is an explanatory diagram showing a conventional arrangement of semiconductor integrated circuit chips on a semiconductor wafer and an arrangement of scribe lines.

FIG. 3 is an explanatory view showing a conventional arrangement and configuration of semiconductor integrated circuit chips on a semiconductor wafer.

FIG. 4 is an explanatory diagram showing an arrangement and configuration of semiconductor integrated circuit chips on another conventional semiconductor wafer.

[Explanation of symbols]

 1 wafer 2 scribe line 11,12,13 semiconductor integrated circuit chip 21,22,23 chip control circuit 31-39 signal input / output pad for chip control circuit 41,42 test circuit

Claims (3)

[Claims] A semiconductor wafer in which a plurality of semiconductor chips on which integrated circuits are formed are separated and arranged by scribe lines, and a control signal line and a test signal line for each integrated circuit are arranged in each semiconductor chip. Connecting the test signal line in each semiconductor chip to a signal input / output pad of the control signal line in a semiconductor chip adjacent to the semiconductor chip, and transmitting a test signal through the signal input / output pad. A semiconductor wafer configured to perform input / output and circuit inspection. 2. The semiconductor wafer according to claim 1, wherein the test signal line is electrically cut off when each semiconductor chip is cut and separated. 3. The semiconductor wafer according to claim 1, wherein a circuit inspection of each semiconductor chip is performed by inputting / outputting a test signal via a signal input / output pad in the semiconductor chip adjacent to the semiconductor chip. Cutting the semiconductor wafer along the scribe line, and collecting the semiconductor chips judged to be good.