TW202413081A - 層疊體和層疊體的製造方法 - Google Patents

層疊體和層疊體的製造方法 Download PDF

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Publication number
TW202413081A
TW202413081A TW112131897A TW112131897A TW202413081A TW 202413081 A TW202413081 A TW 202413081A TW 112131897 A TW112131897 A TW 112131897A TW 112131897 A TW112131897 A TW 112131897A TW 202413081 A TW202413081 A TW 202413081A
Authority
TW
Taiwan
Prior art keywords
thermally conductive
substrate
conductive particle
containing layer
particles
Prior art date
Application number
TW112131897A
Other languages
English (en)
Chinese (zh)
Inventor
長島稔
西尾健
Original Assignee
日商迪睿合股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商迪睿合股份有限公司 filed Critical 日商迪睿合股份有限公司
Publication of TW202413081A publication Critical patent/TW202413081A/zh

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Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B3/00Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form
    • B32B3/26Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer
    • B32B3/30Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer characterised by a layer formed with recesses or projections, e.g. hollows, grooves, protuberances, ribs
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/02Physical, chemical or physicochemical properties
    • B32B7/027Thermal properties
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00Constructional details common to different types of electric apparatus
    • H05K7/20Modifications to facilitate cooling, ventilating, or heating

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Thermal Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Materials Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Laminated Bodies (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
TW112131897A 2022-09-01 2023-08-24 層疊體和層疊體的製造方法 TW202413081A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022139062A JP2024034665A (ja) 2022-09-01 2022-09-01 積層体及び積層体の製造方法
JP2022-139062 2022-09-01

Publications (1)

Publication Number Publication Date
TW202413081A true TW202413081A (zh) 2024-04-01

Family

ID=90099455

Family Applications (1)

Application Number Title Priority Date Filing Date
TW112131897A TW202413081A (zh) 2022-09-01 2023-08-24 層疊體和層疊體的製造方法

Country Status (3)

Country Link
JP (1) JP2024034665A (ja)
TW (1) TW202413081A (ja)
WO (1) WO2024048358A1 (ja)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3180622B2 (ja) * 1995-06-09 2001-06-25 三菱マテリアル株式会社 パワーモジュール用基板及びその製造方法
JP3180621B2 (ja) * 1995-06-09 2001-06-25 三菱マテリアル株式会社 パワーモジュール用基板
JP6927490B2 (ja) * 2017-05-31 2021-09-01 株式会社応用ナノ粒子研究所 放熱構造体
JPWO2021060318A1 (ja) * 2019-09-25 2021-04-01

Also Published As

Publication number Publication date
JP2024034665A (ja) 2024-03-13
WO2024048358A1 (ja) 2024-03-07

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