TW202305965A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW202305965A
TW202305965A TW111119033A TW111119033A TW202305965A TW 202305965 A TW202305965 A TW 202305965A TW 111119033 A TW111119033 A TW 111119033A TW 111119033 A TW111119033 A TW 111119033A TW 202305965 A TW202305965 A TW 202305965A
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Taiwan
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terminal
semiconductor device
pin
current
gate
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TW111119033A
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English (en)
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奥西勅子
波多俊幸
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日商瑞薩電子股份有限公司
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Publication of TW202305965A publication Critical patent/TW202305965A/zh

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Abstract

本發明之目的在於，在用於流通大電流之半導體裝置中減低導通電阻。 本發明之半導體裝置10，具有在俯視下位於閘極端子用引腳GL與克耳文端子用引腳KL之間，並且，經由複數之導線W3而與源極端子ST電性連接之源極端子用引腳SL。

Description

半導體裝置
本發明係關於一種半導體裝置，例如，關於一種適用於成為反相器之構成要件之半導體裝置之有效技術。
日本特開2008－294384號公報(專利文獻1)中，記載一種減低形成有功率MOSFET(MetalOxide Semiconductor Field Effect Transistor，金屬氧化物半導體場效電晶體)之半導體裝置的導通電阻之技術。
日本特開2009－231805號公報(專利文獻2)中，亦有記載一種減低形成有功率MOSFET之半導體裝置的導通電阻之技術。 [先前技術文獻] [專利文獻]
[專利文獻1]日本特開2008－294384號公報 [專利文獻2]日本特開2009－231805號公報
[發明所欲解決之課題]
近年探討於形成有功率半導體元件之半導體裝置流通大電流。例如，探討於使用於三相反相器之半導體裝置流通約300A之電流。關於此點，於半導體裝置流通大電流時，存在於半導體裝置之導通電阻會對半導體裝置之性能造成較大的影響。從而，期望在使用於流通大電流之半導體裝置中減低導通電阻之手段。 [解決課題之手段]
一實施態樣中之半導體裝置，具有在俯視下位於閘極端子用引腳與檢測端子用引腳之間，並且，經由複數之連接構件之中的電流端子用連接構件而與電流端子電性連接之電流端子用引腳。
又，另一實施態樣中之半導體裝置，具有在俯視下位於閘極端子用引腳與多機能端子用引腳之間，並且，經由複數之連接構件之中的電流端子用連接構件而與電流端子電性連接之電流端子用引腳。 [發明之效果]
透過一實施態樣，可提升半導體裝置之性能。
在用以說明實施態樣之全部圖式中，原則上對相同構件標示相同符號，並省略重複之說明。又，為使圖式容易理解，俯視圖亦會標示影線。
＜三相反相器電路之構成例＞ 本實施態樣中之半導體裝置，例如係使用於空調等所使用之三相感應馬達之驅動電路。具體而言，此驅動電路中包含反相器電路，此反相器電路係具有將直流功率轉換為交流功率之機能之電路。
圖1係表示包含反相器電路及三相感應馬達之馬達電路之構成之電路圖。在圖1中，馬達電路具有三相感應馬達MT及反相器電路INV。三相感應馬達MT係透過位相不同之三相電壓驅動。具體而言，三相感應馬達MT中，利用位相相差120度之稱為U相、V相、W相之三相交流電而使導體亦即旋轉體RT的周圍產生旋轉磁場。此情況下，磁場在旋轉體RT的周圍旋轉。此意味著穿過導體亦即旋轉體RT之磁通量會變化。此結果，於導體亦即旋轉體RT產生電磁感應，而使感應電流在旋轉體RT流動。並且，根據弗萊明之左手定則，感應電流在旋轉磁場中流動，意味著向旋轉體RT施加力，透過此力使旋轉體RT旋轉。如此，可知在三相感應馬達MT中，可藉由利用三相交流電使旋轉體RT旋轉。亦即，三相感應馬達MT中，須有三相交流電。故，馬達電路中，藉由利用從直流電製造交流電之反相器電路INV，向三相感應馬達供給三相交流電。
以下，說明此反相器電路INV之構成例。
如圖1所示，例如，反相器電路INV中，對應三相而設有開關元件Q1及二極體FWD。亦即，反相器電路INV中，例如，透過圖1所示之將開關元件Q1及二極體FWD反並聯之構成，實現反相器電路INV之構成要件。例如，在圖1中，第1接腳LG1之上手臂及下手臂、第2接腳LG2之上手臂及下手臂、第3接腳LG3之上手臂及下手臂，分別由將開關元件Q1及二極體FWD反並聯而成之構成要件構成。
換言之，反相器電路INV中，在正電位端子PT與三相感應馬達MT之各相(U相、V相、W相)之間反並聯開關元件Q1與二極體FWD，並且，在三相感應馬達MT之各相與負電位端子NT之間，亦反並聯開關元件Q1與二極體FWD。亦即，於各個單相設置2個開關元件Q1及2個二極體FWD，三相即設有6個開關元件Q1及6個二極體FWD。並且，於各個開關元件Q1之閘極連接閘極控制電路GCC，透過此閘極控制電路GCC，控制開關元件Q1之開關動作。在以此方式構成之反相器電路INV中，藉由以閘極控制電路GCC控制開關元件Q1之開關動作，將直流功率轉換成三相交流功率，並將此三相交流功率供給至三相感應馬達MT。
＜開關元件的種類＞ 例如，作為使用於反相器電路INV之開關元件Q1，可舉出功率MOSFET及IGBT(Insulated Gate Bipolar Transistor，絕緣閘雙極電晶體)。
＜二極體的必要性＞ 如上所述，反相器電路INV中使用開關元件Q1，在使用IGBT作為此開關元件Q1時，須設置與IGBT反並聯之二極體FWD。
單從透過開關元件Q1實現開關機能之觀點而言，會認為需要作為開關元件Q1之IGBT，但不須設置二極體FWD。關於此點，例如，如負荷為馬達之情況般，連接於反相器電路INV之負荷中包含電感時，必須設置二極體FWD。以下說明其理由。
在負荷為不包含電感之純阻抗時，因無回流之能源而不須二極體FWD。但，於負荷連接如馬達等包含電感之電路時，有負荷電流流向開啟之開關的反方向之模式。亦即，負荷中包含電感時，有能源從負荷之電感返回反相器電路INV之情況(電流逆流之情況)。
此時，IGBT單體不具流通此回流電流之機能，故須將二極體FWD與IGBT反並聯。亦即，在反相器電路INV中，如馬達控制般負荷中包含電感之情況下，關閉IGBT時，必須放出蓄積於電感之能源(1／2LI 2)。但，以IGBT單體無法流通用於放出蓄積於電感之能源之回流電流。故，為了使蓄積於此電感之電能回流，將二極體FWD與IGBT反並聯。亦即，二極體FWD具有流通回流電流而放出蓄積於電感之電能之機能。從以上內容，可知在連接於包含電感之負荷之反相器電路中，採用IGBT作為開關元件Q1時，必須將二極體FWD與IGBT反並聯設置。此二極體FWD稱為飛輪二極體。
相對於此，使用功率MOSFET作為開關元件Q1時，在原理上，不須設置與功率MOSFET反並聯之飛輪二極體。其原因在於，功率MOSFET之裝置構造中，必然會寄生形成pn接合二極體亦即本體二極體，其結果，此本體二極體作為飛輪二極體發揮機能。
但，在使用功率MOSFET作為開關元件Q1時，仍有使用順向電壓降小於pn接合二極體之肖特基二極體作為飛輪二極體之情況。
本實施態樣之技術思想可適用於使用IGBT及功率MOSFET中任一者作為開關元件Q1之構成，但在以下之說明中，舉由功率MOSFET構成開關元件Q1之情況為例。並且，飛輪二極體之有無對於說明本實施態樣之技術思想並無直接關係，故以下為求簡明，以不存在飛輪二極體之情況說明本實施態樣之技術思想。
＜反相器電路之實作佈局例＞ 圖2係表示實現反相器電路之實作佈局例之示意圖。
在圖2中，於母板形成電源配線VL、配線WL1～配線WL3及接地配線GL。向電源配線VL供給電源電位，另一方面，向接地配線GL供給接地(Ground)電位。又，配線WL1與三相感應馬達之U相連接，配線WL2與三相感應馬達之V相連接，配線WL3與三相感應馬達之W相連接。
如圖2所示，在電源配線VL與配線WL1之間連接半導體裝置SA1，另一方面，在配線WL1與接地配線GL之間連接半導體裝置SA2。亦即，半導體裝置SA1及半導體裝置SA2在電源配線VL與接地配線GL之間串聯，並構成圖1所示之反相器電路INV之第1接腳LG1。亦即，半導體裝置SA1構成第1接腳LG1之上手臂，同時，半導體裝置SA2構成第1接腳LG1之下手臂。並且，半導體裝置SA1及半導體裝置SA2，分別具有形成有作為開關元件Q1發揮機能之功率MOSFET之半導體晶片。
同樣地，在電源配線VL與配線WL2之間連接半導體裝置SA3，另一方面，在配線WL2與接地配線GL之間連接半導體裝置SA4。亦即，半導體裝置SA3及半導體裝置SA4在電源配線VL與接地配線GL之間串聯，並構成圖1所示之反相器電路INV之第2接腳LG2。亦即，半導體裝置SA3構成第2接腳LG2之上手臂，同時，半導體裝置SA4構成第2接腳LG2之下手臂。並且，半導體裝置SA3及半導體裝置SA4分別具有形成有作為開關元件Q1發揮機能之功率MOSFET之半導體晶片。
再者，在電源配線VL與配線WL3之間連接半導體裝置SA5，另一方面，在配線WL3與接地配線GL之間連接半導體裝置SA6。亦即，半導體裝置SA5及半導體裝置SA6在電源配線VL與接地配線GL之間串聯，並構成圖1所示之反相器電路INV之第3接腳LG3。亦即，半導體裝置SA5構成第3接腳LG3之上手臂，同時，半導體裝置SA6構成第3接腳LG3之下手臂。並且，半導體裝置SA5及半導體裝置SA6分別具有形成有作為開關元件Q1發揮機能之功率MOSFET之半導體晶片。
如上。藉由在形成有電源配線VL1、配線WL1～配線WL3及接地配線GL之母板上以圖2所示之方式配置6個半導體裝置SA1～半導體裝置SA6，實現對應於反相器電路之實作佈局。
＜「TO封裝」之益處＞ 本實施態樣中，例如，如圖2所示，作為具有形成了功率MOSFET之半導體晶片之半導體裝置SA之封裝構造體，採用「TO(Transistor Outline，電晶體外形)封裝」。此處，所謂「TO封裝」，定義為在俯視下僅在半導體裝置之第1邊配置複數之引腳之封裝構造體。在此點上，「TO封裝」與在俯視下不僅在半導體裝置之第1邊更在與第1邊為相反側之第2邊配置複數之引腳之「SON(Small Outline Non-Leaded，小外形無引腳)封裝」及「SOP(Small Outline Package，小外形封裝)封裝」不同，再者，亦與在半導體裝置的全部4個邊配置複數之引腳之「QFN(Quad Flat Non-leaded，方形扁平無引腳)封裝」及「QFP(Quad Flat Package，方形扁平封裝)封裝」不同。透過本實施態樣所採用之「TO封裝」，例如，如圖2所示，僅在半導體裝置SA之第1邊配置複數之引腳，故相較於上述之其他封裝，可得到使在母板上配線時之佈置更為容易之益處。亦即，藉由採用「TO封裝」，可透過精簡的佈局實現對應於反相器電路之實作佈局(參照圖2)。
本案發明人以由具有上述益處之「TO封裝」構成半導體裝置SA為前提，並從減低半導體裝置SA之導通電阻之觀點探討，結果新發現在「TO封裝」中，從實現減低導通電阻之觀點而言，仍存在以下所示之改善餘地，以下對於此點進行說明。
＜改善餘地＞ 圖3係示意表示半導體裝置SA之內部構造之圖。
在圖3中，例如，在由樹脂構成之密封體MR內部，配置有晶片襯墊DP。在此晶片襯墊DP上搭載半導體晶片CHP。於此半導體晶片CHP形成功率MOSFET。於半導體晶片CHP的表面形成與功率MOSFET之閘極電性連接之閘極端子GT，以及與功率MOSFET之源極區域電性連接之克耳文端子(Kelvin terminal)KT及源極端子ST。另一方面，雖圖3中未圖示，於半導體晶片CHP之背面形成有功率MOSFET之汲極，此汲極與晶片襯墊DP電性連接。
接著，於密封體MR之邊S1，以從密封體MR突出之方式配置複數之引腳。具體而言，複數之引腳中包含閘極端子用引腳GL、克耳文端子用引腳KL及源極端子用引腳SL。
閘極端子用引腳GL經由閘極端子用連接構件亦即導線W1而與閘極端子GT電性連接。又，克耳文端子用引腳KL經由克耳文端子用連接構件亦即導線W2而與克耳文端子KT電性連接。再者，源極端子用引腳SL以源極端子用連接構件亦即複數之導線W3與源極端子ST電性連接。
如此，構成「TO封裝」之半導體裝置SA。
此處，如圖3所示，半導體裝置SA中，在閘極端子用引腳GL旁配置克耳文端子用引腳KL。此結果，因源極端子ST與源極端子用引腳SL之相對位置錯開，連接源極端子ST與源極端子用引腳SL之導線W3形成彎曲狀。亦即，半導體裝置SA中，使用彎曲之導線W3連接源極端子ST與源極端子用引腳SL。若使用如此之彎曲之導線W3，因無法以最短距離連接源極端子ST與源極端子用引腳SL，而使導線W3之阻抗值上升。
關於此點，本案發明人探討於半導體裝置SA流通約300A之大電流，而發現在此情況下，彎曲之導線W3造成之阻抗值增加在尋求減低導通電阻上會導致無法忽視之影響。特別係彎曲之導線W3連接流通大電流之源極端子ST與源極端子用引腳SL，而在彎曲之導線W3本身流通大電流。此結果，彎曲所導致的些微之阻抗值上升仍會造成較大的電壓降及焦耳熱的產生，故若將彎曲之導線W3使用於用以流通大電流之半導體裝置SA，會成為導致無法忽視之性能降低的主因。如此，在「TO封裝」之半導體裝置SA中，從尋求以減低導通電阻作為代表之性能提升之觀點而言，仍存在改善之餘地。
故，本案發明人對於在「TO封裝」之半導體裝置SA中必須使用彎曲之導線W3之原因進行了詳細探討，並在以下說明此點。
如圖3所示，吾人認為必須使用彎曲之導線W3之原因，主要在於將克耳文端子用引腳KL配置於閘極端子用引腳GL旁，而使源極端子用引腳SL無法配置於與源極端子ST之配置位置對應之邊S1的中央部。關於此點，在說明為何須將克耳文端子用引腳KL配置於閘極端子用引腳GL旁之前，首先，說明設置克耳文端子用引腳KL之技術意義。
［設置克耳文端子用引腳之技術意義］ 圖4係示意表示不設置克耳文端子用引腳KL時之功率MOSFET100之連接構成之電路圖。如圖4所示，功率MOSFET100設於晶片襯墊DP與源極端子用引腳SL之間，「阻抗R」例如表示包含導線W3造成之阻抗值之封裝阻抗。並且，功率MOSFET100之閘極與閘極端子用引腳GL電性連接。
此處，源極端子用引腳SL與閘極端子用引腳GL之間的電壓V1例如輸入至圖1所示之閘極控制電路GCC。並且，閘極控制電路GCC基於輸入之電壓V1控制功率MOSFET100之開關動作。此時，為了穩定實施以閘極控制電路GCC對功率MOSFET100之控制，要求電壓V1與圖4所示之電壓VGS相等。
但，圖4所示之連接構成中，晶片襯墊DP與源極端子用引腳SL之間流有較大的汲極電流ID。因此，於封裝阻抗(「阻抗R」)亦因流通大電流而產生較大的電壓降。此意味著電壓V1與電壓VGS成為差異較大的值。從而，圖4所示之功率MOSFET100之連接構成中，有閘極控制電路GCC對功率MOSFET100之控制不穩定之疑慮。
相對於此，圖5係示意表示設有克耳文端子用引腳KL時之功率MOSFET100之連接構成之電路圖。圖5所示之連接構成中，除了與功率MOSFET100之電源(源極端子)連接之源極端子用引腳SL，亦設有與功率MOSFET100之電源(克耳文端子)連接之克耳文端子用引腳KL。此結果，如圖5所示，即使在晶片襯墊DP與源極端子用引腳SL之間流有較大的汲極電流ID，汲極電流ID亦不會流向克耳文端子用引腳KL。此意味著克耳文端子用引腳KL與閘極端子用引腳GL之間的電壓V1不會受到因汲極電流ID流向封裝阻抗(「阻抗R」)而產生之電壓降的影響。藉此，克耳文端子用引腳KL與閘極端子用引腳GL之間的電壓V1與電壓VGS幾乎相等。
從而，以圖5所示之功率MOSFET100之連接構成，可使閘極控制電路GCC對功率MOSFET100之控制穩定化。亦即，可說克耳文端子用引腳KL具有「不會受到汲極電流ID造成之電壓降的影響，而使與電壓VGS為幾乎相等之值的電壓V1輸入至閘極控制電路GCC，藉此使閘極控制電路GCC對功率MOSFET100之控制穩定化」之技術意義。
［將克耳文端子用引腳配置於閘極端子用引腳旁的理由］ 考慮到上述設置克耳文端子用引腳KL之技術意義，為使閘極端子用引腳GL與克耳文端子用引腳KL之間的電壓V1幾乎等於電壓VGS，期望閘極端子用引腳GL與克耳文端子用引腳KL之間的寄生阻抗小。因如此之理由，將克耳文端子用引腳KL配置於閘極端子用引腳GL旁。並且，「TO封裝」中，將克耳文端子用引腳KL配置於閘極端子用引腳GL旁之結果，造成連接源極端子ST與源極端子用引腳SL之導線W3彎曲。
關於此點，「TO封裝」以外之上述封裝中，因配置複數之引腳的邊除了第1邊亦存在其他邊，即使須將克耳文端子用引腳KL配置於閘極端子用引腳GL旁，亦可藉由例如在與第1邊不同之第2邊配置相鄰之閘極端子用引腳GL與克耳文端子用引腳KL，並在第1邊配置源極端子用引腳SL，而容易地實現不須使源極端子用引腳SL彎曲之構成。但，「TO封裝」以外之上述封裝中，母板上之配線佈置較為複雜。
相對於此，「TO封裝」中，配置複數之引腳的邊限定於邊S1，故得到母板上之配線之佈置較為容易之益處。另一方面，「TO封裝」中，因配置複數之引腳的邊限定於邊S1，若將克耳文端子用引腳KL配置於閘極端子用引腳GL旁，則無法將源極端子用引腳SL配置於與源極端子ST之配置位置對應之邊S1的中央部。因此，克耳文端子用引腳KL成為阻礙，而難以將源極端子ST與源極端子用引腳SL以最短距離之導線W3連接，而必須使導線W3彎曲。亦即，導線W3之彎曲之改善餘地，係在包含克耳文端子用引腳KL之「TO封裝」中顯現之改善餘地。
故，本實施態樣中，克服包含克耳文端子用引腳KL之「TO封裝」中顯現之導線W3之彎曲導致的改善餘地。以下，說明本實施態樣之技術思想。
＜半導體裝置之封裝構成＞ 圖6係表示本實施態樣之半導體裝置10之封裝構成之示意圖。
在圖6中，半導體裝置10係「TO封裝」，例如，具有配置於樹脂構成之密封體MR內部之晶片襯墊DP。並且，在此晶片襯墊DP上搭載半導體晶片CHP。於半導體晶片CHP形成功率MOSFET。於此半導體晶片CHP的表面，形成與功率MOSFET之閘極電性連接之閘極端子GT、與功率MOSFET之源極區域電性連接之源極端子ST、與功率MOSFET之源極區域電性連接之克耳文端子KT。此時，如圖6所示，在俯視下，源極端子ST包含位於閘極端子GT與克耳文端子KT之間之部份。另一方面，雖圖6中未圖示，於半導體晶片CHP之背面形成汲極，且此汲極與晶片襯墊DP電性連接。
源極端子ST係用以流通電流之「電流端子」，克耳文端子KT係用以檢測電壓之「檢測端子」。
接著，如圖6所示，於密封體MR的邊S1，配置從密封體MR突出之複數之引腳。換言之，沿著與密封體MR之邊S1並行之半導體晶片的第1邊，配置複數之引腳。具體而言，複數之引腳中包含閘極端子用引腳GL、克耳文端子用引腳KL及源極端子用引腳SL。閘極端子用引腳GL經由閘極端子用連接構件亦即導線(接合導線)W1而與閘極端子GT電性連接。又，克耳文端子用引腳KL經由克耳文端子用連接構件亦即導線(接合導線)W2而與克耳文端子KT電性連接。再者，源極端子用引腳SL以源極端子用連接構件亦即複數之導線(接合導線)W3而與源極端子ST電性連接。又，本實施態樣中，導線W1、導線W2及導線W3分別例如由金(Au)構成，但亦可使用由銅(Cu)構成之導線。
此處，本實施態樣中，如圖6所示，閘極端子用引腳GL不與克耳文端子用引腳KL相鄰配置，而在閘極端子用引腳GL與克耳文端子用引腳KL之間配置複數之源極端子用引腳SL。
並且，將源極端子ST與源極端子用引腳SL電性連接之複數之導線W3，分別由向與邊S1所延伸之x方向(第1方向)直交之y方向(第2方向)延伸之直線形狀構成。換言之，複數之導線W3分別由僅向與x方向直交之y方向延伸之筆直形狀構成。
又，如圖6所示，複數之導線W3分別在複數位置與源極端子ST接合。例如，各導線W3與源極端子ST在接合點P1及接合點P2連接。亦即，導線W1與閘極端子GT之接合點的數量為1個，又，導線W2與克耳文端子KT之接合點的數量為1個，相對於此，各導線W3與源極端子ST之接合點的數量為2個。亦即，藉由增加源極端子ST與複數之導線W3各自的接合位置，可減低源極端子ST與源極端子用引腳SL之間的電流路徑上之導通電阻。並且，如圖6所示，不僅經由複數之導線W3將源極端子ST與源極端子用引腳SL互相電性連接，更將各導線W3與源極端子ST在複數位置接合，藉此可在源極端子ST與源極端子用引腳SL之間流通大電流(300A)。又，本實施態樣中，如圖6所示，說明各導線W3與源極端子ST之接合點的數量為2個之情況，但亦可為2個以上。
另一方面，各導線W3與源極端子用引腳SL在接合點P3連接。亦即，各導線W3與源極端子用引腳SL之接合點的數量為1個。其原因在於，如圖6所示，源極端子用引腳SL之面積(特別指沿著導線W3所延伸之y方向之源極端子引腳SL的長度)比源極端子ST之面積(特別指沿著導線W3所延伸之y方向之源極端子ST之長度)小(短)。
如此，「TO封裝」之半導體裝置10以可流通例如300A之電流之方式構成。
＜功率MOSFET之裝置構造＞ 接著，說明形成於半導體晶片CHP之功率MOSFET之裝置構造。圖7係表示功率MOSFET之一例亦即n通道型溝槽閘極型功率MOSFET之半導體晶片CHP之重點剖面圖。
在圖7中，在由n＋型單晶矽構成之半導體基板20的表面，形成由n－型單晶矽構成之磊晶層21。半導體基板20及磊晶層21構成功率MOSFET之汲極。
於磊晶層21之一部份形成p型井22。又，於磊晶層21之表面的一部份形成氧化矽膜23，並於另一部份形成複數之溝24。磊晶層21的表面之中，被氧化矽膜23被覆之區域構成元件分離區域，另一方面，形成有溝24之區域構成元件形成區域(主動區域)。雖未圖示，溝24之平面形狀係四邊形、六邊形、八邊形等多邊形或向一方向延伸之條紋形狀。
於溝24之底部及側壁形成構成功率MOSFET之閘極絕緣膜之氧化矽膜25。又，於溝24之內部埋入構成功率MOSFET之下層閘極之多晶矽膜26A。另一方面，於氧化矽膜23之頂部形成由在與多晶矽膜26A相同步驟堆積之多晶矽膜構成之閘極抽出電極26B。下層閘極(多晶矽膜26A)與閘極抽出電極26B在未圖示之區域電性連接。
於元件形成區域之磊晶層21形成比溝24淺之p－型半導體區域27。此p－型半導體區域27稱為主體區域，且係形成有功率MOSFET之通道區域(反轉層)之區域。於p－型半導體區域27之頂部形成雜質濃度高於p－型半導體區域27之p型半導體區域28，再者，於p型半導體區域28之頂部形成n＋型半導體區域29。p型半導體區域28構成功率MOSFET之抗穿透層，另一方面，n＋型半導體區域29構成功率MOSFET之源極區域。
於形成有功率MOSFET之元件形成區域之頂部及形成有閘極抽出電極26B之元件分離區域之頂部，形成2層之氧化矽膜30及氧化矽膜31。於元件形成區域形成貫通氧化矽膜30、氧化矽膜31、p型半導體區域28及n＋型半導體區域29而到達p－型半導體區域27之連接孔32。於元件分離區域形成貫通氧化矽膜30及氧化矽膜31而到達閘極抽出電極26B之連接孔33。
於包含連接孔32及連接孔33之內部之氧化矽膜31的頂部，例如，形成由較薄的鈦鎢膜(TiW膜)及較厚的鋁膜(Al膜)之積層膜構成之源極40及閘極41。形成於元件形成區域之源極40通過連接孔32而與功率MOSFET之源極區域電性連接。於此連接孔32的底部，形成用以使源極端子ST與p－型半導體區域27歐姆接觸之p＋型半導體區域35。又，形成於元件分離區域之閘極41經由連接孔33之底部之閘極抽出電極26B，而連接於功率MOSFET之下層閘極(多晶矽膜26A)。
於源極40及閘極41之頂部，形成由氧化矽膜與氮化矽膜之積層膜構成之表面保護膜42。並且，藉由將表面保護膜42之一部份去除而使源極40露出，而形成源極端子ST，並藉由將表面保護膜之另一部份去除而使閘極41露出，而形成閘極端子GT。又，雖圖7中未圖示，亦形成克耳文端子。
如上所述，在半導體晶片CHP之主要表面上形成閘極端子GT、克耳文端子(KT)及源極端子ST。
＜實施態樣之特徵＞ 接著，說明本實施態樣之特徵點。
本實施態樣之特徵點在於，例如，如圖6所示，在俯視下，在閘極端子用引腳GL與克耳文端子用引腳KL之間配置源極端子用引腳SL。藉此，可將源極端子用引腳SL配置於與源極端子ST之配置位置對應之邊S1的中央部，故可抑制連接源極端子ST與源極端子用引腳SL之導線W3彎曲。亦即，透過本實施態樣之特徵點，可將連接源極端子ST與源極端子用引腳SL之導線W3，由向與邊S1所延伸之x方向直交之y方向延伸之直線形狀構成。換言之，透過本實施態樣之特徵點，可將複數之導線W3分別由僅向與x方向直交之y方向延伸之筆直形狀構成。
此結果，透過本實施態樣，因流通約300A之大電流之複數之導線W3不會彎曲，可抑制以導線W3之彎曲造成之導通電阻之增加及寄生電感之增加為代表之無法忽視的性能降低。亦即，透過本實施態樣，可將源極端子ST與源極端子用引腳SL以最短長度之導線W3連接，而可尋求半導體裝置10之性能提升。
此處，如在「［將克耳文端子用引腳配置於閘極端子用引腳旁的理由］」之項目中之說明，為使閘極端子用引腳GL與克耳文端子用引腳KL之間的電壓V1幾乎等於電壓VGS，期望閘極端子用引腳GL與克耳文端子用引腳KL之間的寄生阻抗小。為此，採用將克耳文端子用引腳KL配置於閘極端子用引腳GL旁之構成。
關於此點，透過閘極端子用引腳GL及克耳文端子用引腳KL檢測電壓V1之電路，並非用以流通電流之電路而係檢測電壓之檢測電路。本案發明人認為此意味著即使向檢測電路施加些許阻抗，因不會流通大電流，故電壓降對於電壓V1之檢測的影響亦較少。亦即，本案發明人得出「即使閘極端子用引腳GL與克耳文端子用引腳KL之距離較遠，對於電壓V1之檢測的影響亦不大」之判斷。相較之下，本案發明人認為在用以流通約300A之大電流之半導體裝置10中，流通大電流之導線W3彎曲造成之導通電阻及寄生電感之增加，對半導體裝置10之性能降低造成的影響較大。
考慮以上內容，本案發明人採用「在俯視下，在閘極端子用引腳GL與克耳文端子用引腳KL之間配置源極端子用引腳SL」之本實施態樣之特徵點之構成，而取代閘極端子用引腳GL與克耳文端子用引腳KL相鄰配置之構成。此結果，透過本實施態樣，可抑制以導線W3之彎曲造成之導通電阻之增加及寄生電感之增加為代表之無法忽視之性能降低，藉此，可得到尋求半導體裝置10之性能提升之顯著效果。
［端子之上位概念化］ 本實施態樣中，作為形成於半導體晶片CHP之開關元件Q1，舉功率MOSFET為例說明。此情況下，於半導體晶片CHP之表面形成閘極端子GT、克耳文端子KT及源極端子ST。
但，本實施態樣之技術思想不限於由功率MOSFET構成開關元件Q1之態樣，而亦可適用於由IGBT構成開關元件Q1之態樣。此情況下，於半導體晶片CHP之表面形成閘極端子GT、克耳文端子KT及射極端子。
並且，克耳文端子KT係用以檢測電壓之端子，檢測電壓之端子稱為「檢測端子」，故克耳文端子KT係「檢測端子」之一態樣。又，源極端子ST及射極端子係用以流通電流之端子，用以流通電流之端子稱為「電流端子」，故源極端子ST及射極端子係「電流端子」之一態樣。
再者，考慮到如後述之變形例中之說明，各導線(接合導線)W1～W3亦可替換成「帶體(ribbon)」或「夾(clip)」，「導線」、「帶體」及「夾」係連接構件之一態樣。
依據以上內容，將用語上位概念化後如下： (1)閘極端子GT (2)克耳文端子KT→「檢測端子」 (3)源極端子ST及射極端子→「電流端子」 (4)閘極端子用引腳GL (5)克耳文端子用引腳KL→「檢測端子用引腳」 (6)源極端子用引腳SL(射極端子用引腳)→「電流端子用引腳」 (7)導線W1→「閘極端子用連接構件」 (8)導線W2→「檢測端子用連接構件」 (9)導線W3(帶體、夾)→「電流端子用連接構件」
考慮到如此之用語上位概念化，本實施態樣之特徵點在於「在俯視上，在閘極端子用引腳GL與『檢測端子用引腳』之間配置『電流端子用引腳』」。藉此，可將「電流端子用引腳」配置於與「電流端子」之配置位置對應之邊的中央部，故可抑制連接「電流端子」與「電流端子用引腳」之「電流端子用連接構件」之彎曲。亦即，透過本實施態樣之特徵點，可將連接「電流端子」與「電流端子用引腳」之「電流端子用連接構件」由直線形狀構成。換言之，透過本實施態樣之特徵點，可將「電流端子用連接構件」由筆直形狀構成。
＜變形例1＞ 圖8係表示本變形例1之半導體裝置10A之示意構成之圖。
如圖8所示，本變形例1之半導體裝置10A中，對於圖6所示之半導體裝置10，將形成於半導體晶片CHP之閘極端子GT的位置與克耳文端子KT的位置調換。藉此，半導體裝置10A中，經由導線W1與閘極端子GT連接之閘極端子用引腳GL及經由導線W2與克耳文端子KT連接之克耳文端子用引腳KL之位置亦調換。
如上，若採用「在俯視下，於閘極端子用引腳GL與克耳文端子用引腳KL之間配置源極端子用引腳SL」之本實施態樣之特徵點，可實現閘極端子用引腳GL與克耳文端子用引腳KL對稱之實作構成。此結果，若採用本實施態樣之特徵點，不僅圖6所示之半導體裝置10之構成，亦可實現圖8所示之半導體裝置10A之構成。從而，本實施態樣之技術思想在可增加實作佈局之變化之點上亦為有用。
＜變形例2＞ 圖9係表示本變形例2之半導體裝置10B之示意構成之圖。
在圖9中，若採用本實施態樣之特徵點，可將源極端子用引腳SL配置於與源極端子ST之配置位置對應之邊S1的中央部。故，作為連接源極端子ST與源極端子用引腳SL之源極端子用連接構件，亦可使用由鋁(Al)形成之帶體RBN，而代替圖6所示之導線W3。
此情況下，如圖9所示，帶體RBN與源極端子ST在複數位置接合。例如，帶體RBN與源極端子ST在接合點P4及接合點P5連接。亦即，導線W1與閘極端子GT之接合點的數量為一個，又，導線W2與克耳文端子KT之接合點的數量為一個，相對於此，帶體RBN與源極端子ST之接合點的數量為2個。亦即，與上述實施態樣相同，可藉由增加源極端子ST與帶體RBN之接合位置，減低源極端子ST與源極端子用引腳SL之間之電流路徑上之導通電阻。此處，本變形例2所使用之帶體RBN的寬度比上述實施態樣所使用之各導線W1～W3的寬度更寬。並且，如圖9所示，不僅經由一個帶體RBN將源極端子ST與源極端子用引腳SL互相電性連接，亦可藉由將帶體RBN與源極端子ST在複數位置接合，而在源極端子ST與源極端子用引腳SL之間流通大電流(300A)。又，本變形例2中，如圖9所示，說明帶體RBN與源極端子ST之接合點的數量為2個之情況，但亦可為2個以上。又，帶體RBN與源極端子用引腳SL在接合點P6連接。亦即，帶體RBN與源極端子引腳SL之接合點的數量為一個。
＜變形例3＞ 圖10係表示本變形例3之半導體裝置10C之示意構成之圖。
在圖10中，若採用本實施態樣之特徵點，可將源極端子用引腳SL配置於與源極端子ST之配置位置對應之邊S1的中央部。故，作為連接源極端子ST與源極端子用引腳SL之源極端子用連接構件，除了使用圖9所示之帶體RBN，亦可如圖10所示，使用帶體RBN1及帶體RBN2代替圖6所示之導線W3。
＜變形例4＞ 圖11係表示本變形例4之半導體裝置10D之示意構成之圖。
在圖11中，若採用本實施態樣之特徵點，可將源極端子用引腳SL配置於與源極端子ST之配置位置對應之邊S1的中央部。故，作為連接源極端子ST與源極端子用引腳SL之源極端子用連接構件，亦可使用圖11所示之寬導線W4代替圖6所示之導線W3。
＜變形例5＞ 圖12係表示本變形例5之半導體裝置10E之示意構成之圖。
在圖12中，若採用本實施態樣之特徵點，可將源極端子用引腳SL配置於與源極端子ST之配置位置對應之邊S1的中央部。故，作為連接源極端子ST與源極端子用引腳SL之源極端子用連接構件，亦可使用圖12所示之夾CLP代替圖6所示之導線W3。
此情況下，如圖12所示，夾CLP與源極端子ST在1處接合。例如，夾CLP與源極端子ST在接合點P7連接。亦即，導線W1與閘極端子GT之接合點的數量為一個，又，導線W2與克耳文端子KT之接合點的數量為一個，再者，夾CLP與源極端子ST之接合點的數量亦為一個。此處，本變形例5所使用之夾CLP的寬度比上述實施態樣所使用之各導線W1～W3的寬度更寬。又，本變形例5所使用之夾CLP的厚度比上述變形例2所使用之帶體RBN的厚度更厚。故，不同於上述實施態樣及上述變形例2，即使不增加源極端子ST與夾CLP之接合位置，亦可藉由使用具備上述寬度及厚度並且由銅(Cu)形成之夾CLP，減低源極端子ST與源極端子用引腳SL之間之電流路徑上之導通電阻。又，夾CLP與源極端子用引腳SL在接合點P8連接。亦即，夾CLP與源極端子引腳SL之接合點的數量為一個。
＜實施態樣之其他益處＞ 例如，在閘極端子用引腳GL與克耳文端子用引腳KL相鄰配置之「TO封裝」中，作為不使連接源極端子ST與源極端子用引腳SL之導線W3彎曲之構成例，亦可思及將不彎曲之直線形狀之導線W3傾斜配置之構成。將此技術稱為關聯技術，並說明本實施態樣之技術思想相較於關聯技術之優越性。
圖13係示意表示實現本實施態樣之技術思想之導線W3之配置之圖。在圖13中，導線W3係由僅向y方向延伸之直線形狀構成，表示導線W3從y方向之傾斜之導線角度θ為0°。此情況下，例如，配置6條導線W3所需之半導體晶片之面積以占有面積200A表示。
接著，圖14係示意表示實現關聯技術之一例之導線W3之配置之圖。在圖14中，導線W3係由從y方向傾斜之直線形狀構成，表示導線W3從y方向之傾斜之導線角度θ為12°。此情況下，例如，配置6條導線W3所需之半導體晶片之面積以占有面積200B表示。
接著，圖15係示意表示實現關聯技術之另一例之導線W3之配置之圖。在圖15中，導線W3係由從y方向傾斜之直線形狀構成，表示導線W3從y方向之傾斜之導線角度θ為45°。此情況下，例如，配置6條導線W3所需之半導體晶片之面積以占有面積200C表示。
從圖13～圖15可知，配置6條導線W3所需之半導體晶片之面積為占有面積200A＜占有面積200B＜占有面積200C。亦即，實現本實施態樣之技術思想而將導線W3由僅向y方向延伸之直線形狀構成時，相較於實現關聯技術而將導線W3由從y方向傾斜之直線形狀構成之情況，可減小半導體晶片中之導線W3的占有面積。此意味著透過本實施態樣，在使用之導線W3的數量相同時，可相較於關聯技術縮小半導體晶片的尺寸。如此，本實施態樣之技術思想不僅可減低導通電阻，在可縮小半導體晶片之尺寸之點上亦較佳。
再者，使用其他呈現方式說明本實施態樣之技術思想相較於關聯技術之優越性。圖16係示意表示在將半導體晶片之占有面積設為面積200時，配置實現本實施態樣之技術思想之導線W3之構成之圖。如圖16所示，使用由僅向y方向延伸之直線形狀構成之導線W3時，可在面積200中配置7條導線W3。
另一方面，圖17係示意表示將半導體晶片之占有面積設為面積200時，配置實現關聯技術之導線W3之構成之圖。如圖17所示，使用由從y方向傾斜之直線形狀構成之導線W3時，在面積200中僅可配置6條導線W3。
如此，對於導線W3之形狀適用本實施態樣之技術思想時，相較於關聯技術，可增加在相同半導體晶片之面積200中可配置之導線W3的數量。此意味著在使用相同尺寸之半導體晶片時，相較於關聯技術，本實施態樣可增加在半導體晶片中可配置之導線W3之數量，其結果，可減低導通電阻。從而，從此觀點而言，本實施態樣之技術思想亦較佳。
＜應用例＞ 接著，說明本實施態樣之技術思想之應用例。具體而言，說明本實施態樣之複數之引腳之配置佈局不僅限於包含功率MOSFET之半導體裝置，亦可適用於包含雙向閘流體之半導體裝置。亦即，說明有關複數之引腳之配置佈局之設計對於包含功率MOSFET之半導體裝置與包含雙向閘流體之半導體裝置之共通化之貢獻。
圖18係雙向閘流體之電路圖。又，圖19係示意表示雙向閘流體之構造之圖。
所謂雙向閘流體係功率半導體元件的一種，其係可透過一個閘極控制雙向之電流之半導體元件。原理上，雙向閘流體如圖18及圖19所示，藉由將可控制一方向之電流之閘流體300A及閘流體300B反並聯，而控制雙向之電流。雙向閘流體可使電流雙向流通，故在交流電源之控制上被廣泛利用。雙向閘流體如圖18及圖19所示，具有主端子MT1、主端子MT2及閘極端子GT之3個端子，藉由給予閘極端子GT控制信號，不僅可從主端子MT1向主端子MT2流通電流，亦可反向從主端子MT2向主端子MT1流通電流。又，主端子MT1亦稱為第1楊極端子，主端子MT2亦稱為第2楊極端子。
圖20係示意表示包含習知的雙向閘流體之半導體裝置50A之構成之圖。如圖20所示，在成為主端子MT2之晶片襯墊DP上，搭載形成有雙向閘流體之半導體晶片CHP1。並且，在半導體晶片CHP1之表面形成主端子MT1及閘極端子GT。又，沿著密封體MR的一邊配置閘極端子用引腳GL及主端子用引腳MTL。此處，閘極端子GT與閘極端子用引腳GL以導線W1電性連接，另一方面，主端子MT1與主端子用引腳MTL以導線W5電性連接。此處，如圖20所示，複數之導線W5分別與主端子MT1在複數位置接合。例如，各導線W5與主端子MT1在接合點P1及接合點P2連接。亦即，各導線W5與主端子MT1之接合點的數量為2個。另一方面，各導線W5與主端子用引腳MTL在接合點P3連接。亦即，各導線W5與主端子用引腳MTL之接合點的數量為一個。如此，構成半導體裝置50A。
相對於此，圖21係示意表示包含習知的功率MOSFET之半導體裝置50B之構成之圖。如圖21所示，在成為汲極之晶片襯墊DP上搭載形成有功率MOSFET之半導體晶片CHP2。並且，在半導體晶片CHP2之表面形成源極端子ST及閘極端子GT。又，沿著密封體MR的一邊配置閘極端子用引腳GL及源極端子用引腳SL。此處，閘極端子GT與閘極端子用引腳GL以導線W1電性連接，另一方面，源極端子ST與源極端子用引腳SL以導線W3電性連接。此處，如圖21所示，複數之導線W3分別與源極端子ST在複數位置接合。例如，各導線W3與源極端子ST在接合點P1及接合點P2連接。亦即，各導線W3與源極端子ST之接合點的數量為2個。另一方面，各導線W3與源極端子用引腳SL在接合點P3連接。亦即，各導線W3與源極端子用引腳SL之接合點的數量為一個。如此，構成半導體裝置50B。
從圖20及圖21可知，形成有雙向閘流體之半導體晶片CHP1之閘極端子GT之配置位置與形成有功率MOSFET之半導體晶片CHP2之閘極端子GT之配置位置相反。此結果，半導體裝置50A中之閘極端子用引腳GL及主端子用引腳MTL之排列，與半導體裝置50B中之閘極端子用引腳GL及源極端子用引腳SL之排列不同。從而，在習知的半導體裝置50A及半導體裝置50B中，難以將複數之引腳之配置佈局共通化。關於此點，若適用本實施態樣之複數之引腳之配置佈局之設計點，在包含雙向閘流體之半導體裝置50A及包含功率MOSFET之半導體裝置50B中，可達到複數之引腳之配置佈局之共通化。以下說明此點。
首先，圖6中表示對於形成有功率MOSFET之半導體裝置，適用本實施態樣之複數之引腳之配置佈局之半導體裝置10。
另一方面，圖22中，表示在形成有雙向閘流體之半導體裝置中，適用本實施態樣之複數之引腳之配置佈局之半導體裝置60A。
若比較圖6與圖22雙方，可知藉由適用本實施態樣之複數之引腳之配置佈局，可實現包含功率MOSFET之半導體裝置10及包含雙向閘流體之半導體裝置60A之雙方。
特別係圖22所示之多機能端子用引腳FL在包含雙向閘流體之半導體裝置60A中，經由導線W5A而與主端子MT1電性連接。另一方面，此多機能端子用引腳FL在包含功率MOSFET之半導體裝置10中，作為經由導線W2而與克耳文端子KT連接之克耳文端子用引腳KL發揮機能。藉此，藉由適用本實施態樣之複數之引腳之配置佈局，實現包含功率MOSFET之半導體裝置10及包含雙向閘流體之半導體裝置60A之雙方。亦即，透過本實施態樣，在包含功率MOSFET之半導體裝置10及包含雙向閘流體之半導體裝置60A雙方中，藉由妥善使用多機能端子用引腳FL，可使複數之引腳之配置佈局共通化。從而，本實施態樣之技術思想，在可達到於具有相互不同之機能之半導體裝置中將複數之引腳之配置佈局共通化之點上，其汎用性亦較佳。
又，如圖22所示，導線W5A與主端子MT1在複數位置接合。例如，導線W5A與主端子MT1在接合點P1及接合點P2連接。亦即，導線W5A與主端子MT1之接合點的數量為2個。另一方面，導線W5A與多機能端子用引腳FL在接合點P3A連接。亦即，導線W5A與多機能端子用引腳FL之接合點的數量為一個。
又，如圖22所示，導線W5B與主端子MT1在複數位置接合。例如，導線W5B與主端子MT1在接合點P1及接合點P2連接。亦即，導線W5B與主端子MT1之接合點的數量為2個。另一方面，導線W5B與主端子用引腳MTL在接合點P3B連接。亦即，導線W5B與主端子用引腳MTL之接合點的數量為一個。
又，圖22中，表示在形成有雙向閘流體之半導體裝置中，適用本實施態樣之複數之引腳之配置佈局之半導體裝置60A，但不限於此，例如，亦可係以如圖23所示之半導體裝置60B之方式構成。此情況下，吾人認為因半導體裝置60B中包含之導線W5B不存在彎曲部位，故可相較於半導體裝置60A減低導通電阻。
以上，基於實施態樣具體說明了本案發明人完成之發明，但本發明不限於該實施態樣，而可在不脫離其主旨之範圍內進行各種變更，自不待言。
10:半導體裝置 10A:半導體裝置 10B:半導體裝置 10C:半導體裝置 10D:半導體裝置 10E:半導體裝置 100:功率MOSFET 20:半導體基板 21:磊晶層 22:p型井 23:氧化矽膜 24:溝 25:氧化矽膜 26A:多晶矽膜 26B:閘極抽出電極 27:p-型半導體區域 28:p型半導體區域 29:n+型半導體區域 30:氧化矽膜 31:氧化矽膜 32:連接孔 33:連接孔 35:p+型半導體區域 40:源極 41:閘極 42:表面保護膜 50A:半導體裝置 50B:半導體裝置 60A:半導體裝置 60B:半導體裝置 200:面積 200A:占有面積 200B:占有面積 200C:占有面積 300A:閘流體 300B:閘流體 LG1:第1接腳 LG2:第2接腳 LG3:第3接腳 PT:正電位端子 NT:負電位端子 GCC:閘極控制電路 INV:反相器電路 Q1:開關元件 FWD:二極體 RT:旋轉體 MT:三相感應馬達 MT1:主端子 MT2:主端子 MTL:主端子用引腳 VL:電源配線 SA1:半導體裝置 SA2:半導體裝置 SA3:半導體裝置 SA4:半導體裝置 SA5:半導體裝置 SA6:半導體裝置 S1:邊 WL1:配線 WL2:配線 WL3:配線 MR:密封體 V1:電壓 VGS:電壓 ID:汲極電流 CHP:半導體晶片 CHP1:半導體晶片 CHP2:半導體晶片 CLP:夾 DP:晶片襯墊 KT:克耳文端子(檢測端子) KL:克耳文端子用引腳(檢測端子用引腳) FL:多機能端子用引腳 GT:閘極端子 GL:閘極端子用引腳 P1:接合點 P2:接合點 P3:接合點 P3A:接合點 P3B:接合點 P4:接合點 P5:接合點 P6:接合點 P7:接合點 P8:接合點 RBN:帶體 RBN1:帶體 RBN2:帶體 ST:源極端子(電流端子) SL:源極端子用引腳(電流端子用引腳) W1:導線(接合導線) W2:導線(接合導線) W3:導線(接合導線) W4:導線(接合導線) W5:導線(接合導線) W5A:導線(接合導線) W5B:導線(接合導線)
圖1係表示包含反相器電路及三相感應馬達之電路構成之電路圖。 圖2係表示實現反相器電路之實作佈局例之示意圖。 圖3係示意表示半導體裝置之內部構造之圖。 圖4係示意表示不設置克耳文端子用引腳時之功率MOSFET之連接構成之電路圖。 圖5係示意表示有設置克耳文端子用引腳時之功率MOSFET之連接構成之電路圖。 圖6係表示實施態樣中之半導體裝置之封裝構成之示意圖。 圖7係表示功率MOSFET之一例之n通道型溝槽閘極型功率MOSFET之半導體晶片之重點剖面圖。 圖8係表示變形例1中之半導體裝置之示意構成之圖。 圖9係表示變形例2中之半導體裝置之示意構成之圖。 圖10係表示變形例3中之半導體裝置之示意構成之圖。 圖11係表示變形例4中之半導體裝置之示意構成之圖。 圖12係表示變形例5中之半導體裝置之示意構成之圖。 圖13係示意表示實現實施態樣之技術思想之導線配置之圖。 圖14係示意表示實現相關技術之一例之導線配置之圖。 圖15係示意表示實現相關技術之另一例之導線配置之圖。 圖16係示意表示在將半導體晶片之占有面積設為既定面積時，實現本實施態樣之技術思想之導線配置之構成之圖。 圖17係示意表示實現相關技術之導線配置之構成之圖。 圖18係雙向閘流體之電路圖。 圖19係示意表示雙向閘流體之構造之圖。 圖20係表示包含習知的雙向閘流體之半導體裝置之構成之圖。 圖21係表示包含習知的功率MOSFET之半導體裝置之構成之圖。 圖22係表示在形成有雙向閘流體之半導體裝置中，適用實施態樣之複數之引腳之配置佈局之半導體裝置之一例之圖。 圖23係表示在形成有雙向閘流體之半導體裝置中，適用實施態樣之複數之引腳之配置佈局之半導體裝置之另一例之圖。
10:半導體裝置
CHP:半導體晶片
DP:晶片襯墊
MR:密封體
KT:克耳文端子(檢測端子)
KL:克耳文端子用引腳(檢測端子用引腳)
FL:多機能端子用引腳
GT:閘極端子
GL:閘極端子用引腳
P1:接合點
P2:接合點
P3:接合點
S1:邊
ST:源極端子(電流端子)
SL:源極端子用引腳(電流端子用引腳)
W1:導線(接合導線)
W2:導線(接合導線)
W3:導線(接合導線)

Claims (20)

  1. 一種半導體裝置，包含： 晶片襯墊； 半導體晶片，搭載於該晶片襯墊上； 複數之引腳，在俯視下沿著該半導體晶片之第1邊配置；以及， 複數之連接構件，將該半導體晶片與該複數之引腳電性連接； 該半導體晶片包含： 閘極端子； 檢測端子；以及， 電流端子，包含位於該閘極端子與該檢測端子之間的部份； 該複數之引腳包含： 閘極端子用引腳，經由該複數之連接構件之中的閘極端子用連接構件，而與該閘極端子電性連接； 檢測端子用引腳，經由該複數之連接構件之中的檢測端子用連接構件，而與該檢測端子電性連接；以及， 電流端子用引腳，在俯視下位於該閘極端子用引腳與該檢測端子用引腳之間，並且，經由該複數之連接構件之中的電流端子用連接構件，而與該電流端子電性連接。
  2. 如請求項1所述之半導體裝置，其中， 該電流端子用連接構件，由向與該第1邊所延伸之第1方向直交之第2方向延伸之直線形狀構成。
  3. 如請求項1所述之半導體裝置，其中， 該電流端子用連接構件，由僅向與該第1邊所延伸之第1方向直交之第2方向延伸之形狀構成。
  4. 如請求項3所述之半導體裝置，其中， 該電流端子用連接構件，係由金(Au)或銅(Cu)形成之導線。
  5. 如請求項4所述之半導體裝置，其中， 該閘極端子用連接構件與該閘極端子之接合點的數量為一個； 該檢測端子用連接構件與該檢測端子之接合點的數量為一個； 該電流端子用連接構件與該電流端子之接合點的數量為2個以上。
  6. 如請求項5所述之半導體裝置，其中， 該電流端子用連接構件的數量，比該閘極端子用連接構件及該檢測端子用連接構件各自的數量多。
  7. 如請求項6所述之半導體裝置，其中， 該半導體裝置以可流通300A之電流之方式構成。
  8. 如請求項1所述之半導體裝置，其中， 該電流端子用連接構件係由鋁(Al)形成之帶體。
  9. 如請求項8所述之半導體裝置，其中， 該閘極端子用連接構件與該閘極端子之接合點的數量為一個； 該檢測端子用連接構件與該檢測端子之接合點的數量為一個； 該電流端子用連接構件與該電流端子之接合點的數量為2個以上。
  10. 如請求項9所述之半導體裝置，其中， 該半導體裝置以可流通300A之電流之方式構成。
  11. 如請求項1所述之半導體裝置，其中， 該電流端子用連接構件係由銅(Cu)形成之夾。
  12. 如請求項11所述之半導體裝置，其中， 該閘極端子用連接構件與該閘極端子之接合點的數量為一個； 該檢測端子用連接構件與該檢測端子之接合點的數量為一個； 該電流端子用連接構件與該電流端子之接合點的數量為一個。
  13. 如請求項12所述之半導體裝置，其中， 該半導體裝置以可流通300A之電流之方式構成。
  14. 如請求項1所述之半導體裝置，其中， 於該半導體晶片形成有功率MOSFET； 該檢測端子係克耳文端子； 該電流端子係源極端子。
  15. 如請求項14所述之半導體裝置，其中， 該半導體晶片包含： 主要表面；以及， 背面，與該主要表面為相反側； 與該功率MOSFET之閘極電性連接之該閘極端子，形成於該主要表面上； 與該功率MOSFET之源極區域電性連接之該檢測端子，形成於該主要表面上； 與該功率MOSFET之該源極區域電性連接之該電流端子，形成於該主要表面上； 該功率MOSFET之汲極形成於該背面。
  16. 如請求項1所述之半導體裝置，其中， 該複數之引腳僅配置於該第1邊一側。
  17. 一種半導體裝置，包含： 晶片襯墊； 半導體晶片，搭載於該晶片襯墊上； 複數之引腳，在俯視下沿著該半導體晶片之第1邊配置；以及， 複數之連接構件，將該半導體晶片與該複數之引腳電性連接； 該半導體晶片包含： 閘極端子； 多機能端子，可用於複數之機能；以及， 電流端子，包含位於該閘極端子與該多機能端子之間的部份； 該複數之引腳包含： 閘極端子用引腳，經由該複數之連接構件之中的閘極端子用連接構件，而與該閘極端子電性連接； 多機能端子用引腳，經由該複數之連接構件之中的多機能端子用連接構件，而與該多機能端子電性連接；以及， 電流端子用引腳，在俯視下位於該閘極端子用引腳與該多機能端子用引腳之間，並且，經由該複數之連接構件之中的電流端子用連接構件，而與該電流端子電性連接； 於該半導體晶片形成有功率MOSFET之情況，該多機能端子係克耳文端子； 於該半導體晶片形成有雙向閘流體之情況，該多機能端子係該電流端子，並且，該多機能端子用引腳係具有與該電流端子用引腳相同之機能之其他引腳。
  18. 如請求項17所述之半導體裝置，其中， 該電流端子用連接構件，由向與該第1邊所延伸之第1方向直交之第2方向延伸之直線形狀構成。
  19. 如請求項12所述之半導體裝置，其中， 該電流端子用連接構件，由僅向與該第1邊所延伸之第1方向直交之第2方向延伸之形狀構成。
  20. 如請求項19所述之半導體裝置，其中， 該半導體裝置以可流通300A之電流之方式構成。
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