TW202230535A - 半導體結構及其形成方法 - Google Patents

半導體結構及其形成方法 Download PDF

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TW202230535A
TW202230535A TW110115445A TW110115445A TW202230535A TW 202230535 A TW202230535 A TW 202230535A TW 110115445 A TW110115445 A TW 110115445A TW 110115445 A TW110115445 A TW 110115445A TW 202230535 A TW202230535 A TW 202230535A
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layer
capping layer
conductive
diffusion barrier
dielectric layer
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TW110115445A
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English (en)
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TWI783464B (zh
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蔡承祐
楊固峰
邱文智
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台灣積體電路製造股份有限公司
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Abstract

一種方法包括在晶圓的內連線結構之上形成導電接墊，在導電接墊之上形成覆蓋層，形成介電層以覆蓋覆蓋層，以及蝕刻介電層以在介電層中形成開口。覆蓋層暴露於開口。然後在晶圓上執行濕式清潔製程。在濕式清潔製程期間，覆蓋層的頂面暴露於用於進行濕式清潔製程的化學溶液中。所述方法更包括沉積導電擴散阻擋件，導電擴散阻檔件延伸至開口中，以及在導電擴散阻擋件之上沉積導電材料。

Description

積體電路裝置的接合結構及其形成方法
在三維（3D）封裝的形成中，封裝組件（例如，裝置晶粒、封裝件、中介物、封裝基底、或其類似物）相互接合。接合可以藉由直接金屬-對-金屬接合、混合接合或類似方式來執行。接合結構在封裝組件中形成，並用於將封裝組件接合在一起。
以下公開提供用於實施所提供主題的不同特徵的許多不同實施例或實例。以下闡述組件及佈置的具體實例以簡化本公開。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵進而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外，本公開可能在各種實例中重複使用參照編號及/或字母。此種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「位於…之下（underlying）」、「位於…下方（below）」、「下部的（lower）」、「位於…之上（overlying）」、「上部的（upper）」等空間相對性用語來闡述圖中所例示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向（旋轉90度或處於其他定向），且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
提供用於接合封裝組件的接合結構及其形成方法。根據本公開的一些實施例，接合結構的形成包括在金屬接墊之上形成覆蓋層（capping layer）。在覆蓋層之上形成介電層，以及在介電層中形成開口以暴露出覆蓋層。可執行濕式預清潔製程來清潔開口。在濕式預清潔製程之後，可選擇性地執行濺鍍製程，以移除覆蓋層的暴露部分。接著可形成導電特徵，所述導電特徵延伸到介電層中並與覆蓋層接觸。由於金屬接墊不會暴露於濕式預清潔製程所用的化學藥品中，因此可以避免金屬接墊的電化學腐蝕（galvanic corrosion）。本文討論的實施例是為了提供示例以使得能夠進行或使用本公開的主題，並且本領域技術人員將容易地理解可在不同實施例的預期範圍內進行修飾。在各種視圖和示例中，相似的參照數字用於表示相似的元件。儘管可將方法實施例討論為以特定順序執行，但其他方法實施例可以任何邏輯順序執行。
圖1示出封裝2。封裝2包括彼此接合的封裝組件10及封裝組件10’。在一些實施例中，封裝組件10和10’又可被稱為半導體結構。封裝組件10及封裝組件10’中的每一者可為裝置晶粒、封裝、矽中介物（具有矽作為基底）、有機中介物、封裝基底、印刷電路板或其類似物。根據一些實施例，封裝組件10包括基底4。基底4可為半導體基底，例如矽基底。在基底4之上形成有內連線結構6，內連線結構6可包括介電層及位於介電層中的金屬線以及通孔（未示出）。金屬接墊32形成在內連線結構6之上，並且可電耦合到封裝組件10中的裝置（例如晶體管、電阻器、電容器等）。覆蓋層34形成在金屬接墊32之上，且可由緻密的（dense）導電層或緻密的介電層形成。可在金屬接墊32下方形成擴散阻擋件30。電性連接件9形成在金屬接墊32上且電性（及/或訊號地）連接到金屬接墊32。電性連接件9可包括金屬柱或金屬通孔。電性連接件9可能與覆蓋層34的頂面接觸（因此停在覆蓋層34上），或者可穿過覆蓋層34，而使得電性連接件9的側壁與覆蓋層34的側壁接觸。
根據一些實施例，封裝組件10’包括基底4’。基底4’可為半導體基底，例如矽基底。形成有穿過基底4’的穿孔18（也稱為基底穿孔或矽穿孔）。在基底4’上形成有內連線結構6’，內連線結構6’可包括介電層以及位於介電層中的金屬線和通孔（未示出）。金屬接墊32’形成在內連線結構6’上，且可電耦合到封裝組件10’中的裝置（例如晶體管、電阻器、電容器等）。覆蓋層34’形成在金屬接墊32’之上。電性連接件9’形成在金屬接墊32’上並與金屬接墊32’電性連接（訊號連接）。電性連接件9’可著陸於（land）覆蓋層34’或穿過覆蓋層34’。亦形成有擴散阻擋件30’。根據一些實施例，封裝組件10藉由混合接合而接合到封裝組件10’，其中電性連接件9藉由直接金屬-對-金屬接合（藉由相互擴散）而接合到電性連接件9’，且表面介電層14藉由熔融接合（fusion bonding）而接合到介電層14’。根據替代實施例，電性連接件9和電性連接件9’凸出於相應的介電層14和介電層14’之外，且採用直接金屬-對-金屬接合，其中底部填充劑（未示出）填充封裝組件10和封裝組件10’之間的間隙。根據又一選擇實施例，焊料區（未示出）可設置在電性連接件9和電性連接件9’之間且將電性連接件9和電性連接件9’接合在一起。
封裝組件10’可被包封在包封體15中。包封體15可包括模製化合物，模製底部填充劑，環氧樹脂，樹脂及/或其類似物。扇出型內連結構20形成在封裝組件10和10’之上並電耦合至封裝組件10和10’。在封裝2的頂面處形成有例如焊料區22的電性連接件。
圖2A至圖2I示出根據本公開一些實施例的在形成封裝組件中的接合結構的中間階段的剖視圖。相應的製程也以示意圖方式反映在圖15中所示的製程流程中。對應所形成的封裝組件可為圖1中的封裝組件10（或封裝組件10’）。
參照圖2A，提供封裝組件10的初始結構，其包括基底4（可為半導體基底）及位於基底4之上的內連線結構6。根據封裝組件10是裝置晶粒的一些實施例，可在半導體基底4的頂面處存在例如晶體管等積體電路裝置（未示出）。根據替代實施例，舉例來說，當封裝組件10是中介物、封裝基底或其類似物時，則沒有形成主動裝置及/或被動裝置。內連線結構6可包括介電層3以及金屬線和通孔5（示意性地示出，而沒有示出其細節）。根據一些示例實施例，介電層3可包括低介電常數（k）介電層，且每個金屬線/通孔5可包括銅以及位於銅之下的擴散阻擋件，且可使用鑲嵌製程來形成。
進一步參照圖2A，沉積（毯覆的）擴散阻擋層30、（毯覆的）金屬接墊層32以及（毯覆的）覆蓋層34。如圖15所示，相應的製程在製程流程200中被示為製程202。根據一些實施例，毯覆的擴散阻擋層30由選自鈦、氮化鈦、鉭、氮化鉭、或其類似物或其多層的材料形成或包括上述材料。金屬接墊層32沉積在擴散阻擋層30之上，並且可包括銅、鋁、鎳、鎢或其類似物。根據一些實施例，金屬接墊層32包括AlCu。沉積方法可包括物理氣相沉積（Physical Vapor Deposition，PVD）、化學氣相沉積（Chemical Vapor Deposition，CVD）或類似製程。
覆蓋層34沉積在金屬接墊層32之上。根據一些實施例，覆蓋層34由導電材料形成或包括導電材料，導電材料可包括鈦、氮化鈦、鉭、氮化鉭或其類似物或其多層。根據替代實施例，覆蓋層34由介電材料形成，介電材料可包括氧化鋁（例如Al 2O 3）、氮化鋁、氮化矽或其類似物或其組合或其多層。當由介電材料形成時，覆蓋層34可為薄的，例如，其厚度小於約100 Å，且其厚度可在約30 Å至約100 Å的範圍內。覆蓋層34的形成可包括原子層沉積（Atomic Layer Deposition，ALD）、CVD、電漿增強CVD（PECVD）或類似製程。
在覆蓋層34之上形成底抗反射層（Bottom Anti-Reflective Coating，BARC）36，且在底抗反射層36之上形成圖案化的蝕刻罩幕38。相應的製程在如圖15所示的製程流程200中被示為製程204。根據一些實施例，圖案化的蝕刻罩幕38包括光阻，所述光阻藉由曝光製程和顯影製程被圖案化。蝕刻罩幕38也可為單層罩幕或可包括多個層，例如三層。根據一些實施例，底抗反射層36可由SiON、SiOC、SiOCN或其類似物或其多層形成、或可包括上述材料。根據替代實施例，底抗反射層36可由有機材料（例如交聯的光阻）形成。底抗反射層36用於減少曝光製程期間的反射，所述曝光製程用於圖案化上覆的蝕刻罩幕38。
在隨後的製程中，圖案化的蝕刻罩幕38用於蝕刻下方的底抗反射層36、覆蓋層34、金屬接墊層32以及擴散阻擋層30。被圖案化的金屬接墊層32和擴散阻擋層30分別被稱為金屬接墊32和擴散阻擋件30。所得的結構在圖2B中出。相應的製程在如圖15所示的製程流程200中被示為製程206。所得的擴散阻擋件30和金屬接墊32電連接到下方的金屬線和通孔。接著，將蝕刻罩幕38移除，且所得的結構在圖2C中示出。相應的製程在如圖15所示的製程流程200中被示為製程208。根據一些實施例，將底抗反射層36自覆蓋層34移除。相應的製程在如圖15所示的製程流程200中被示為製程210。根據替代實施例，將底抗反射層36保留而未從覆蓋層34移除，並作為附加的覆蓋層留在最終結構中。因此，將底抗反射層36（根據這些實施例也稱為介電覆蓋層36）示為虛線，以表示其在隨後的結構中可能存在或可能不存在。相應的製程210在圖15中也以虛線示出。在整個說明書中，當特徵或製程顯示為虛線時，表示相應的特徵或製程可能存在或可能不存在（可能採用或可能不採用）。
參照圖2D，沉積側壁覆蓋層40。相應的製程在如圖15所示的製程流程200中被示為製程212。根據替代實施例，不形成側壁覆蓋層40。根據一些實施例，側壁覆蓋層40由選自用於形成覆蓋層34的同一組候選材料中的材料形成。因此，側壁覆蓋層40可以是導電層或介電層。舉例來說，可使用鈦、氮化鈦、鉭、氮化鉭、氧化鋁、氮化鋁、氮化矽等。覆蓋層34和側壁覆蓋層40的材料可彼此相同或不同，且各自可為選自上述候選材料的任何材料。側壁覆蓋層40的沉積可以包括共形沉積製程，例如ALD、CVD或其類似製程。
如圖2E所示，接著圖案化側壁覆蓋層40。相應的製程在如圖15所示的製程流程200中也被顯示為製程212。根據一些實施例，側壁覆蓋層40的圖案化藉由無需蝕刻罩幕的非等向性蝕刻製程來進行。因此，留下了側壁覆蓋層40的豎直部分，而移除了側壁覆蓋層40的水平部分。根據替代實施例，使用圖案化的蝕刻罩幕41來執行側壁覆蓋層40的圖案化。因此，側壁覆蓋層40的一些水平部分，例如區42（圖2G）所示的部分可以保留而不被移除，且留在最終結構中。隨後形成的蝕刻停止層44將位於側壁覆蓋層40的垂直部分和水平部分（如果未移除的話）二者之上並與側壁覆蓋層40的垂直部分和水平部分（如果未移除的話）二者接觸。
根據替代實施例，跳過了圖2D和2E中所示的製程，並且未形成側壁覆蓋層40。結果，隨後形成的蝕刻停止層44與擴散阻擋件30的側壁、金屬接墊32的側壁及覆蓋層34的側壁物理接觸。相應的製程在圖15中的製程流程200中也以虛線示出，以指示可執行或可不執行該製程。
圖2F示出蝕刻停止層44、介電層46、蝕刻停止層48及介電層50的形成。相應的製程在如圖15所示的製程流程200中被示為製程214。根據一些實施例，在介電層46的沉積之後，執行例如化學機械拋光（CMP）製程或機械研磨製程等平坦化製程。因此，有時將介電層46稱為平坦化層。根據一些實施例，介電層46和介電層50由氧化矽形成，但亦可使用其他材料，例如未摻雜的矽酸鹽玻璃、氮化矽、氧氮化矽、碳氧化矽（silicon oxycarbide）、碳氮氧化矽（silicon oxy-carbo-nitride）或其類似物。蝕刻停止層44和48可由氮化矽形成，但也可使用其他材料，例如氧化鋁、氮化鋁、氮氧化矽、碳氧化矽、碳氮氧化矽或其類似物。
根據其中未形成側壁覆蓋層40或者側壁覆蓋層40的頂部水平部分被移除的替代實施例，蝕刻停止層44可與底抗反射層36的頂面物理接觸，或者與覆蓋層34的頂面物理接觸（如果已移除底抗反射層36）。
圖2G示出開口52的形成。開口52包括底部開口52A和頂部開口52B。可藉由多個蝕刻製程來執行所述形成製程，其中採用兩個蝕刻罩幕來產生用於開口52A和52B的不同圖案。可藉由乾式蝕刻製程來執行所述蝕刻製程，其中根據蝕刻停止層44、介電層46、蝕刻停止層48和介電層50的材料來選擇蝕刻氣體。相應的製程在如圖15所示的製程流程200被示為製程216。根據替代實施例，藉由乾式蝕刻來蝕刻介電層50、蝕刻停止層48、介電層46，並且藉由濕式蝕刻製程來對蝕刻停止層44進行蝕刻。
根據一些實施例，在形成開口52之後，可執行預清潔製程。根據一些實施例，藉由濕式清潔製程來執行預清潔製程，所述濕式清潔製程使用包含胺基（amine-based）材料的化學溶液，例如_XM-426（JTBaker®），DuPont™EKC265™，ACT970（Versum材料）或其類似物。相應的製程在如圖15所示的製程流程200中被示為製程218。
根據一些實施例，覆蓋層34的頂面被暴露於預清潔化學溶液，且覆蓋層34不被蝕刻。因此覆蓋層34保護下方的金屬接墊32免受電化學腐蝕，電化學腐蝕可能會導致金屬接墊32中產生凹坑（孔）。凹坑可能會損壞隨後形成的擴散阻擋件54（圖2I）的完整性，這是由於擴散阻擋件54可能會掉入凹坑中，且因此擴散阻擋件54也將具有孔洞。
圖2H示出電性連接件9的形成，電性連接件9包括擴散阻擋件54和金屬材料56。所述形成製程可包括鑲嵌製程。根據一些實施例，擴散阻擋件54由鈦、氮化鈦、鉭、氮化鉭或其類似物等材料形成或者包括上述材料。金屬材料56可包括銅或銅合金。根據一些實施例，使用PVD來形成擴散阻擋件54，且在鍍覆製程中來鍍覆金屬材料56，鍍覆製程可包括電化學鍍覆製程、無電鍍覆製程或其類似製程。在鍍覆金屬材料56之後，可執行例如CMP製程或機械研磨製程等平坦化製程，以移除擴散阻擋件54的多餘部分，從而得到電性連接件9。
根據一些實施例，如圖2H所示，電性連接件9的底面與覆蓋層34的頂面接觸。當覆蓋層34由導電材料（如上所述，例如Ti、TiN、Ta或TaN）或介電材料（例如Al 2O 3或AlN）形成時，可以實現這些實施例。在覆蓋層34由介電材料形成的實施例中，覆蓋層34是薄的，使得載流子可以隧穿覆蓋層34，以實現電性連接件9與金屬接墊32之間的訊號及/或電性互連。舉例來說，覆蓋層34的厚度可小於約100Å，且可在約30Å至約100Å的範圍內。
根據替代實施例，在形成電性連接件9之前移除覆蓋層34的位於開口52A正下方的部分，使得電性連接件9穿過覆蓋層34並與金屬接墊32物理接觸。圖2I中所示的虛線區58表示覆蓋層34的被移除的部分以及電性連接件9的穿過覆蓋層34的部分。相應的製程在圖15所示的製程流程200中被示為製程220。根據一些實施例，為防止金屬接墊32的電化學腐蝕，可在預清潔的腔室中藉由物理離子轟擊移除覆蓋層34。用於移除覆蓋層34的部分的製程氣體可以包括Ar、Kr、Xe或其類似物，且可添加其他氣體，例如H 2、N 2、或其類似物。因此，移除區58中的部分覆蓋層34包括對覆蓋層34執行濺鍍。相應的製程220在圖15製程流程200中也以虛線示出，以指示可以執行或可以不執行該製程。在移除區58中的部分覆蓋層34後，將沉積擴散阻擋件54。覆蓋層34的濺鍍和擴散阻擋件54的沉積可以是在同一生產工具中原位執行的（但也可在同一生產工具的同一真空環境中在不同的製程腔室中執行），兩者之間沒有真空中斷（vacuum break）。舉例來說，PVD工具可包含脫氣（Degas）腔室、預清潔腔室、阻擋件腔室和Cu晶種腔室。製程順序可以是脫氣、預清潔、阻擋件的形成以及Cu晶種的形成。PVD工具中不會發生真空中斷，亦即，在從脫氣、預清潔、阻擋件的形成以及Cu晶種的形成的整個製程中，晶圓一直處在真空環境中。根據一些實施例，可在預清潔腔室中進行覆蓋層34的移除。然後，可將晶圓轉移到阻擋件腔室以沉積擴散阻擋件54。相應的製程在圖15所示的製程流程200中被示為製程222。根據這些實施例，儘管金屬接墊32被暴露出，但由於金屬接墊32沒有暴露在預清潔化學品（或其他濕式溶液）中，因此金屬接墊32不會遭受電化學腐蝕。因此擴散阻擋件54可保持其完整性。
接下來，例如在鍍覆製程中沉積金屬材料56，所述鍍覆製程可為電化學鍍覆製程。然後執行例如CMP製程或機械研磨製程等平坦化製程，以移除擴散阻擋件54和金屬材料56的多餘部分，並因此形成電性連接件9。相應的製程在如圖15所示的製程流程200中被示為製程224。
隨後的圖示出根據本公開的替代實施例的形成接合結構時的中間階段的剖視圖。除非另有說明，否則這些實施例中的組件的材料和形成製程與圖1及圖2A至2I所示的先前實施例中的以相似參考符號表示的相似組件的材料和形成製程基本相同。因此，有關於後續圖中所示的組件的形式製程和材料的細節可在先前實施例的討論中找到。在隨後的圖式所示的每個實施例中，與前面的實施例類似，覆蓋層34以及可能的底抗反射層36保護金屬接墊32免受電化學腐蝕。如果電性連接件9穿過覆蓋層34，則可在濕式預清潔製程之後移除覆蓋層34的一部分，且可在與用於沉積擴散阻擋件54的相同生產工具中（可能在同一真空環境中的不同製程腔室中）原位移除覆蓋層34的所述一部分。
圖3A至圖3F示出根據一些實施例的接合結構的形成。這些實施例類似於圖2A至圖2I所示的實施例，不同之處在於：圖案化的側壁覆蓋層40仍包括與金屬接墊32交疊的水平部分。參照圖3A，在內連線結構6之上形成擴散阻擋件30、金屬接墊32、覆蓋層34及可選的底抗反射層36。覆蓋層34可為介電層，也可為導電層。所述形成製程與圖2A至圖2C所示的製程相同，於此不再贅述。在圖3B中，沉積側壁覆蓋層40。接著，形成蝕刻罩幕41，以覆蓋側壁覆蓋層40的位於金屬接墊32的側壁及頂部上的一些部分。然後蝕刻側壁覆蓋層40，接著移除蝕刻罩幕41。所得的結構在圖3C中示出。如圖3D所示，接著沉積蝕刻停止層44、介電層46、蝕刻停止層48及介電層50。之後，如圖3E所示，形成開口52A和開口52B。
接著可執行濕式預清潔製程，並且在濕式預清潔製程期間，覆蓋層34保護金屬接墊32免於暴露於在濕式預清潔製程中所使用的化學溶液中。因此金屬接墊32不會由於電化學腐蝕而被腐蝕。然後可將封裝組件10放置在其中形成真空的製程腔室中。接著例如藉由濺鍍移除覆蓋層34的裸露部分。
如圖3F所示，然後形成電性連接件9。根據一些實施例，例如在與移除覆蓋層34的同一生產工具中（可能在同一真空環境中的不同製程腔室中）藉由PVD原位沉積擴散阻擋件54。接著，例如藉由鍍覆沉積金屬材料56。然後執行例如CMP製程或機械研磨製程等平坦化製程，以移除多餘的材料，並形成如圖3F所示的電性結構。
圖4A至圖4F示出根據一些實施例的接合結構的形成。這些實施例類似於圖3A至圖3F所示的實施例，不同之處在於：電性連接件9沒有穿過側壁覆蓋層40以接觸金屬接墊32，而是著陸（land）於側壁覆蓋層40的頂面上。參照圖4A，在內連線結構6之上形成擴散阻擋件30、金屬接墊32、覆蓋層34及底抗反射層36（可保留或可不保留）。覆蓋層34可為介電層，也可為導電層。所述形成製程與圖2A至圖2C所示的製程相同，於此不再贅述。在圖4B中，沉積側壁覆蓋層40，其可由導電材料形成。接著，形成蝕刻罩幕41，以覆蓋側壁覆蓋層40的位於金屬接墊32的側壁及頂面上的一些部分。然後蝕刻側壁覆蓋層40，之後移除蝕刻罩幕41。所得的結構在圖4C中示出。如圖4D所示，然後沉積蝕刻停止層44、介電層46、蝕刻停止層48及介電層50。接著，如圖4E所示，形成開口52A和開口52B。開口52A穿過蝕刻停止層44，且側壁覆蓋層40的頂面暴露出來。然後形成電性連接件9，如圖4F所示。電性連接件9具有與側壁覆蓋層40的頂部水平部分的頂面接觸的底面。根據這些實施例，覆蓋層34（如果是電介質）、底抗反射層36（如果存在）和側壁覆蓋層40中的介電層的總厚度可小於約100Å，並且可在約30Å至約100Å的範圍內。
圖5A至圖5F示出根據一些實施例的接合結構的形成。這些實施例類似於圖3A至圖3F所示的實施例，不同之處在於：側壁覆蓋層40進一步延伸至內連線結構6的頂面上。參照圖5A，在內連線結構6之上形成擴散阻擋件30、金屬接墊32、覆蓋層34以及可選的底抗反射層36。覆蓋層34可為介電層，也可為導電層。所述形成製程與圖2A至圖2C所示的製程相同，於此不再贅述。在圖5B中，沉積側壁覆蓋層40，其可由導電材料或介電材料形成。在所示的區中可不對側壁覆蓋層40執行圖案化，且因此，側壁覆蓋層40在內連線結構6的頂面上延伸。然後，如圖5C所示，沉積蝕刻停止層44、介電層46、蝕刻停止層48及介電層50。接著，如圖5D所示，形成開口52A和開口52B。開口52A穿過側壁覆蓋層40和底抗反射層36，且覆蓋層34的頂面暴露出來。可執行濕式預清潔製程，在此期間覆蓋層34暴露於在濕式預清潔製程中所使用的化學溶液中。因此保護了金屬接墊32免受電化學腐蝕。然後例如在濺鍍製程中移除覆蓋層34的裸露部分。如圖5E所示，然後形成電性連接件9。電性連接件9的底面與金屬接墊32的頂面接觸。覆蓋層34的暴露部分的移除以及擴散阻擋件54的沉積也可原位執行。
圖6A、圖6B、圖6C、圖7A、圖7B、圖7C、圖8及圖9示出根據替代實施例的接合結構的剖視圖。這些實施例與先前的實施例類似，且包括在金屬接墊32的頂部延伸的側壁覆蓋層40。
圖6A、圖6B及圖6C示出根據一些實施例的接合結構。在圖6A所示的實施例中，在覆蓋層34的頂部沒有保留底抗反射層。電性連接件9穿過側壁覆蓋層40（可為導電層或介電層），並著陸在覆蓋層34（也可為導電層或介電層）的頂面上。側壁覆蓋層40和覆蓋層34的可用材料已經參照圖2A至圖2I所示的實施例討論了，於此不再贅述。在圖6B中所示的實施例中，在覆蓋層34的頂部沒有保留底抗反射層。側壁覆蓋層40可為導電層或介電層，且電性連接件9著陸於導電的側壁覆蓋層40的頂部部分上，而不會穿過側壁覆蓋層40的頂部部分。在圖6C所示的實施例中，在覆蓋層34的頂部上沒有保留底抗反射層。側壁覆蓋層40可為介電層，且電性連接件9穿過側壁覆蓋層40以著陸於覆蓋層34上。覆蓋層34可為介電層或導電層。此外，根據一些實施例，側壁覆蓋層40可由介電材料（例如Al 2O 3）形成，相應的側壁覆蓋層40的厚度可大於約600Å，以確保相鄰金屬接墊32之間的電隔離。
圖6A、圖6B和圖6C示出一些實施例，其中在覆蓋層34的頂部上沒有保留底抗反射層。與圖6A、圖6B和圖6C所述的實施例不同，圖7A、圖7B和圖7C示出一些實施例，其中底抗反射層36保留下來，而沒有被移除。在圖7A所示的實施例中，底抗反射層36保留在覆蓋層34的頂部上，且電性連接件9穿過底抗反射層36和側壁覆蓋層40二者的頂部。側壁覆蓋層40可為導電層或介電層。電性連接件9著陸於覆蓋層34的頂面上，覆蓋層34可為導電層或介電層。在圖7B中所示的實施例中，底抗反射層36保留在覆蓋層34的頂部上。覆蓋層34和側壁覆蓋層40中的每一者都可為導電層或介電層，且電性連接件9著陸於導電的側壁覆蓋層40上，而不會穿過導電的側壁覆蓋層40。在圖7C中所示的實施例中，側壁覆蓋層40是介電層，並在內連線結構6的頂面上延伸。電性連接件9穿過側壁覆蓋層40和底抗反射層36並著陸在覆蓋層34上，覆蓋層34可為介電層或導電層。此外，側壁覆蓋層40的厚度可大於約600Å，以確保相鄰金屬接墊32之間的電隔離。
圖8和圖9示出根據替代實施例的接合結構的剖視圖。這些實施例與先前的實施例類似，且包括側壁覆蓋層40，所述側壁覆蓋層具有位於金屬接墊32的側壁上的豎直部分，但不包括位於覆蓋層34的頂部上的水平部分。覆蓋層34和側壁覆蓋層40中的每一者可由介電材料（例如氧化鋁）或導電材料（例如Ti、TiN、Ta、TaN或其類似物）形成。在圖8中，沒有底抗反射層保留在覆蓋層34的頂部上，覆蓋層34可為介電層或導電層。在圖9所示的實施例中，底抗反射層36保留在覆蓋層34的頂部。電性連接件9穿過底抗反射層36，且著陸於覆蓋層34的頂面上。
圖10A至10H示出根據一些實施例的接合結構的形成。這些實施例類似於圖2A至圖2I所示的實施例，不同之處在於：未形成側壁覆蓋層，且電性連接件9穿過覆蓋層34和底抗反射層36（如果有形成，其為可選的），且著陸在金屬接墊32的頂面上。圖10A、圖10B、圖10C及圖10D與圖2A、圖2B及圖2C基本相同，於此不再贅述。覆蓋層34可為介電層或導電層。在圖10E中，形成蝕刻停止層44、介電層46、蝕刻停止層48和介電層50。接著，如圖10F所示，形成開口52A和開口52B。在開口52A和52B的形成中，開口52A穿過底抗反射層36（如果有的話）。可使用乾式蝕刻製程來形成開口52A和52B。覆蓋層34的頂面暴露於開口52A。然後可執行濕式預清潔製程，在此期間覆蓋層34暴露於在濕式預清潔製程中所使用的化學溶液中。因此保護了金屬接墊32免受電化學腐蝕。
接著，例如在製程腔室中藉由濺鍍來移除覆蓋層34的暴露部分，從而暴露出金屬接墊32。如圖10G和10H所示，然後形成電性連接件9。圖10G示出擴散阻擋件54的沉積和金屬材料56的形成。根據一些實施例，在與用於移除覆蓋層34暴露部分的相同生產工具中（可能在同一真空環境中的不同製程腔室中）原位沉積擴散阻擋件54，且在覆蓋層34的移除（例如，濺鍍）和擴散阻擋件54的沉積之間可沒有真空中斷。然後例如藉由鍍覆沉積導電材料56。然後執行平坦化製程（例如CMP製程或機械研磨製程）以形成電性連接件9，如圖10H所示。電性連接件9的底面與金屬接墊32的頂面接觸。
圖11示出根據一些實施例的接合結構。這些實施例與圖10H所示的實施例類似，不同之處在於：側壁覆蓋層40形成在擴散阻擋件30的側壁、金屬接墊32的側壁和覆蓋層34的側壁上。底抗反射層36可存在或不存在，如果底抗反射層存在，則側壁覆蓋層40會進一步延伸至底抗反射層36的側壁上。類似於圖10H中的實施例，電性連接件9穿過覆蓋層34並著陸在金屬接墊32上。同樣，覆蓋層34在相應的預清潔製程中保護金屬接墊32免受電化學腐蝕。
圖12A至圖12F-1示出根據一些實施例的接合結構的形成。這些實施例與圖2A至2I中所示的實施例類似，不同之處在於：不形成側壁覆蓋層，且電性連接件9不是使用鑲嵌製程形成，而是使用鍍覆罩幕形成。圖12A至圖12D所示的製程與圖2A至圖2C所示的製程相同，於此不再贅述。在圖12E中，形成介電層44，介電層44可被形成為共形層（conformal layer）。接著，如圖12F-1所示，形成電性連接件9。根據一些實施例，電性連接件9的形成包括對介電層44和底抗反射層36（如果存在）執行蝕刻，以形成開口，並執行濕式預清潔製程。在濕式預清潔製程期間，覆蓋層34保護下方的金屬接墊32免受電化學腐蝕。接著例如藉由濺鍍在製程腔室中移除覆蓋層34的暴露部分。然後在與用於移除覆蓋層34的相同生產工具中（可能在同一真空環境中的不同製程腔室中）（例如使用PVD）原位形成金屬晶種層，且在覆蓋層34的移除和金屬晶種層的形成之間沒有真空中斷。金屬晶種層可包括擴散阻擋件54（例如，由鈦形成），以及在擴散阻擋件之上的銅層。然後形成圖案化的鍍覆罩幕，其具有在鍍覆罩幕中形成的開口，所述開口與在先前的製程中形成的開口交疊。然後鍍覆導電材料56，之後移除鍍覆罩幕，並蝕刻之前被鍍覆罩幕覆蓋的金屬晶種層。金屬晶種層和鍍覆材料的剩餘部分為電性連接件9。在圖12F-1所示的實施例中，電性連接件9具有與金屬接墊32的頂面接觸的底面。
圖12F-2示出根據替代實施例的接合結構。這些實施例類似於圖12F-1中所示的實施例，不同之處在於：電性連接件9著陸在覆蓋層34的頂面上，覆蓋層34可由導電材料或介電材料形成。圖12F-2所示的結構的形成也可包括圖12A至圖12E中所示的製程。
圖13A至13D示出根據一些實施例的接合結構的形成。這些實施例類似於圖2A至2I中所示的實施例，不同之處在於：側壁覆蓋層40不是藉由沉積形成，而是藉由氧化金屬接墊32的側壁表面部分以形成金屬氧化物而形成。參照圖13A，形成擴散阻擋件30、金屬接墊32和覆蓋層34。覆蓋層34可為導電層或介電層。接下來，如圖13B所示，執行氧化製程，以使得金屬接墊32的側壁表面部分被氧化，以形成側壁覆蓋層40。取決於金屬接墊32的材料，側壁覆蓋層40可由氧化銅、氧化鋁或其組合及/或其他金屬的氧化物形成。儘管未具體示出，但擴散阻擋件30的側壁部分和覆蓋層34的側壁部分也可包括在氧化製程中形成的相應材料的氧化物。
在圖13C中，沉積蝕刻停止層44、介電層46、蝕刻停止層48和介電層50，之後執行多個蝕刻製程，以形成開口52A和開口52B。開口52A穿過蝕刻停止層44，且覆蓋層34的頂面暴露出來。然後可執行濕式預清潔製程，在此期間覆蓋層34可保護金屬接墊32免受電化學腐蝕。接下來，如圖13D所示，在鑲嵌製程中形成電性連接件9。
圖13D-1示出圖13D中的區60的放大圖。由於在氧化過程中將氧添加到金屬接墊32中以形成側壁覆蓋層40，因此側壁覆蓋層40的體積大於金屬接墊32的被氧化部分。因此，側壁覆蓋層40橫向地擴展，且包括與上覆的覆蓋層34交疊的第一部分以及延伸超出覆蓋層34的邊緣的第二部分。由於蝕刻停止層44是共形地形成，因此側壁覆蓋層40和覆蓋層34的拓撲結構（topology）會反映在蝕刻停止層44的側壁上。蝕刻停止層44的側壁具有階梯45，所述階梯45所在的水平高度接近側壁覆蓋層34的頂面的水平高度。
圖13E示出根據一些實施例的接合結構的剖視圖。這些實施例與圖13D中的實施例類似，不同之處在於：底抗反射層36保留下來，且電性連接件9穿過覆蓋層34以接觸金屬接墊32。類似地，移除覆蓋層34的一部分以暴露金屬接墊32可在濕式預清潔製程之後執行，所述濕式預清潔製程在暴露出覆蓋層34之後執行，且移除覆蓋層34的一部分可與擴散阻擋件54的沉積原位執行。
圖13F示出根據一些實施例的接合結構的剖視圖。這些實施例與圖13D中的實施例類似，不同之處在於：底抗反射層36保留下來，且電性連接件9穿過底抗反射層36以接觸覆蓋層34。
圖14A至圖14E示出根據一些實施例的接合結構的形成。這些實施例與圖2A至圖2I所示的實施例類似，不同之處在於：未形成如圖2I所示的側壁覆蓋層40和覆蓋層34，而是底抗反射層36充當覆蓋層，以保護金屬接墊32免受電化學腐蝕。圖14A示出初始結構的形成。所述形成製程與圖2A至圖2C中所示的製程相似，不同之處在於：未形成如圖2C中所示的覆蓋層34。底抗反射層36保留下來，而未被移除。在圖14B中，沉積蝕刻停止層44、介電層46、蝕刻停止層48和介電層50。接著，如圖14C所示，形成開口52A和開口52B。開口52A和開口52B的形成可藉由乾式蝕刻製程來執行。然後可以執行濕式預清潔製程，其中底抗反射層36的頂面暴露於在濕式預清潔製程中所使用的化學物質。底抗反射層36保護下方的金屬接墊32免受電化學腐蝕。接著，如圖14D所示，在製程腔室中例如藉由濺鍍移除底抗反射層36的暴露部分，所述製程腔室與用於沉積擴散阻擋件54的腔室處在相同的環境中。然後例如藉由PVD沉積擴散阻擋件54。所述沉積可與底抗反射層36的濺鍍原位執行，在底抗反射層36的濺鍍和擴散阻擋件54的沉積之間沒有真空中斷。然後，例如藉由鍍覆形成金屬材料56，之後進行CMP製程以形成電性連接件9。所得的結構在圖14E中示出。
本公開的實施例具有一些有利的特徵。藉由形成覆蓋層而避免了金屬接墊的電化學腐蝕。所述覆蓋層可未被蝕刻穿以用於電性連接件的形成，或者可藉由濺鍍製程而被蝕刻穿，所述濺鍍製程與隨後的擴散阻檔件的形成原位執行。
根據本公開的一些實施例，一種方法包括：在晶圓的內連線結構之上形成導電接墊；在導電接墊之上形成覆蓋層；形成介電層，以覆蓋覆蓋層；蝕刻介電層，以在介電層中形成開口，其中覆蓋層被開口暴露出；在晶圓上執行濕式清潔製程，其中在濕式清潔製程期間，覆蓋層的頂面暴露於用於執行濕式清潔製程的化學溶液中；沉積導電擴散阻檔件，所述導電擴散阻檔件延伸到開口中；以及在導電擴散阻擋件之上沉積導電材料。在實施例中，所述方法更包括藉由濺鍍移除覆蓋層的一部分，使得開口進一步延伸到覆蓋層中，以暴露出導電接墊，其中濺鍍覆蓋層和沈積導電擴散阻擋件是在同一生產工具中（可在同一真空環境中的不同製程腔室中）原位執行的。在實施例中，在濺鍍覆蓋層和沈積導電擴散阻擋件時不會在其間發生真空中斷。在實施例中，形成覆蓋層包括沉積介電材料。在實施例中，形成覆蓋層包括沉積附加導電材料。在實施例中，導電擴散阻擋件被沉積為具有與覆蓋層的頂面接觸的底面。在實施例中，導電擴散阻擋件被沉積為穿過覆蓋層。在實施例中，所述方法更包括在覆蓋層之上形成抗反射層，其中介電層沉積在抗反射層之上，且其中導電擴散阻擋件穿過抗反射層。在實施例中，所述方法更包括在覆蓋層之上形成抗反射層；以及在沉積介電層之前，移除抗反射層。在實施例中，所述方法更包括：在形成介電層之前，沉積側壁覆蓋層，所述側壁覆蓋層在導電接墊側壁和覆蓋層的側壁上延伸。在實施例中，沉積側壁覆蓋層包括沉積介電材料。在實施例中，沉積側壁覆蓋層包括沉積附加導電材料。在實施例中，所述方法更包括在形成介電層之前，執行氧化製程以氧化導電接墊的側壁表面部分，並在導電接墊的側壁上形成金屬氧化物。
根據本公開中的一些實施例，一種結構包括：導電接墊；覆蓋層，位於導電接墊之上並與導電接墊接觸；介電層，在導電接墊和覆蓋層的第一頂面和側壁上延伸；以及導電通孔，延伸到介電層中，其中通孔與導電接墊的一部分交疊，且通孔訊號耦合到導電接墊。在實施例中，覆蓋層包括介電材料。在實施例中，覆蓋層包括導電層。在實施例中，導電通孔的底面與覆蓋層的第二頂面接觸，以形成介面。在實施例中，導電通孔延伸至覆蓋層中以接觸導電接墊的第一頂面。
根據本公開的一些實施例，一種結構包括：半導體基底；內連線結構，位於半導體基底之上；擴散阻檔件，位於內連線結構之上；金屬接墊，位於擴散阻擋件之上；覆蓋層，位於金屬接墊之上並與金屬接墊接觸；第一介電層，位於覆蓋層之上並與覆蓋層接觸，其中擴散阻擋件的邊緣、金屬接墊的邊緣、覆蓋層的邊緣和第一介電層的邊緣實質上豎直地對齊；第二介電層，在擴散阻擋件、金屬接墊、覆蓋層和第一介電層的第一頂面和側壁上延伸；導電通孔，延伸至第二介電層和第一介電層中，以接觸覆蓋層。在實施例中，導電通孔與覆蓋層的第二頂面接觸。
前文概述若干實施例的特徵以使得本領域的技術人員可更好地理解本發明的各方面。本領域的技術人員應瞭解，其可易於使用本發明作為設計或修改用於進行本文中所介紹的實施例的相同目的和/或獲得相同優點的其它製程和結構的基礎。本領域的技術人員還應認識到，此類等效構造並不脫離本發明的精神和範圍，且其可在不脫離本發明的精神和範圍的情況下在本文中進行各種改變、替代以及更改。
2:封裝 3、14、14’、46、50:介電層 4、4’:基底 5:金屬線和通孔 6、6’:內連線結構 9、9’:電性連接件 10、10’:封裝組件 15:包封體 18:穿孔 20:扇出型內連結構 22:焊料區 30:擴散阻擋件（擴散阻擋層） 30’、54:擴散阻擋件 32:金屬接墊（金屬接墊層） 32’:金屬接墊 34、34’:覆蓋層 36:底抗反射層 38、41:蝕刻罩幕 40:側壁覆蓋層 42、58、60:區 44:蝕刻停止層（介電層） 48:蝕刻停止層 45:階梯 52、52A、52B:開口 56:金屬材料 200:製程流程 202、204、206、208、210、212、214、216、218、220、222、224:製程
結合附圖閱讀以下詳細說明，會最佳地理解本公開的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為使論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1示出根據一些實施例的具有接合結構的封裝的剖視圖。 圖2A至圖2I示出根據一些實施例的形成接合結構的中間階段的剖視圖。 圖3A至圖3F示出根據一些實施例的形成接合結構的中間階段的剖視圖。 圖4A至圖4F示出根據一些實施例的形成接合結構的中間階段的剖視圖。 圖5A至圖5E示出根據一些實施例的形成接合結構的中間階段的剖視圖。 圖6A至圖6C示出根據一些實施例的一些接合結構的剖視圖。 圖7A至圖7C示出根據一些實施例的一些接合結構的剖視圖。 圖8至圖9示出根據一些實施例的一些接合結構的剖視圖。 圖10A至10H示出根據一些實施例的形成接合結構的中間階段的剖視圖。 圖11示出根據一些實施例的接合結構的剖視圖。 圖12A至圖12E、圖12F-1及圖12F-2示出根據一些實施例的形成接合結構的中間階段的剖視圖。 圖13A至圖13D示出根據一些實施例的形成接合結構的中間階段的剖視圖。 圖13D-1示出根據一些實施例的圖13D中的接合結構的一部分的放大圖。 圖13E及圖13F示出根據一些實施例的一些接合結構的剖視圖。 圖14A至圖14E示出根據一些實施例的形成接合結構的中間階段的剖視圖。 圖15示出根據一些實施例的用於形成封裝組件的接合結構的製程流程。
200:製程流程
202、204、206、208、210、212、214、216、218、220、222、224:製程

Claims (20)

  1. 一種方法，包括： 在晶圓的內連線結構之上形成導電接墊； 在所述導電接墊之上形成覆蓋層； 形成介電層，以覆蓋所述覆蓋層； 蝕刻所述介電層，以在所述介電層中形成開口，其中所述覆蓋層被所述開口暴露出； 在所述晶圓上執行濕式清潔製程，其中在所述濕式清潔製程期間，所述覆蓋層的頂面暴露於用於執行所述濕式清潔製程的化學溶液中； 沉積導電擴散阻擋件，所述導電擴散阻檔件延伸至所述開口中；以及 在所述導電擴散阻擋件之上沉積導電材料。
  2. 如請求項1所述的方法，更包括：藉由濺鍍移除所述覆蓋層的一部分，其中所述開口進一步延伸至所述覆蓋層中，以暴露出所述導電接墊，其中濺鍍所述覆蓋層以及沉積所述導電擴散阻檔件是在相同的製程真空環境中原位執行的。
  3. 如請求項2所述的方法，其中在執行濺鍍所述覆蓋層和沉積所述導電擴散阻擋件之間沒有真空中斷。
  4. 如請求項1所述的方法，其中形成所述覆蓋層包括沉積介電材料。
  5. 如請求項1所述的方法，其中形成所述覆蓋層包括沉積附加導電材料。
  6. 如請求項1所述的方法，其中所述導電擴散阻擋件被沉積為具有與所述覆蓋層的所述頂面接觸的底面。
  7. 如請求項1所述的方法，其中所述導電擴散阻擋件被沉積為穿過所述覆蓋層。
  8. 如請求項1所述的方法，更包括：在所述覆蓋層之上形成抗反射層，其中所述介電層沉積在所述抗反射層之上，且其中所述導電擴散阻擋件穿過所述抗反射層。
  9. 如請求項1所述的方法，更包括： 在所述覆蓋層之上形成抗反射層；以及 在沉積所述介電層之前，移除所述抗反射層。
  10. 如請求項1所述的方法，更包括：在形成所述介電層之前，沉積側壁覆蓋層，所述側壁覆蓋層在所述導電接墊的側壁和所述覆蓋層的側壁上延伸。
  11. 如請求項10所述的方法，其中沉積所述側壁覆蓋層包括沉積介電材料。
  12. 如請求項10所述的方法，其中沉積所述側壁覆蓋層包括沉積附加導電材料。
  13. 如請求項1所述的方法，更包括：在形成所述介電層之前，執行氧化製程，以氧化所述導電接墊的側壁表面部分，並在所述導電接墊的側壁上形成金屬氧化物。
  14. 一種結構，包括： 導電接墊； 覆蓋層，位於所述導電接墊之上並與所述導電接墊接觸； 介電層，在所述導電接墊和所述覆蓋層的第一頂面和側壁上延伸；以及 導電通孔，延伸至所述介電層中，其中所述導電通孔與所述導電接墊的一部分交疊，且其中所述導電通孔訊號耦合到所述導電接墊。
  15. 如請求項14所述的結構，其中所述覆蓋層包括介電材料。
  16. 如請求項14所述的結構，其中所述覆蓋層包括導電層。
  17. 如請求項14所述的結構，其中所述導電通孔的底面與所述覆蓋層的第二頂面接觸，以形成介面。
  18. 如請求項14所述的結構，其中所述導電通孔延伸至所述覆蓋層中，以接觸所述導電接墊的所述第一頂面。
  19. 一種結構，包括： 半導體基底； 內連線結構，位於所述半導體基底之上； 擴散阻擋件，位於所述內連線結構之上； 金屬接墊，位於所述擴散阻擋件之上； 覆蓋層，位於所述金屬接墊之上並與所述金屬接墊接觸； 第一介電層，位於所述覆蓋層之上並與所述覆蓋層接觸，其中所述擴散阻擋件的邊緣、所述金屬接墊的邊緣、所述覆蓋層的邊緣和所述第一介電層的邊緣實質上豎直地對齊； 第二介電層，在所述擴散阻擋件、所述金屬接墊、所述覆蓋層和所述第一介電層的第一頂面和側壁上延伸；以及 導電通孔，延伸至所述第二介電層和所述第一介電層中，以與所述覆蓋層接觸。
  20. 如請求項19所述的結構，其中所述導電通孔接觸所述覆蓋層的第二頂面。
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