CN113113350A - 半导体装置的形成方法 - Google Patents
半导体装置的形成方法 Download PDFInfo
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- CN113113350A CN113113350A CN202011457562.0A CN202011457562A CN113113350A CN 113113350 A CN113113350 A CN 113113350A CN 202011457562 A CN202011457562 A CN 202011457562A CN 113113350 A CN113113350 A CN 113113350A
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- layer
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- dielectric layer
- insulator
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Abstract
提供半导体装置与其形成方法。一实施例的方法包括接收基板,其含有下侧接点结构;沉积第一介电层于基板上;形成金属‑绝缘层‑金属结构于第一介电层上;沉积第二介电层于金属‑绝缘层‑金属结构上;进行第一蚀刻工艺,形成开口延伸穿过第二介电层以露出金属‑绝缘层‑金属结构;进行第二蚀刻工艺,延伸开口穿过金属‑绝缘层‑金属结构,以露出第一介电层;以及进行第三蚀刻工艺,进一步延伸开口穿过第一介电层,以露出下侧接点结构。第一蚀刻工艺与第三蚀刻工艺的蚀刻剂包括氟,而第二蚀刻工艺的蚀刻剂不含氟。
Description
技术领域
本发明实施例关于半导体装置的形成方法,更特别关于以多个蚀刻工艺形成开口穿过金属-绝缘层-金属结构(以及上方与下方的介电层)。
背景技术
半导体集成电路产业已经历快速成长。集成电路材料与设计的技术进展,使每一代的集成电路比前一代具有更小且更复杂的电路。然而这些进展亦增加制造与处理集成电路的复杂度。为了实现这些进展,制造与处理集成电路的方法亦需类似发展。在集成电路演进中,功能密度(比如单位芯片面积的内连线装置数目)通常随着几何尺寸(比如采用的制作工艺所能产生的最小构件)缩小而增加。
随着集成电路装置的几何尺寸缩小,需要大表面积的被动装置将移动到后段工艺的结构。金属-绝缘层-金属电容器为此类的被动装置的例子。一般的金属-绝缘层-金属电容器包括多个导体板层,其彼此之间以多个绝缘层绝缘。接点通孔穿过金属-绝缘层-金属电容器。一些接点通孔穿过导体板层而不电性耦接至任何的导体板层,且一些接点通孔电性耦接至一组导体板层,而一些接点通孔电性耦接至不同组的导体板层。形成接点通孔的方法需形成开口穿过金属-绝缘层-金属电容器,以及金属-绝缘层-金属电容器之上与之下的介电层。在蚀刻导体板层时可产生一或多种非挥发的绝缘性副产物,造成阶状结构并增加接点电阻。因此虽然现有的金属-绝缘层-金属结构与其制作方法适用于其发展目的,但无法完全符合所有方面的需求。
发明内容
本发明一实施例关于半导体装置的形成方法。方法包括接收基板,其包括下侧接点结构;沉积第一介电层于基板上;形成金属-绝缘层-金属结构于第一介电层上;沉积第二介电层于金属-绝缘层-金属结构上;进行第一蚀刻工艺,形成开口延伸穿过第二介电层以露出金属-绝缘层-金属结构;进行第二蚀刻工艺,延伸开口穿过金属-绝缘层-金属结构,以露出第一介电层;以及进行第三蚀刻工艺,进一步延伸开口穿过第一介电层,以露出下侧接点结构。第一蚀刻工艺包括第一蚀刻剂,第二蚀刻工艺包括第二蚀刻剂,且第三蚀刻工艺包括第三蚀刻剂。第一蚀刻剂与第三蚀刻剂包括氟,且第二蚀刻剂不含氟。
本发明另一实施例关于半导体装置的形成方法。方法包括接收含有下侧接点结构的基板;沉积氮化硅层于基板上,包括形成氮化硅层于下侧接点结构上;沉积第一氧化硅层于氮化硅层上;形成导体板层于第一氧化硅层上;沉积第二氧化硅层于导体板层上;进行第一蚀刻工艺,形成开口穿过第二氧化硅层,以露出导体板层;进行第二蚀刻工艺,延伸开口穿过导体板层,以露出第一氧化硅层;以及进行第三蚀刻工艺,进一步延伸开口穿过第一氧化硅层与氮化硅层,以露出下侧接点结构。第一蚀刻工艺包括第一蚀刻剂,第二蚀刻工艺包括第二蚀刻剂,且第三蚀刻工艺包括第三蚀刻剂。第一蚀刻剂与第三蚀刻剂含氟,而第二蚀刻剂基本上为氯气。
本发明另一实施例关于半导体装置。半导体装置包括下侧接点结构;第一介电层,位于下侧接点结构上;金属-绝缘层-金属结构,位于第一介电层上;第二介电层,位于金属-绝缘层-金属结构上;以及接点通孔,延伸穿过第一介电层、金属-绝缘层-金属结构、与第二介电层,以直接接触下侧接点结构。接点通孔包括穿过第一介电层的厚度的第一部分、穿过金属-绝缘层-金属结构的厚度的第二部分、以及穿过第二介电层的厚度的第三部分。第一部分以第一角度呈实质上线性的锥形。第二部分以第二角度呈实质上线性的锥形,且第二角度大于第一角度。第三部分以第三角度呈实质上线性的锥形,且第三角度小于第二角度。
附图说明
图1是本发明实施例中,制作半导体装置的方法的流程图。
图2至图20是本发明实施例中,半导体装置于多种制作阶段的剖视图。
图21A、图21B、及图21C是本发明实施例中,穿过金属-绝缘层-金属结构中的导体板层的开口的部分剖视图。
图22A及图22B是本发明实施例中,穿过金属-绝缘层-金属结构中的导体板层的上侧接点结构的部分上视图。
符号说明
D1:第一锥形角度
D2:第二锥形角度
D3:第三锥形角度
L1:第一尺寸
L2:第二尺寸
R:直径
S:侧壁
10:方法
12,14,16,18,20,22,24,26,28,30:步骤
200:工件
202:基板
210:内连线层
220:碳化物层
230:氧化物层
240:蚀刻停止层
250:第一介电层
251:沟槽
252:氮氧化硅层
253,254,255:下侧接点结构
256:第二介电层
258:第三介电层
260:金属-绝缘层-金属结构
262:底导体板层
264:第一绝缘层
266:中间导体板层
268:第二绝缘层
267:第四介电层
269:顶导体板层
270:第一多层钝化结构
271,272,273:开口
275,276,277:上侧接点结构
278,2050:阻障层
280:第一钝化层
282:第二钝化层
284:开口
402,404,406:虚置板
具体实施方式
下述详细描述可搭配附图说明,以利理解本发明的各方面。值得注意的是,各种结构仅用于说明目的而未按比例绘制,如本业常态。实际上为了清楚说明,可任意增加或减少各种结构的尺寸。
下述内容提供的不同实施例或例子可实施本发明实施例的不同结构。特定构件与排列的实施例是用以简化本公开而非局限本发明。举例来说,形成第一构件于第二构件上的叙述包含两者直接接触,或两者之间隔有其他额外构件而非直接接触。此外,本发明的多种实例可重复采用相同标号以求简洁,但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。此外,可由不同比例任意示出多种结构,使附图简化清楚。
此外,空间性的相对用语如“下方”、“其下”、“下侧”、“上方”、“上侧”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件,而非局限于图示方向。举例来说,若将附图中的装置翻转,则下方或之下的元件将转为上方或之上的元件。元件亦可转动90°或其他角度,因此方向性用语仅用以说明图示中的方向。
此外,当数值或数值范围的描述有“约”、“近似”、或类似用语时,除非特别说明否则其包含所述数值的+/-10%。举例来说,用语“约5nm”包含的尺寸范围为4.5nm至5.5nm。
金属-绝缘层-金属电容器已广泛用于功能电路如混合信号电路、模拟电路、射频电路、动态随机存取存储器、埋置的动态随机存取存储器、或逻辑操作电路。在单芯片系统应用中,可将不同功能电路所用的不同电容器整合至相同芯片上,以用于不同目的。举例来说,混合信号电路中的电容器用于去耦电容器与高频噪声滤波器。对动态随机存取存储器与埋置的动态随机存取存储器电路而言,电容器可用于存储器存储。对射频电路而言,电容器可用于耦合及/或旁路目的所用的震荡器与相移网络。对微处理器而言,电容器可用于去耦合。金属-绝缘层-金属电容器如其名所示,可包含交错的金属层与绝缘层的三明治结构。金属-绝缘层-金属电容器的例子可包含底导体板层、中间导体板层于底导体板层上、以及顶导体板层于中间导体板层上,并以绝缘层绝缘相邻的导体板层。以后段工艺制作金属-绝缘层-金属电容器的例子中,结构具有较大表面积,且导体板层延伸于多个下侧接点结构上。接点通孔可穿过导体板层并电性耦接下侧接点结构至上侧接点结构(如接点垫),以连接至外部电路。
接点通孔穿过导体板层的情况至少有三种。在第一种情况中,接点通孔延伸穿过导体板层,而不电性耦接至任何导体板层。第一种情况中的接点通孔可用于逻辑驱动信号,且可视作逻辑接点通孔。在第二种情况中,接点通孔延伸穿过导体板层,且只电性耦接至中间导体板层。由于第二种状况中的接点通孔电性耦接至中间导体板层,但与顶导体板层及底导体板层电性隔离,其可视作中间板接点通孔。在第三种情况中,接点通孔延伸穿过导体板层且只电性耦接至顶导体板层与底导体板层。由于第三种情况中的接点孔只电性耦接至顶导体板层与底导体板层,但与中间导体板层电性绝缘,其可视作顶板-底板接点通孔。逻辑导体通孔与操作金属-绝缘层-金属电容无关。相反地,中间板接点通孔与顶板-底板接点通孔可提供通路至中间导体板之间的电容。另一方面,中间板接点通孔与顶板-底板接点通孔可提供通路至顶导体板层与底导体板层之间的电容。
可图案化导体板层以确保电性耦接至个别的接点孔,并与个别的接点孔绝缘。由于逻辑接点穿过导体板层而不耦接至任何导体板层,每一导体板层中的开口垂直对准以形成逻辑接点通孔所用的通道。由于中间板接点通孔耦接至中间导体板层并与顶导体板层及底导体板层绝缘,开口形成于顶导体板层与底导体板层中。由于顶板-底板接点通孔与中间导体板层绝缘,开口形成于中间导体板层中。开口比顶板-底板接点通孔所用的通孔开口大。
由上述说明可知,通孔开口可穿过不同树木的导体板层。逻辑接点通孔的形成方法不需蚀穿所有的三个导体板层,因为已形成垂直对准开口于导体板层中。中间板接点通孔的形成方法需要蚀穿一个导体板层如中间导体板层。顶板-底板接点通孔的形成方法需要蚀穿两个导体板层如顶导体板层与底导体板层。当相同的蚀刻工艺中蚀刻通孔开口时,会产生不均匀的蚀刻负载。蚀穿逻辑接点通孔所用的通孔开口与导体板层无关,蚀穿中间板接点通孔所用的通孔开口与一个导体板层相关,而蚀穿顶板-底板接点通孔所用的通孔开口与两个导体板层相关。为了解决此问题,虚置板可用于平衡不均匀的蚀刻负载。两个虚置板可分别插入底导体板层与中间导体板层中的开口。虚置板可插入顶导体板层,并位于中间板接点通孔形成处。由于插入虚置板,逻辑接点通孔、中间板接点通孔、与顶板-底板接点通孔的形成方法均关于蚀穿两个导体层。
一般采用氟为主的蚀刻剂蚀穿导体板层、其上方的介电层、与其下方的介电层。举例来说,一些现有的蚀刻工艺采用六氟化硅蚀穿导体板层。当导体板层的组成为过渡金属或过渡金属氮化物如钛、钽、氮化钛、或氮化钽时,可发现现有蚀刻工艺会产生副产物如金属氟化物(之后可视作金属氟化物副产物)。举例来说,蚀刻氮化钛的导体板层会产生氟化钛。金属氟化物副产物为非挥发性,且蚀刻工艺时不会移除金属氟化物副产物。蚀刻导体板层时,会再沉积金属氟化物于新蚀刻的表面上,并减缓蚀刻工艺。由于朝下侧导体板层进行蚀刻工艺时易发生再沉积,因此再沉积的金属氟化物通常会造成通孔开口的阶状侧壁。在侧视图中,采用现有工艺所形成的接点通孔其特性为接点通孔穿过金属-绝缘层-金属电容器时,陡峭的锥形之后为和缓的锥形。此外,由于金属氟化物副产物的导电性与蚀刻速率低于导体板层的材料,残留的金属氟化物副产物会保留于导体板层与接点通孔之间的界面,造成接点电阻增加。此外,残留的金属氟化物会再沉积于导体板层之下的介电层上并减缓下方介电层的蚀刻速率,造成下方介电层碟化。下方介电层碟化会造成不均匀地蚀穿下方介电层之下的蚀刻停止层。界面是否残留的金属氟化物副产物,可由能量色散X光光谱观察与确认。
本发明实施例提供的方法可避免形成金属氟化物副产物,并可避免接点电阻增加。本发明实施例的方法采用多个蚀刻工艺形成开口穿过金属-绝缘层-金属结构(以及上方与下方的介电层)。在一些实施例中,第一蚀刻工艺采用六氟化硫蚀穿上方的介电层,第二蚀刻工艺采用氯气蚀穿金属-绝缘层-金属结构,而第三蚀刻工艺采用四氟化碳蚀穿下方介电层。第二蚀刻工艺中的氯气蚀穿金属-绝缘层-金属结构并产生挥发性的金属氯化物,其可在第二蚀刻工艺时轻易移除。本发明实施例不产生减缓蚀刻工艺的非挥发性物种,且可形成线性锥形的接点通孔穿过金属-绝缘层-金属结构。此外,由于金属氯化物的蚀刻副产物易于移除,因此不负面影响接点通孔与导体板层之间的接点电阻。此外,非挥发性的金属氯化物在蚀刻工艺穿过金属-绝缘层-金属结构之下的层状物时,不会造成碟化。
本发明的多种实施例将搭配附图详述。在此考量下,图1是本发明实施例中,制作半导体装置的方法10的流程图。方法10仅用于举例而非局限本发明实施例至方法10所实际记载处。在方法10之前、之中、与之后可提供额外步骤,且方法的额外实施例可置换、省略、或调换一些所述步骤。此处未详述所有步骤以简化说明。在一些实施例中,方法10将搭配图2至20说明如下,其为半导体装置于不同制作阶段的部分剖视图。
如图1及2所示,方法10的步骤12提供工件200。工件200包含多种层状物形成其上。由于自工件200形成半导体装置,因此工件200可视作半导体装置。工件200包括基板202,其组成可为硅或其他半导体材料如锗。基板202亦可包含半导体化合物如碳化硅、砷化镓、砷化铟、或磷化铟。在一些实施例中,基板202可包含半导体合金如硅锗、碳化硅锗、磷砷化镓、或磷化镓铟。在一些实施例中,基板202可包含磊晶层,比如基体半导体层上的磊晶层。多种微电子构件如晶体管构件(包含源极/漏极结构、栅极结构、栅极间隔物、源极/漏极接点、栅极接点、隔离结构如浅沟槽隔离层、或任何其他合适构件)可形成于基板202之中或之上。
工件200亦包括内连线层210。内连线层210可为多层内连线结构中的内连线层之一。多层内连线结构形成于基板202上并可包含多个图案化介电层与导电层以提供工件200的多种微电子构件之间的内连线(如打线)。内连线层210与基板202之间可具有中间层或构件,但未图示以简化说明。在一实施例中,内连线层210厚约169nm至约230nm。
内连线层210可包含多个导电构件以及层间介电构件,且层间介电构件部分或完全地围绕导电构件。导电构件可包含接点、通孔、或金属线路。层间介电构件可为氧化硅或含氧化硅的材料,其中硅以多种合适的方式存在。举例来说,层间介电层构件包含氧化硅或低介电常数的介电材料(介电常数小于氧化硅的介电常数如约4)。在一些实施例中,低介电常数的介电材料包括多孔的有机硅酸盐薄膜如碳氢氧化硅、四乙氧基硅烷的氧化物、未掺杂的硅酸盐玻璃、掺杂氧化硅如硼磷硅酸盐玻璃、掺杂氟的硅酸盐玻璃、磷硅酸盐玻璃、掺杂氟的氧化硅、掺杂碳的氧化硅、多孔的氧化硅、多孔的掺杂碳的氧化硅、碳氮化硅、碳氮氧化硅、旋转涂布的硅为主的聚合物介电层、或上述的组合。
在一实施例中,沉积碳化物层220于内连线层210上。沉积工艺可包含化学气相沉积、物理气相沉积、原子层沉积、或上述的组合。在一些实施例中,碳化物层220通常具有一致的厚度,其介于约45nm至约70nm之间。可采用任何种类的碳化物材料(如碳化硅)作为碳化物层220。
在一实施例中,沉积氧化物层230于碳化物层220上。可采用任何合适的沉积工艺如化学气相沉积、物理气相沉积、原子层沉积、或上述的组合。在一些实施例中,氧化物层230包含未掺杂的氧化硅。在一实施例中,内连线层210、碳化物层220、与氧化物层230可取代为一或多个内连线结构。
在一实施例中,沉积蚀刻停止层240于氧化物层230上。在一些实施例中,蚀刻停止层240厚约45nm至约55nm。蚀刻停止层240可包含碳氮化硅、碳氧化硅、碳化硅、碳氮氧化硅、氮化硅、或上述的组合。
可沉积第一介电层250于蚀刻停止层240上。在一些实施例中,第一介电层250包括未掺杂的氧化硅玻璃或氧化硅。在一些实施例中,第一介电层250厚约800nm至约1000nm。
如图1及图3至图6所示,方法10的步骤14图案化第一介电层250以形成沟槽251。在一些实施方式中,图案化第一介电层250的方法关于多个工艺。如图3所示,沉积氮氧化硅层252于第一介电层250上。在一些实施例中,氮氧化硅层252厚约54nm至约66nm。如图4所示,图案化氮氧化硅层252的方法可采用光微影工艺。如图5所示,采用氮氧化硅层252作为蚀刻遮罩,蚀刻第一介电层以形成沟槽251于其中。如图6所示,在移除作为蚀刻遮罩的氮氧化硅层252之后,可留下图案化的第一介电层250。
如图1及图7所示,方法10的步骤16形成一或多个下侧接点结构(如下侧接点结构253、254、及255)于第一介电层250的沟槽251中。虽然下侧接点结构253、254、及255位于上侧接点结构之下(如下述),下侧接点结构253、254、及255有时可视作顶金属接点,因为其位于晶体管结构(未图示于此处)之上。每一下侧接点结构253、254、及255可包含阻障层与金属填充层。形成下侧接点结构253、254、及255的方法关于多重工艺。在一些实施例中,阻障层2050形成于每一沟槽251中,接着沉积金属填充层于沟槽中的阻障层上。在一些实施例中,阻障层2050包含氮化钛、钽、氮化钽、或上述的组合。在一些实施例中,金属填充层包括金属或合金如铜、钴、镍、铝、钨、钛、或上述的组合。在一些实施例中,金属填充层的形成方法可为沉积或电镀,以及之后的化学机械平坦化工艺。在一实施例中,化学机械平坦化工艺亦移除第一介电层250的约5%至约10%的厚度。在一实施例中,金属填充层的组成为铜。
如图1及图8所示,方法10的步骤18沉积第二介电层256于下侧接点结构253、254、及255上。在一些实施例中,第二介电层256厚约65nm至约85nm。第二介电层256可包含碳氮化硅、氮化硅、及/或其他合适材料,其可保护下侧接点结构253、254、及255免于氧化。此外,步骤18沉积第三介电层258于第二介电层256上。在一些实施例中,第三介电层258厚约300nm至约500nm。第三介电层258可包含氧化物材料如未掺杂的氧化硅玻璃或其他合适材料。
如图1及图9至图13所示,方法10的步骤20形成金属-绝缘层-金属结构260(如图13所示)于第三介电层258上。如图9至图13所示,形成金属-绝缘层-金属结构260的方法关于多重工艺,包括形成与图案化底导体板层262、中间导体板层266、与顶导体板层269。
如图9所示,形成图案化的底导体板层262于第三介电层258上。形成底导体板层262的方法可关于多个工艺如沉积、光微影、显影、及/或蚀刻等等。可对底导体板层262进行表面处理,比如采用一氧化二氮气体的侧壁钝化。在一些实施例中,底导体板层262厚约40nm至约80nm。如图10所示,形成第一绝缘层264于底导体板层262上。在一实施例中,沉积第一绝缘层264,使其具有通常一致的厚度于工件200的上表面上(比如在底导体板层262的顶部与侧壁表面上具有大致相同的厚度)。如图11所示,形成图案化的中间导体板层266于第一绝缘层264上。中间导体板层266的形成方法可与底导体板层262的形成方法类似,但中间导体板层266的图案可与底导体板层262的图案不同。如图12所示,形成第二绝缘层268于中间导体板层266上。在一实施例中,沉积第二绝缘层268,使其具有通常一致的厚度于工件200的上表面上(比如在中间导体板层266的顶部与侧壁表面上具有大致相同的厚度)。如图13所示,形成图案化的顶导体板层269于第二绝缘层268上。顶导体板层269的形成方法可与中间导体板层266或底导体板层262的形成方法类似,但顶导体板层269的图案与中间导体板层266或底导体板层262的图案不同。在一些实施例中,为了避免电迁移与氧扩散,金属-绝缘层-金属结构260的导体板层的组成可为过渡金属或过渡金属的氮化物。举例来说,金属-绝缘层-金属结构260中的导体板层的组成可为钛、钽、氮化钛、或氮化钽。
如图13所示,金属-绝缘层-金属结构260包含多个金属层,比如底导体板层262、中间导体板层266、与顶导体板层269,其可作为电容器的金属板。金属-绝缘层-金属结构260亦包括多个绝缘层,其包含底导体板层262与中间导体板层266之间的第一绝缘层264,以及中间导体板层266与顶导体板层269之间的第二绝缘层268。金属-绝缘层-金属结构260用于实施一或多个电容器,其可连接至另一电子构件如晶体管。多层的金属-绝缘层-金属结构260可让电容器在垂直方向与横向方向中紧密的排列在一起,进而减少实施电容器所需的横向空间。如此一来,金属-绝缘层-金属结构260可容纳超高密度的电容器。
一些实施例为了增加电容值,第一绝缘层264及/或第二绝缘层268可采用高介电常数的介电材料,其介电常数大于氧化硅的介电常数。第一绝缘层264与第二绝缘层268可较薄以增加电容值。然而可维持第一绝缘层264与第二绝缘层268的最小厚度,以避免金属-绝缘层-金属结构260中的电容器电位崩溃(比如当两个电容器板具有高电位差时,电容器板之间可能漏电流而造成崩溃)。在一些实施例中,第一绝缘层与第二绝缘层268各自厚约6nm至约20nm。在一些实施例中,第一绝缘层264与第二绝缘层268的组成可各自为氧化锆、氧化铪、氧化铝、氧化钽、氧化硅、或氧化钛。此外,为了最佳化电容器效能,一些实施例的第一绝缘层264(或第二绝缘层268)为三层结构,其由下至上包括第一锆层、铝层、与第二锆层,且每一层各自厚约15nm至约25nm。
如图1及图14所示,方法10的步骤22沉积第四介电层267于金属-绝缘层-金属结构260上。在一些实施例中,第四介电层267厚约400nm至约500nm。在一些实施例中,第三介电层258可包含氧化物材料,比如未掺杂的氧化硅玻璃或其他合适材料。在一些实施例中,第四介电层267的形成方法可为沉积厚约900nm至约1000nm的氧化物材料,之后以化学机械平坦化工艺达到最终厚度。如图15所示,金属-绝缘层-金属结构260夹设于第三介电层258与第四介电层267之间,且上述两个介电层可具有相同材料及/或相同厚度。在一些实施例中,第二介电层256、第三介电层258、金属-绝缘层-金属结构260、与第四介电层267可视作第一多层钝化结构270的部分。在其他实施例中,若金属-绝缘层-金属结构260不存在于第一多层钝化结构270中,第三介电层258与第四介电层267可结合成单一介电层(厚约900nm至约1100nm)于第二介电层256上。
如图1及图15至图17所示,方法10的步骤24采用多个蚀刻工艺形成一或多个开口(如开口271、272、及273)自上至下穿过第四介电层267、金属-绝缘层-金属结构260、第三介电层258、与第二介电层256。在一些实施例中,步骤24包括第一蚀刻工艺以蚀穿第四介电层267、第二蚀刻工艺以蚀穿金属-绝缘层-金属结构260、与第三蚀刻工艺以蚀穿第三介电层258。如图15所示,实施第一蚀刻工艺。第一蚀刻工艺可为干蚀刻工艺,其采用六氟化硫作为蚀刻剂。第一蚀刻工艺为时控工艺,其止于顶导体板层269。在图15中,顶导体板层269包括虚置板404及406。即使沿着其余的顶导体板层269沉积虚置板404及406,虚置板404及406仍与其余的顶导体板层269绝缘。如上所述,可插入虚置板以避免不均匀的蚀刻负载。
如图16所示,实施第二蚀刻工艺。第二蚀刻工艺可为干蚀刻工艺。选择第二蚀刻工艺所用的蚀刻剂,使蚀刻剂与导体板层的反应不产生第二蚀刻工艺无法轻易移除的非挥发性副产物。在一些实施例中,第二蚀刻工艺所用的蚀刻剂为氯为主的蚀刻剂如氯气。换言之,第二蚀刻工艺所用的蚀刻剂不含氟或氟原子。当导体板层的组成为过渡金属或过渡金属氮化物,第二蚀刻工艺会产生过渡金属氯化物如氯化钛或绿化钽,其为挥发性且易于移除。此外,由于第二蚀刻工艺不产生任何沿着侧壁S再沉积的副产物,第二蚀刻工艺蚀穿金属-绝缘层-金属结构260的蚀刻速率实质上一致。如此一来,沿着金属-绝缘层-金属结构260的开口侧壁为线性锥形。在一些实施例中,第二蚀刻工艺为时控工艺,其可止于完全蚀穿金属-绝缘层-金属结构260中的所有导体板层之后。在一些例子中,第二蚀刻工艺可向下延伸开口(包括开口271、272、及273)至低于金属-绝缘层-金属结构260的水平。第二蚀刻工艺不会造成第三介电层258碟化,因为不再沉积非挥发性的副产物于靠近开口(包括开口271、272、及273)的侧壁的第三介电层258上。第二蚀刻工艺可使开口(包括开口271、272、及273)的下表面实质上平坦。开口的平坦下表面可避免第三蚀刻工艺时产生碟化。
如图17所示,实施第三蚀刻工艺。第三蚀刻工艺可为干蚀刻工艺,其采用的蚀刻剂蚀刻第三介电层258与第二介电层256的速率,大于第二蚀刻工艺的蚀刻速率。此外,可选择第三蚀刻工艺所用的蚀刻剂,使其不损伤下侧接点结构253、254、及255。举例来说,第二蚀刻工艺中的氯气蚀刻氧化物与氮化物的速率,小于四氟化碳的蚀刻速率。目前已知氯气会损伤铜,比如下侧接点结构253、254、及255的材料。在一些实施例中,第三蚀刻工艺采用四氟化碳作为蚀刻剂。如图17所示,第三蚀刻工艺还向下延伸开口(包括开口271、272、及273)直到露出下侧接点结构(包括下侧接点结构253、254、及255)。此时实质上形成开口271、272、及273。在一些实施方式中,可进行一或多道冲洗或清洁工艺,以清洁露出的导电表面(比如穿过金属-绝缘层-金属结构260的侧壁S以及下侧接点结构253、254、及255的露出部分)。
图17所示的开口271、272、及273的轮廓已简化以利说明。实际上,不同的蚀刻工艺可由不同速率蚀刻不同层,以形成不同锥形角度的锥形。穿过金属-绝缘层-金属结构260的开口271、272、及273的侧视细节分别如图21A、21B、及21C所示。首先如图21A所示。第一蚀刻工艺以一致的速率蚀穿第四介电层267,造成线性的锥形轮廓,其相对于正交(垂直)于基板202的方向具有第一锥形角度D1。第二蚀刻以实质上一致的速率蚀穿金属-绝缘层-金属结构260,造成线性的锥形轮廓,其相对于正交(垂直)于基板202的方向具有第二锥形角度D2。第三蚀刻工艺以实质上一致的速率蚀穿第三介电层258,造成线性的锥形轮廓,其相对于正交(垂直)于基板202的方向具有第三锥形角度D3。在一些实施例中,第二锥形角度D2可大于第一锥形角度D1与第三锥形角度D3,而第三锥形角度D3可大于第一锥形角度D1。在一些实施例中,第一锥形角度D1介于约0°至约10°之间,第二锥形角度D2介于约35°至约45°之间,且第三锥形角度D3介于约15°至约20°之间。值得注意的是,第二蚀刻工艺蚀刻第一绝缘层264与第二绝缘层268的速率,不同于蚀刻导体板层的速率。然而蚀穿金属-绝缘层-金属结构的速率由蚀穿较厚的导体板层的速率控制,因此穿过金属-绝缘层-金属结构260的开口的部分具有实质上线性的锥形轮廓。依据形成开口与不同锥形轮廓的蚀刻工艺,每一开口271、272、及273可视为具有三部分:具有第一锥形角度D1的顶部、具有第二锥形角度D2的中间部分、与具有第三锥形角度D3的底部。
图21A、21B、及21C亦显示穿过两个导体板层的每一开口271、272、及273。开口271穿过中间导体板层266中的虚置板402与顶导体板层269中的虚置板404。开口272穿过中间导体板层266与顶导体板层269中的虚置板406。开口273穿过顶导体板层269与底导体板层262。每一虚置板与其余的导体板层绝缘以达电性浮置。
如图1及图18所示,方法10的步骤26分别形成一或多个上侧接点结构(如上侧接点结构275、276、及277)于开口271、272、及273之中与之上。上侧接点结构275、276、及277包含接点通孔,其填入开口271、272、及273且可视作接点通孔、金属通孔、或金属线路。在一些实施例中,为了形成一或多个上侧接点结构(如上侧接点结构275、276、及277),可先顺应性地沉积阻障层278于第四介电层267之上与开口271、272、及273之中,其沉积方法可采用合适的沉积技术如原子层沉积、物理气相沉积、或化学气相沉积。接着可沉积金属填充层于阻障层278上,其沉积方法可采用合适的沉积技术如原子层沉积、物理气相沉积、或化学气相沉积。在一些实施例中,阻障层278与导体板层的材料可相同。在这些实施例中,阻障层278的组成可为钛、钽、氮化钛、或氮化钽。金属填充层的组成可为铜、铝、或其合金。在一些例子中,上侧接点结构所用的金属填充层可包含约95%至约5%的铝。接着图案化沉积的阻障层278与金属填充层,以形成上侧接点结构275、276、及277,如图18所示。在一些实施例中,以两阶段或多阶段的蚀刻工艺图案化阻障层278与金属填充层。在图18所示的实施例中,上侧接点结构275、276、及277高于第四介电层267的部分,可具有实质上笔直的侧壁。在图18所示的其他实施例中,上侧接点结构275、276、及277高于第四介电层267的部分可具有锥形侧壁。在一些实施方式中,非等向蚀刻工艺步骤的蚀刻速率大于等向蚀刻工艺步骤的蚀刻速率,且需较多能量。虽然未图示,沿着Z方向所示的上侧接点结构可为方形、圆形、卵形、跑道形、多边形、或矩形。
上侧接点结构275、276、及277的至少上侧部分为重布线层的部分,以重新接合上侧与下侧层之间的连线。上侧接点结构275、276、及277各自由上至下穿过第四介电层267、金属-绝缘层-金属结构260、第三介电层258、与第二介电层256。上侧接点结构275、276、及277可分别电性接触下侧接点结构253、254、及255。上侧接点结构275为逻辑接点通孔,其电性耦接至下侧接点结构253,但与金属-绝缘层-金属结构260的功能部分电性绝缘。虽然上侧接点结构275电性耦接至虚置板402及404,虚置板402及404为电性浮置。如此一来,上侧接点结构275与底导体板层262、中间导体板层266、与顶导体板层269的任一者电性绝缘。上侧接点结构277为中间板接点通孔,其电性耦接至中间导体板层266,但与底导体板层262及顶导体板层269电性绝缘。虽然上侧接点结构277电性耦接至虚置板406,虚置板406为电性浮置且与其余的顶导体板层269电性绝缘。上侧接点结构277为顶板-底板接点通孔,其电性耦接至底导体板层262与顶导体板层269,但与中间导体板层266电性绝缘。
虽然图18未示出,上侧接点结构275、276、及277的形状与轮廓通常追随开口271、272、及273的形状与轮廓。上侧接点结构275、276、及277将追随锥形轮廓,如图21A、21B、及21C所示。此处不详述细节以简化说明。
如图1及图19所示,方法10的步骤28形成钝化结构于上侧接点结构275、276、及277与第四介电层267上。如图18所示,第一钝化层280形成于工件200上,包括形成于上侧接点结构275、276、及277与第四介电层267上。在一些实施例中,第一钝化层280可包含一或多个等离子体辅助氧化物层、一或多个未掺杂的氧化硅玻璃层、或上述的组合。第一钝化层280的形成方法可采用化学气相沉积、旋转涂布、或其他合适技术。在一些实施方式中,第一钝化层280的厚度可介于约1000nm至约1400nm之间,比如1200nm。第二钝化层282形成于第一钝化层280上。在一些实施例中,第二钝化层282可包含氮化硅,其形成方法可为化学气相沉积、物理气相沉积、或合适方法,且其厚度介于约600nm至约800nm之间(比如700nm)。
图19中的上侧接点结构275、276、及277(包括阻障层278)的任一者的上视图可为实质上矩形或实质上圆形。图22A及图22B各自为上侧接点结构275、276、及277(包括阻障层278)的一者于X-Y平面上穿过第四介电层267的剖视图。在一些实施例中,上侧接点结构275、276、及277(包括阻障层278)的任一者为实质上矩形,如图22A所示。图22A中的矩形剖面具有第一尺寸L1与第二尺寸L2。在一些例子中,第一尺寸L1可与第二尺寸L2相同。在其他例子中,第一尺寸L1可大于第二尺寸L2。在一些实施方式中,第一尺寸L1与第二尺寸L2介于约3200nm至约3800nm之间。在一些其他实施例中,每一上侧接点结构275、276、及277(含阻障层278)为实质上圆形,如图22B所示。图22B中的圆形剖面具有直径R。在一些实施方式中,直径R介于约3200nm至约3800nm之间。
如图1及图20所示,方法10的步骤30进行后续工艺。后续工艺可包含形成开口284穿过第一钝化层280与第二钝化层282、沉积一或多个聚合物材料层、图案化一或多个聚合物材料层、沉积凸块下金属化层、沉积含铜凸块层、沉积盖层、沉积焊料层、以及再流动焊料层。这些额外工艺可形成接点结构以用于连接至外部电路。
本发明实施例的方法与半导体装置可提供一些优点。举例来说,本发明实施例的方法采用无氟蚀刻剂蚀穿金属-绝缘层-金属结构,以避免残留的金属氟化物副产物存在于接点通孔与金属-绝缘层-金属结构之间的界面。无金属氟化物残留可改善界面电阻与装置效能。
本发明一实施例提供半导体装置的形成方法。方法包括接收基板,其包括下侧接点结构;沉积第一介电层于基板上;形成金属-绝缘层-金属结构于第一介电层上;沉积第二介电层于金属-绝缘层-金属结构上;进行第一蚀刻工艺,形成开口延伸穿过第二介电层以露出金属-绝缘层-金属结构;进行第二蚀刻工艺,延伸开口穿过金属-绝缘层-金属结构,以露出第一介电层;以及进行第三蚀刻工艺,进一步延伸开口穿过第一介电层,以露出下侧接点结构。第一蚀刻工艺包括第一蚀刻剂,第二蚀刻工艺包括第二蚀刻剂,且第三蚀刻工艺包括第三蚀刻剂。第一蚀刻剂与第三蚀刻剂包括氟,且第二蚀刻剂不含氟。
在一些实施例中,金属-绝缘层-金属结构包括导体板层,其组成为氮化钛、氮化钽、钛、或钽。在一些实施例中,金属-绝缘层-金属结构包括绝缘层,其组成为氧化锆、氧化铪、氧化铝、氧化钽、氧化硅、或氧化钛。在一些实施例中,第一蚀刻剂包括六氟化硫,第二蚀刻剂包括氯气,第三蚀刻剂包括四氟化碳,且下侧接点结构包括铜。
本发明另一实施例关于半导体装置的形成方法。方法包括接收含有下侧接点结构的基板;沉积氮化硅层于基板上,包括形成氮化硅层于下侧接点结构上;沉积第一氧化硅层于氮化硅层上;形成导体板层于第一氧化硅层上;沉积第二氧化硅层于导体板层上;进行第一蚀刻工艺,形成开口穿过第二氧化硅层,以露出导体板层;进行第二蚀刻工艺,延伸开口穿过导体板层,以露出第一氧化硅层;以及进行第三蚀刻工艺,进一步延伸开口穿过第一氧化硅层与氮化硅层,以露出下侧接点结构。第一蚀刻工艺包括第一蚀刻剂,第二蚀刻工艺包括第二蚀刻剂,且第三蚀刻工艺包括第三蚀刻剂。第一蚀刻剂与第三蚀刻剂含氟,而第二蚀刻剂基本上为氯气。
在一些实施例中,导体板层包括氮化钛、氮化钽、钛、或钽。在一些实施例中,上述方法还包括沉积绝缘层于导体板层上。绝缘层的组成为氧化锆、氧化铪、氧化铝、氧化钽、氧化硅、或氧化钛。在一些例子中,第一蚀刻剂包括六氟化硫,且其中第三蚀刻剂包括四氟化碳。在一些实施方式中,第二蚀刻剂与导体板层之间不反应产生非挥发性副产物。在一些实施例中,开口穿过导体板层且为线性锥形。在一些实施例中,上述方法还包括形成接点通孔穿过开口,以接触下侧接点结构。在一些实施例中,接点通孔包括阻障层与金属填充层,阻障层与导体板层包括相同组成,且金属填充层包括铜与铝。
本发明另一实施例关于半导体装置。半导体装置包括下侧接点结构;第一介电层,位于下侧接点结构上;金属-绝缘层-金属结构,位于第一介电层上;第二介电层,位于金属-绝缘层-金属结构上;以及接点通孔,延伸穿过第一介电层、金属-绝缘层-金属结构、与第二介电层,以直接接触下侧接点结构。接点通孔包括穿过第一介电层的厚度的第一部分、穿过金属-绝缘层-金属结构的厚度的第二部分、以及穿过第二介电层的厚度的第三部分。第一部分以第一角度呈实质上线性的锥形。第二部分以第二角度呈实质上线性的锥形,且第二角度大于第一角度。第三部分以第三角度呈实质上线性的锥形,且第三角度小于第二角度。
在一些实施例中,金属-绝缘层-金属结构包括导体板层。接点通孔包括阻障层与埋置于阻障层中的金属填充层。阻障层与导体板层包括钛、钽、氮化钛、或氮化钽。金属填充层包括铜与铝。在一些实施方式中,金属-绝缘层-金属结构包括绝缘层,其组成为氧化锆、氧化铪、氧化铝、氧化钽、氧化硅、或氧化钛。在一些例子中,接点通孔与金属-绝缘层-金属结构之间的界面无金属氟化物。在一些实施例中,第一角度介于约0°至约10°之间,第二角度介于约35°至约45°之间,且第三角度介于约15°至约20°之间。
上述实施例的特征有利于本技术领域中技术人员理解本发明。本技术领域中技术人员应理解可采用本发明作基础,设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中技术人员亦应理解,这些等效置换并未脱离本发明构思与范围,并可在未脱离本发明的构思与范围的前提下进行改变、替换、或变动。
Claims (1)
1.一种半导体装置的形成方法,包括:
接收一基板,其包括一下侧接点结构;
沉积一第一介电层于该基板上;
形成一金属-绝缘层-金属结构于该第一介电层上;
沉积一第二介电层于该金属-绝缘层-金属结构上;
进行一第一蚀刻工艺,形成一开口延伸穿过该第二介电层以露出该金属-绝缘层-金属结构;
进行一第二蚀刻工艺,延伸该开口穿过该金属-绝缘层-金属结构,以露出该第一介电层;以及
进行一第三蚀刻工艺,进一步延伸该开口穿过该第一介电层,以露出该下侧接点结构,
其中该第一蚀刻工艺包括一第一蚀刻剂,该第二蚀刻工艺包括一第二蚀刻剂,且该第三蚀刻工艺包括一第三蚀刻剂,
其中该第一蚀刻剂与该第三蚀刻剂包括氟,
其中该第二蚀刻剂不含氟。
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