TW202133354A - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TW202133354A
TW202133354A TW109121417A TW109121417A TW202133354A TW 202133354 A TW202133354 A TW 202133354A TW 109121417 A TW109121417 A TW 109121417A TW 109121417 A TW109121417 A TW 109121417A TW 202133354 A TW202133354 A TW 202133354A
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Taiwan
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semiconductor
semiconductor wafer
wafer
substrate
chip
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TW109121417A
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English (en)
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TWI770541B (zh
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金泳龍
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南韓商三星電子股份有限公司
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Abstract

本發明揭露一種半導體封裝，包括：第一半導體晶片，在基板上；第二半導體晶片，在所述基板上且與所述第一半導體晶片橫向間隔開；虛擬晶片，在所述第一半導體晶片上；以及介電層，在所述第一半導體晶片與所述虛擬晶片之間。所述第一半導體晶片的頂表面可低於所述第二半導體晶片的頂表面。所述介電層可包含無機介電材料。

Description

半導體封裝
本發明概念是有關於一種半導體封裝，且更具體而言，是有關於一種其中安裝有多個半導體晶片的半導體封裝。
提供半導體封裝來實作積體電路晶片，以有資格在電子產品中使用。通常，在半導體封裝中，將半導體晶片安裝於印刷電路板（printed circuit board，PCB）上，且使用接合導線或凸塊將半導體晶片電性連接至印刷電路板。隨著電子工業的發展，需要更小、更輕及多功能的電子裝置，且因此提出了其中多個晶片堆疊於單個半導體封裝中的多晶片封裝、或者具有安裝於單個半導體封裝中的不同種類的晶片且作為一個系統運作的系統級封裝（system-in-package）。
本發明概念的一些示例性實施例提供一種其中多個半導體晶片被輕易地安裝且熱輻射得以改良的半導體封裝。
根據本發明概念的一些示例性實施例，一種半導體封裝可包括：基板；第一半導體晶片，在所述基板上；第二半導體晶片，在所述基板上，所述第二半導體晶片與所述第一半導體晶片橫向間隔開，所述第二半導體晶片被佈置成使得所述第一半導體晶片的頂表面低於所述第二半導體晶片的頂表面；虛擬晶片，在所述第一半導體晶片上；以及介電層，在所述第一半導體晶片與所述虛擬晶片之間。所述介電層可包含無機介電材料。
根據本發明概念的一些示例性實施例，一種半導體封裝可包括：第一基板；第二基板，在所述第一基板上並電性連接至所述第一基板；第一半導體晶片，在所述第二基板上；第二半導體晶片，在所述第二基板上，所述第二半導體晶片與所述第一半導體晶片橫向間隔開，所述第二半導體晶片被佈置成使得所述第一半導體晶片的頂表面低於所述第二半導體晶片的頂表面；虛擬晶片，在所述第一半導體晶片上；以及介電層，在所述第一半導體晶片與所述虛擬晶片之間。所述介電層可包含無機介電材料。
根據本發明概念的一些示例性實施例，一種半導體封裝可包括：基板；第一半導體晶片，在所述基板上，所述第一半導體晶片包括與所述第一半導體晶片的頂表面鄰近的多個第一晶片焊墊；第二半導體晶片，在所述基板上，所述第二半導體晶片與所述第一半導體晶片橫向間隔開；及上部半導體晶片，在所述第一半導體晶片上。所述上部半導體晶片的底表面可面對所述第一半導體晶片的頂表面。所述上部半導體晶片可包括與所述上部半導體晶片的所述底表面鄰近的多個第二晶片焊墊。所述多個第二晶片焊墊可直接連接至所述多個第一晶片焊墊。所述第一半導體晶片的所述頂表面可低於所述第二半導體晶片的頂表面。
當在本說明書中結合數值而使用用語「約」或「實質上」時，旨在使相關聯的數值包括在所陳述數值周圍±10%的容差。當指定範圍時，所述範圍包括其之間的所有值，例如0.1%的增量。
現在將在以下參照附圖詳細闡述本發明概念的一些示例性實施例。
圖1說明示出根據本發明概念一些示例性實施例的半導體封裝1000的平面圖。圖2說明沿著圖1所示線I-I’截取的剖視圖。
參照圖1及圖2，第一半導體晶片300及第二半導體晶片200可設置於基板100上。第二半導體晶片200可被設置成與第一半導體晶片300橫向間隔開。根據一些實施例，多個第二半導體晶片200可放置於基板100上，且所述多個第二半導體晶片200中的每一者可與第一半導體晶片300橫向間隔開。
基板100可例如為中介層基板。基板100可包括在基板100的頂表面100U上的第一基板焊墊110及在基板100的底表面100L上的第二基板焊墊120。第一基板焊墊110可藉由基板100中的內部線路電性連接至第二基板焊墊120。基板100可在其底表面100L上設置有下部凸塊130，下部凸塊130連接至對應的第二基板焊墊120。第一基板焊墊110及第二基板焊墊120以及下部凸塊130可包含導電材料。
第一半導體晶片300可具有彼此相對的第一表面300S1及第二表面300S2，且可包括與第一表面300S1鄰近的電路層320及第一晶片焊墊310。電路層320可包括積體電路。第一半導體晶片300可被設置成使得第一表面300S1能夠面對基板100的頂表面100U。在本說明中，第一半導體晶片300的第一表面300S1可被稱為第一半導體晶片300的底表面，且第一半導體晶片300的第二表面300S2可被稱為第一半導體晶片300的頂表面。
第一凸塊360可設置於第一半導體晶片300與基板100之間。第一凸塊360可放置於第一半導體晶片300的第一表面300S1與基板100的頂表面100U之間，且可連接至第一基板焊墊110中對應的第一基板焊墊。第一凸塊360可連接至第一半導體晶片300的對應的第一晶片焊墊310。第一半導體晶片300可藉由第一凸塊360電性連接至基板100。第一凸塊360可包含導電材料。
第二半導體晶片200可具有彼此相對的第一表面200S1及第二表面200S2。第二半導體晶片200可被設置成使得第一表面200S1能夠面對基板100的頂表面100U。在本說明中，第二半導體晶片200的第一表面200S1可被稱為第二半導體晶片200的底表面，且第二半導體晶片200的第二表面200S2可被稱為第二半導體晶片200的頂表面。
第二半導體晶片200可包括多個子半導體晶片210、220及230，且所述多個子半導體晶片210、220及230可在與基板100的頂表面100U垂直的方向上堆疊。在此種情形中，第二半導體晶片200的第一表面200S1可對應於所述多個子半導體晶片210、220及230中最下部的子半導體晶片210的底表面，且第二半導體晶片200的第二表面200S2可對應於所述多個子半導體晶片210、220及230中最上部的子半導體晶片230的頂表面。第二半導體晶片200可包括穿透所述多個子半導體晶片210、220及230的貫通電極250，且可更包括所述多個子半導體晶片210、220及230之間的連接凸塊240。所述多個子半導體晶片210、220及230可經由貫通電極250及連接凸塊240彼此電性連接。貫通電極250及連接凸塊240可包含導電材料。
第二凸塊260可設置於第二半導體晶片200與基板100之間。第二凸塊260可放置於第二半導體晶片200的第一表面200S1與基板100的頂表面100U之間，且可連接至第一基板焊墊110中對應的第一基板焊墊。當第二半導體晶片200包括所述多個子半導體晶片210、220及230時，第二凸塊260可連接至穿透所述多個子半導體晶片210、220及230中最下部的子半導體晶片210的對應的貫通電極250。第二半導體晶片200可藉由第二凸塊260電性連接至基板100。第二凸塊260可包含導電材料。
第一半導體晶片300及第二半導體晶片200可為彼此不同的半導體晶片。例如，第一半導體晶片300可為邏輯晶片、應用處理器（application processor，AP）晶片或系統晶片（system-on-chip，SOC），且第二半導體晶片200可為記憶體晶片。當第二半導體晶片200包括所述多個子半導體晶片210、220及230時，所述多個子半導體晶片210、220及230可包括多個記憶體晶片。例如，所述多個子半導體晶片210、220及230中最下部的子半導體晶片210可包括邏輯電路、記憶體電路或其組合，且所述多個子半導體晶片210、220及230的其餘部分可為彼此相同的記憶體晶片。第二記憶體晶片200可為其中堆疊有多個記憶體晶片（例如，彼此相同的記憶體晶片）的高頻寬記憶體（high bandwidth memory，HBM）晶片。
第一半導體晶片300可具有較第二半導體晶片200的厚度200T小的厚度300T。第一半導體晶片300的第二表面300S2（或頂表面）可位於較第二半導體晶片200的第二表面200S2（或頂表面）低的高度處。當第二半導體晶片200包括所述多個子半導體晶片210、220及230時，第一半導體晶片300的第二表面300S2（或頂表面）的高度可小於所述多個子半導體晶片210、220及230中最上部的子半導體晶片230的頂表面的高度。在本說明中，「厚度」可沿著與基板100的頂表面100U垂直的方向而量測，且「高度」可為自基板100的頂表面100U量測的距離。
根據一些實施例，虛擬晶片400可堆疊於第一半導體晶片300上，且介電層500可設置於第一半導體晶片300與虛擬晶片400之間。虛擬晶片400可具有彼此相對的第一表面400S1及第二表面400S2，且可被設置成使得第一表面400S1能夠面對第一半導體晶片300的第二表面300S2。在本說明中，虛擬晶片400的第一表面400S1可被稱為虛擬晶片400的底表面，且虛擬晶片400的第二表面400S2可被稱為虛擬晶片400的頂表面。介電層500可夾置於第一半導體晶片300的第二表面300S2與虛擬晶片400的第一表面400S1之間，且可沿著第一半導體晶片300的第二表面300S2及沿著虛擬晶片400的第一表面400S1延伸。虛擬晶片400的第二表面400S2可位於與第二半導體晶片200的第二表面200S2實質上相同的高度處。
介電層500可提供第一半導體晶片300與虛擬晶片400之間的直接接合。介電層500可包含無機介電材料，例如氧化矽、氮化矽及碳氮化矽中的一或多種。介電層500可具有約1微米（μm）或更小的厚度500T。當介電層500的厚度T5大於約1微米時，可能難以排放自第一半導體晶片300產生的熱。虛擬晶片400可為不具有電路層的半導體基板，例如矽基板、鍺基板或矽-鍺基板。例如，虛擬晶片400可為塊體矽基板。
當多個半導體晶片安裝於單個基板或基板100上時，所述半導體晶片可被設置成使得其頂表面接觸地使用導熱層來排放自半導體晶片產生的熱。當各半導體晶片具有不同的厚度時，半導體晶片的頂表面可位於不同的高度處，且在此種情形中，可能難以形成導熱層。
根據本發明概念，虛擬晶片400可堆疊於第一半導體晶片300上，且虛擬晶片400的第二表面400S2可位於與第二半導體晶片200的第二表面200S2實質上相同的高度處。例如，虛擬晶片400可補償第一半導體晶片300的第二表面300S2與第二半導體晶片200的第二表面200S2之間的高度差。因此，在後續製程中，可在虛擬晶片400的第二表面400S2及第二半導體晶片200的第二表面200S2上輕易地形成導熱層。
此外，第一半導體晶片300及虛擬晶片400可藉由包含無機介電材料的介電層500彼此直接接合。在此種情形中，第一半導體晶片300及虛擬晶片400可在晶圓級接合製程中輕易地彼此接合。另外，由於介電層500包含無機介電材料，因此可輕易地排放自第一半導體晶片300產生的熱。
因此，可提供其中多個半導體晶片被輕易地安裝且熱輻射得以改良的半導體封裝1000。
圖3及圖4說明沿著圖1所示線I-I’截取的剖視圖，其各自示出根據本發明概念一些示例性實施例的半導體封裝1100。為使說明簡潔起見，以下將著重於與參照圖1及圖2所論述的半導體封裝1000的差異。
參照圖1、圖3及圖4，根據一些實施例，虛擬半導體晶片600可設置於基板100上。虛擬半導體晶片600可與第一半導體晶片300及第二半導體晶片200橫向間隔開。虛擬半導體晶片600可具有彼此相對的第一表面600S1及第二表面600S2，且可被設置成使得第一表面600S1能夠面對基板100的頂表面100U。在本說明中，虛擬半導體晶片600的第一表面600S1可被稱為虛擬半導體晶片600的底表面，且虛擬半導體晶片600的第二表面600S2可被稱為虛擬半導體晶片600的頂表面。
根據一些實施例，如圖3所示，虛擬凸塊660可設置於虛擬半導體晶片600與基板100之間。虛擬凸塊660可放置於虛擬半導體晶片600的第一表面600S1與基板100的頂表面100U之間，且可連接至第一基板焊墊110中對應的第一基板焊墊。虛擬半導體晶片600可藉由虛擬凸塊660附著至基板100。虛擬凸塊660可包含導電材料，但本發明概念並非僅限於此。虛擬凸塊660可包含與第一凸塊360及第二凸塊260相同的材料。
根據其他實施例，如圖4所示，黏合層665可設置於虛擬半導體晶片600與基板100之間。黏合層665可放置於虛擬半導體晶片600的第一表面600S1與基板100的頂表面100U之間。虛擬半導體晶片600可藉由黏合層665附著至基板100。黏合層665可包含有機介電材料。
返回參照圖1、圖3及圖4，虛擬半導體晶片600可具有較第一半導體晶片300的厚度300T大的厚度600T。虛擬半導體晶片600的第二表面600S2（或頂表面）可位於較第一半導體晶片300的第二表面300S2（或頂表面）大的高度處。根據一些實施例，虛擬半導體晶片600的第二表面600S2的高度可與虛擬晶片400的第二表面400S2的高度及第二半導體晶片200的第二表面200S2的高度實質上相同。虛擬半導體晶片600可為不具有電路層的半導體晶片，例如矽基板、鍺基板或矽-鍺基板。例如，虛擬半導體晶片600可為塊體矽基板。
根據本實施例，第一半導體晶片300、第二半導體晶片200及虛擬半導體晶片600可安裝於單個基板或基板100上，且虛擬晶片400可堆疊於第一半導體晶片300上。虛擬半導體晶片600的第二表面600S2的高度可與虛擬晶片400的第二表面400S2的高度及第二半導體晶片200的第二表面200S2的高度實質上相同。因此，在後續製程中，可在虛擬晶片400的第二表面400S2、第二半導體晶片200的第二表面200S2及虛擬半導體晶片600的第二表面600S2上輕易地形成導熱層。
圖5至圖7說明示出根據本發明概念一些示例性實施例製作半導體封裝的方法的剖視圖。為使說明簡潔起見，將作出省略以避免對參照圖1至圖4所論述的半導體封裝1000及1100進行贅述。
參照圖5，可提供包括多個第一半導體晶片300的第一晶圓300W。第一晶圓300W可具有彼此相對的第一表面300WS1及第二表面300WS2。所述多個第一半導體晶片300中的每一者可包括電路層320及第一晶片焊墊310，且電路層320及第一晶片焊墊310可鄰近於第一晶圓300W的第一表面300WS1設置。電路層320可包括積體電路。
可在第一晶圓300W的第二表面300WS2上形成第一介電層510。第一介電層510可包含無機介電材料，例如氧化矽、氮化矽及碳氮化矽中的一或多種。根據一些實施例，第一介電層510的形成可包括執行沈積製程以在第一晶圓300W的第二表面300WS2上沈積第一介電層510。沈積製程可例如為化學氣相沈積製程。根據其他實施例，第一介電層510可為藉由對第一晶圓300W的第二表面300WS2執行平坦化製程而形成的原生氧化物層。平坦化製程可例如為化學機械研磨製程或回蝕製程。
可提供虛擬晶圓400W。虛擬晶圓400W可具有彼此相對的第一表面400WS1及第二表面400WS2。虛擬晶圓400W可為不具有電路層的半導體晶圓，例如矽基板、鍺基板或矽-鍺基板。例如，虛擬晶圓400W可為塊體矽基板。
可在虛擬晶圓400W的第一表面400WS1上形成第二介電層520。第二介電層520可包含無機介電材料，例如氧化矽、氮化矽及碳氮化矽中的一或多種。第二介電層520可藉由用於形成第一介電層510的實質上相同的方法來形成。
可將第一晶圓300W設置於虛擬晶圓400W的第一表面400WS1上。第一晶圓300W可被設置成使得其第二表面300WS2能夠面對虛擬晶圓400W的第一表面400WS1。因此，第一介電層510可鄰近於第二介電層520設置。
參照圖6，熱壓製程HC可將第一介電層510接合至第二介電層520，藉此形成介電層500。介電層500可提供第一晶圓300W與虛擬晶圓400W之間的直接結合。因此，可形成其中第一晶圓300W及虛擬晶圓400W彼此接合的接合式結構SS。
參照圖7，在形成接合式結構SS之後，可在第一晶圓300W的第一表面300WS1上形成第一凸塊360。第一凸塊360可連接至第一半導體晶片300中的每一者的對應的第一晶片焊墊310。
切割製程SP可將接合式結構SS分離成多個晶片堆疊CS。切割製程SP可將第一晶圓300W分離成所述多個第一半導體晶片300，且亦可將虛擬晶圓400W分離成多個虛擬晶片400。晶片堆疊CS中的每一者可包括第一半導體晶片300、虛擬晶片400以及第一半導體晶片300與虛擬晶片400之間的介電層500。晶片堆疊CS中的每一者可更包括形成於第一半導體晶片300中的每一者上的對應的第一凸塊360。
第一晶圓300W的第一表面300WS1可對應於第一半導體晶片300中的每一者的第一表面300S1，且第一晶圓300W的第二表面300WS2可對應於第一半導體晶片300中的每一者的第二表面300S2。虛擬晶圓400W的第一表面400WS1可對應於虛擬晶片400中的每一者的第一表面400S1，且虛擬晶圓400W的第二表面400WS2可對應於虛擬晶片400中的每一者的第二表面400S2。
返回參照圖1及圖2，可將晶片堆疊CS中對應的晶片堆疊設置於基板100上。基板100可例如為中介層基板。對應的晶片堆疊CS可被設置成使得第一半導體晶片300的第一表面300S1能夠面對基板100的頂表面100U。對應的晶片堆疊CS可在基板100上被安裝成使得第一凸塊360可接觸對應的第一基板焊墊110。可將第二半導體晶片200安裝於基板100上，且半導體封裝1000可由基板100、第二半導體晶片200及對應的晶片堆疊CS構成。根據一些實施例，如參照圖3及圖4所論述，可將虛擬半導體晶片600設置於基板100上，且半導體封裝1100可由基板100、第二半導體晶片200、對應的晶片堆疊CS及虛擬半導體晶片600構成。
圖8至圖11說明示出根據本發明概念一些示例性實施例製作半導體封裝的方法的剖視圖。為使說明簡潔起見，以下將著重於與參照圖5至圖7所論述的製作半導體封裝的方法的差異。
參照圖8，可提供包括多個第一半導體晶片300的第一晶圓300W。第一晶圓300W可具有彼此相對的第一表面300WS1及第二表面300WS2。所述多個第一半導體晶片300中的每一者可包括電路層320及第一晶片焊墊310，且電路層320可鄰近於第一晶圓300W的第一表面300WS1設置。電路層320可包括積體電路。
可在第一晶圓300W的第一表面300WS1上形成第一凸塊360。第一凸塊360可連接至第一半導體晶片300中的每一者的對應的第一晶片焊墊310。
可在第一晶圓300W的第一表面300WS1上形成保護膜370，且保護膜370可覆蓋第一凸塊360。保護膜370可例如包含介電樹脂。
參照圖9，可在第一晶圓300W的第二表面300WS2上形成第一介電層510。第一介電層510可包含無機介電材料，例如氧化矽、氮化矽及碳氮化矽中的一或多種。第一介電層510可藉由參照圖5所論述的用於形成第一介電層510的實質上相同的方法來形成。
可提供虛擬晶圓400W。虛擬晶圓400W可具有彼此相對的第一表面400WS1及第二表面400WS2，且可在虛擬晶圓400W的第一表面400WS1上形成第二介電層520。第二介電層520可包含無機介電材料，例如氧化矽、氮化矽及碳氮化矽中的一或多種。第二介電層520可藉由用於形成第一介電層510的實質上相同的方法來形成。
可將第一晶圓300W設置於虛擬晶圓400W的第一表面400WS1上。第一晶圓300W可被設置成使得其第二表面300WS2能夠面對虛擬晶圓400W的第一表面400WS1。因此，第一介電層510可鄰近於第二介電層520設置。
參照圖10，熱壓製程HC可將第一介電層510接合至第二介電層520，藉此形成介電層500。根據本實施例，保護膜370可在熱壓製程HC期間保護第一凸塊360。介電層500可提供第一晶圓300W與虛擬晶圓400W之間的直接結合。因此，可形成其中第一晶圓300W及虛擬晶圓400W彼此接合的接合式結構SS。
參照圖11，在形成接合式結構SS之後，可對虛擬晶圓400W的第二表面400WS2執行輪磨製程BG。輪磨製程BG可使欲加工的虛擬晶圓400W具有所需的厚度400WT。此後，可移除保護膜370。後續製程可與參照圖1、圖2及圖5至圖7所論述的製程實質上相同。
圖12說明沿著圖1所示線I-I’截取的剖視圖，其示出根據本發明概念一些示例性實施例的半導體封裝1200。為使說明簡潔起見，以下將著重於與參照圖1及圖2所論述的半導體封裝1000的差異。
參照圖12，第一半導體晶片300及第二半導體晶片200可設置於基板100上。基板100及第二半導體晶片200可與參照圖1及圖2所論述的基板100及第二半導體晶片200實質上相同。
第一半導體晶片300可具有彼此相對的第一表面300S1及第二表面300S2，且可被設置成使得第一表面300S1能夠面對基板100的頂表面100U。第一半導體晶片300可包括與第一表面300S1或第二表面300S2鄰近的電路層（圖中未示出），且所述電路層可包括積體電路。第一半導體晶片300可包括與第二表面300S2鄰近的第一晶片焊墊310，且更包括穿透第一半導體晶片300內部的貫通電極330。貫通電極330可連接至第一晶片焊墊310中對應的第一晶片焊墊。第一晶片焊墊310中的至少一者可與貫通電極330電性分離。第一晶片焊墊310及貫通電極330可包含導電材料。
第一凸塊360可設置於第一半導體晶片300與基板100之間。第一半導體晶片300的貫通電極330可連接至第一凸塊360中對應的第一凸塊，且第一半導體晶片300可藉由第一凸塊360電性連接至基板100。
根據一些實施例，上部半導體晶片700可堆疊於第一半導體晶片300上。上部半導體晶片700可具有彼此相對的第一表面700S1及第二表面700S2，且可被設置成使得第一表面700S1能夠面對第一半導體晶片300的第二表面300S2。在本說明中，上部半導體晶片700的第一表面700S1可被稱為上部半導體晶片700的底表面，且上部半導體晶片700的第二表面700S2可被稱為上部半導體晶片700的頂表面。
上部半導體晶片700可包括與第一表面700S1鄰近的電路層720。電路層720可包括積體電路。上部半導體晶片700可包括與第一表面700S1鄰近的第二晶片焊墊710。第二晶片焊墊710可連接至對應的第一晶片焊墊310。第二晶片焊墊710可直接連接至第一晶片焊墊310，且例如，可與第一晶片焊墊310直接接觸。第二晶片焊墊710可包含導電材料。
第一晶片焊墊310及第二晶片焊墊710可提供第一半導體晶片300與上部半導體晶片700之間的直接接合。在此種情形中，上部半導體晶片700的第一表面700S1及第一半導體晶片300的第二表面300S2可彼此接觸以構成邊界B。上部半導體晶片700與第一半導體晶片300之間的邊界B可包含第一晶片焊墊310之間及第二晶片焊墊710之間的無機介電材料（例如，氧化矽）。
上部半導體晶片700的第二表面700S2（或頂表面）可位於與第二半導體晶片200的第二表面200S2實質上相同的高度處。上部半導體晶片700可為邏輯晶片、應用處理器（AP）晶片、記憶體晶片或系統晶片（SOC）。上部半導體晶片700可藉由第一晶片焊墊310及第二晶片焊墊710電性連接至第一半導體晶片300，且亦可經由貫通電極330及第一凸塊360電性連接至基板100。
根據本實施例，上部半導體晶片700可堆疊於第一半導體晶片300上，且上部半導體晶片700的第二表面700S2（或頂表面）的高度可與第二半導體晶片200的第二表面200S2的高度實質上相同。例如，上部半導體晶片700可補償第一半導體晶片300的第二表面300S2與第二半導體晶片200的第二表面200S2之間的高度差。因此，在後續製程中，可在上部半導體晶片700的第二表面700S2及第二半導體晶片200的第二表面200S2上輕易地形成導熱層。
第一晶片焊墊310及第二晶片焊墊710可提供第一半導體晶片300與上部半導體晶片700之間的直接接合。在此種情形中，第一半導體晶片300及上部半導體晶片700可在晶圓級接合製程中輕易地彼此接合。另外，第一半導體晶片300的第一晶片焊墊310中的至少一者可與貫通電極330電性分離，且在此種情形中，所述至少一個第一晶片焊墊310及其所連接的第二晶片焊墊710可用作排放自第一半導體晶片300產生的熱所沿著的路徑。因此，可輕易地排放自第一半導體晶片300產生的熱。
除了前面所提及的差異之外，根據本實施例的半導體封裝1200可與以上參照圖1及圖2所論述的半導體封裝1000實質上相同。
圖13及圖14說明沿著圖1所示線I-I’截取的剖視圖，其各自示出根據本發明概念一些示例性實施例的半導體封裝1300。
參照圖1、圖13及圖14，根據一些實施例，虛擬半導體晶片600可設置於基板100上。虛擬半導體晶片600可被設置成與第一半導體晶片300及第二半導體晶片200橫向間隔開。虛擬半導體晶片600可與參照圖1、圖3及圖4所論述的虛擬半導體晶片600實質上相同。除了前面所提及的差異之外，根據本實施例的半導體封裝1300可與參照圖1及圖12所論述的半導體封裝1200實質上相同。
圖15及圖16說明示出根據本發明概念一些示例性實施例製作半導體封裝的方法的剖視圖。為使說明簡潔起見，將作出省略以避免對參照圖1及圖12至圖14所論述的半導體封裝1200及1300進行贅述。
參照圖15，可提供包括多個第一半導體晶片300的第一晶圓300W。第一晶圓300W可具有彼此相對的第一表面300WS1及第二表面300WS2。所述多個第一半導體晶片300中的每一者可包括與第一表面300WS1或第二表面300WS鄰近的電路層（圖中未示出），且所述電路層可包括積體電路。所述多個第一半導體晶片300中的每一者可包括與第一晶圓300W的第二表面300WS2鄰近的第一晶片焊墊310，且可更包括穿透第一半導體晶片300內部的貫通電極330。
可提供包括多個上部半導體晶片700的上部晶圓700W。上部晶圓700W可具有彼此相對的第一表面700WS1及第二表面700WS2。所述多個上部半導體晶片700可包括對應的電路層720，且電路層720可鄰近於上部晶圓700W的第一表面700WS1設置。電路層720可包括積體電路。上部半導體晶片700中的每一者可包括與上部晶圓700W的第一表面700WS1鄰近的第二晶片焊墊710。
可將上部晶圓700W設置於第一晶圓300W的第二表面300WS2上。上部晶圓700W可被設置成使得其第一表面700WS1能夠面對第一晶圓300W的第二表面300WS2。因此，第二晶片焊墊710可鄰近於第一晶片焊墊310設置。
參照圖16，熱壓製程可將第一晶片焊墊310接合至第二晶片焊墊710。第一晶片焊墊310及第二晶片焊墊710可提供第一晶圓300W與上部晶圓700W之間的直接接合，且因此，可形成其中第一晶圓300W及上部晶圓700W彼此接合的接合式結構SS。在此種情形中，上部晶圓700W的第一表面700WS1及第一半導體晶片300的第二表面300S2可彼此接觸以構成邊界B。上部晶圓700W與第一晶圓300W之間的邊界B可包含第一晶片焊墊310之間及第二晶片焊墊710之間的無機介電材料（例如，氧化矽）。
在形成接合式結構SS之後，可在第一晶圓300W的第一表面300WS1上形成第一凸塊360。所述多個第一半導體晶片300中的每一者的貫通電極330可連接至第一凸塊360中對應的第一凸塊。
切割製程SP可將接合式結構SS分離成多個晶片堆疊CS。切割製程SP可將第一晶圓300W分離成所述多個第一半導體晶片300，且亦可將上部晶圓700W分離成所述多個上部半導體晶片700。晶片堆疊CS中的每一者可包括第一半導體晶片300、上部半導體晶片700及形成於第一半導體晶片300中的每一者上的對應的第一凸塊360。
返回參照圖1及圖12，可將晶片堆疊CS中對應的晶片堆疊設置於基板100上。對應的晶片堆疊CS可在基板100上被安裝成使得第一凸塊360可接觸對應的第一基板焊墊110。可將第二半導體晶片200安裝於基板100上，且半導體封裝1200可由基板100、第二半導體晶片200及對應的晶片堆疊CS構成。根據一些實施例，如參照圖13及圖14所論述，可將虛擬半導體晶片600設置於基板100上，且半導體封裝1300可由基板100、第二半導體晶片200、對應的晶片堆疊CS及虛擬半導體晶片600構成。
圖17說明根據本發明概念一些示例性實施例的半導體封裝1400的平面圖。
參照圖17，第一半導體晶片300及多個第二半導體晶片200可設置於基板100上。所述多個第二半導體晶片200中的每一者可與第一半導體晶片300橫向間隔開。除了第二半導體晶片200的數目或者第一半導體晶片300及第二半導體晶片200的平面佈置之外，根據本實施例的半導體封裝1400可被配置成與參照圖1至圖4及圖12至圖14所論述的半導體封裝1000、1100、1200及1300實質上相同。
圖18說明示出根據本發明概念一些示例性實施例的半導體封裝1500的平面圖。圖19說明沿著圖18所示線I-I’截取的剖視圖。為使說明簡潔起見，以下將著重於與以上參照圖1及圖2所論述的半導體封裝1000的差異。
參照圖18及圖19，基板100上可設置有第一半導體晶片300a、第二半導體晶片200及第三半導體晶片300b。根據一些實施例，第一半導體晶片300a及第三半導體晶片300b中的每一者可與第二半導體晶片200橫向間隔開。基板100及第二半導體晶片200可與參照圖1及圖2所論述的基板100及第二半導體晶片200實質上相同。
虛擬晶片400可堆疊於第一半導體晶片300a上，且上部半導體晶片700可堆疊於第三半導體晶片300b上。第一半導體晶片300及虛擬晶片400可藉由夾置於其之間的介電層500彼此直接接合。第一半導體晶片300a及虛擬晶片400可與參照圖1及圖2所論述的第一半導體晶片300及虛擬晶片400實質上相同。第三半導體晶片300b及上部半導體晶片700可藉由第三半導體晶片300b的第一晶片焊墊310及藉由上部半導體晶片700的第二晶片焊墊710彼此直接接合。第三半導體晶片300b及上部半導體晶片700可與參照圖1及圖12所論述的第一半導體晶片300及上部半導體晶片700實質上相同。
根據本實施例，半導體封裝1500可由上面堆疊有第一半導體晶片300a的基板100、堆疊於第一半導體晶片300a上的虛擬晶片400、第二半導體晶片200、第三半導體晶片300b以及堆疊於第三半導體晶片300b上的上部半導體晶片700構成。
圖20說明示出根據本發明概念一些示例性實施例的半導體封裝1600的剖視圖。為使說明簡潔起見，以下將著重於與以上參照圖1及圖2所論述的半導體封裝1000的差異。
參照圖20，第二基板100可設置於第一基板900上。
第一基板900可例如為印刷電路板。第一基板900可包括導電焊墊910，且導電焊墊910可鄰近於第一基板900的頂表面900U設置。外部端子915可設置於第一基板900的底表面900L上，且導電焊墊910可藉由第一基板900中的內部線路電性連接至外部端子915。
第二基板100可設置於第一基板900的頂表面900U上。第二基板100可與參照圖1及圖2所論述的基板100實質上相同。第二基板100可藉由下部凸塊130電性連接至第一基板900。下部凸塊130可連接至對應的導電焊墊910。下部底填充層920可設置於第一基板900與第二基板100之間，且可覆蓋下部凸塊130。下部底填充層920可包含介電樹脂。
第一半導體晶片300及第二半導體晶片200可設置於第二基板100上。第一半導體晶片300及第二半導體晶片200可與參照圖1及圖2所論述的第一半導體晶片300及第二半導體晶片200實質上相同。第一半導體晶片300可藉由第一凸塊360電性連接至第二基板100，且第二半導體晶片200可藉由第二凸塊260電性連接至第二基板100。
上部底填充層930可設置於第一半導體晶片300與第二基板100之間，藉此覆蓋第一凸塊360，且亦可設置於第二半導體晶片200與第二基板100，藉此覆蓋第二凸塊260。上部底填充層930可包含介電樹脂。
根據一些實施例，虛擬晶片400可堆疊於第一半導體晶片300上。介電層500可提供第一半導體晶片300與虛擬晶片400之間的直接接合。第一半導體晶片300及虛擬晶片400可與參照圖1及圖2所論述的第一半導體晶片300及虛擬晶片400實質上相同。根據其他實施例，第二基板100上可安裝有參照圖3、圖4及圖12至圖14所論述的多個晶片。
熱輻射結構960可設置於第一基板900上，且可覆蓋第二基板100、第一半導體晶片300及第二半導體晶片200以及虛擬晶片400。熱輻射結構960可包含導熱材料。所述導熱材料可包括金屬材料（例如，銅及/或鋁）或含碳材料（例如，石墨烯、石墨及/或碳奈米管）。例如，熱輻射結構960可包括單個金屬層或多個堆疊式金屬層。對於另一實例，熱輻射結構960可包括散熱器或熱管。對於另一實例，熱輻射結構960可被配置成使用水冷卻。
導熱層950可設置於虛擬晶片400的及第二半導體晶片200的頂表面上。導熱層950可夾置於熱輻射結構960與虛擬晶片400的頂表面之間以及熱輻射結構960與第二半導體晶片200的頂表面之間。導熱層950可包含熱介面材料（thermal interface material，TIM）。熱介面材料可例如包括聚合物及導熱顆粒。導熱顆粒可分佈於聚合物中。自第一半導體晶片300及第二半導體晶片200產生的熱可藉由導熱層950傳遞至熱輻射結構960。
根據本發明概念，第一半導體晶片300上可設置有虛擬晶片400或上部半導體晶片700。在此種情形中，虛擬晶片400或上部半導體晶片700可補償第一半導體晶片300的頂表面與第二半導體晶片200的頂表面之間的高度差，且因此可輕易地形成導熱層950。
第一半導體晶片300及虛擬晶片400可藉由包含無機介電材料的介電層500彼此直接接合，或者第一半導體晶片300及上部半導體晶片700可藉由晶片焊墊之間的直接接觸而彼此直接接合。在此種情形中，第一半導體晶片300及虛擬晶片400或上部半導體晶片700可在晶圓級接合製程中輕易地彼此接合。另外，因介電層500的材料及晶片焊墊的佈置，自第一半導體晶片300產生的熱可被輕易地排放。
因此，可提供一種其中多個半導體晶片被輕易地安裝且熱輻射得以改良的半導體封裝。
前述說明提供用於闡釋本發明概念的一些示例性實施例。因此，本發明概念並非僅限於以上所述的實施例，且此項技術中具有通常知識者將理解，在不背離本發明概念的精神及特徵的條件下，可在形式及細節上作出變化。
100:基板/第二基板 100L、900L:底表面 100U、900U:頂表面 110:第一基板焊墊 120:第二基板焊墊 130:下部凸塊 200:第二半導體晶片/第二記憶體晶片 200S1、300S1、300WS1、400S1、400WS1、600S1、700S1、700WS1:第一表面 200S2、300S2、300WS2、400S2、400WS2、600S2、700S2、700WS2:第二表面 200T、300T、400WT、500T、600T:厚度 210、220、230:子半導體晶片 240:連接凸塊 250、330:貫通電極 260:第二凸塊 300、300a:第一半導體晶片 300b:第三半導體晶片 300W:第一晶圓 310:第一晶片焊墊 320、720:電路層 360:第一凸塊 370:保護膜 400:虛擬晶片 400W:虛擬晶圓 500:介電層 510:第一介電層 520:第二介電層 600:虛擬半導體晶片 660:虛擬凸塊 665:黏合層 700:上部半導體晶片 700W:上部晶圓 710:第二晶片焊墊 900:第一基板 910:導電焊墊 915:外部端子 920:下部底填充層 930:上部底填充層 950:導熱層 960:熱輻射結構 1000、1100、1200、1300、1400、1500、1600:半導體封裝 B:邊界 BG:輪磨製程 CS:晶片堆疊 I-I’:線 HC:熱壓製程 SP:切割製程 SS:接合式結構
圖1說明示出根據本發明概念一些示例性實施例的半導體封裝的平面圖。 圖2說明沿著圖1所示線I-I’截取的剖視圖。 圖3及圖4說明沿著圖1所示線I-I’截取的剖視圖，其各自示出根據本發明概念一些示例性實施例的半導體封裝。 圖5至圖7說明示出根據本發明概念一些示例性實施例製作半導體封裝的方法的剖視圖。 圖8至圖11說明示出根據本發明概念一些示例性實施例製作半導體封裝的方法的剖視圖。 圖12說明沿著圖1所示線I-I’截取的剖視圖，其示出根據本發明概念一些示例性實施例的半導體封裝。 圖13及圖14說明沿著圖1所示線I-I’截取的剖視圖，其各自示出根據本發明概念一些示例性實施例的半導體封裝。 圖15及圖16說明示出根據本發明概念一些示例性實施例製作半導體封裝的方法的剖視圖。 圖17說明示出根據本發明概念一些示例性實施例的半導體封裝的平面圖。 圖18說明示出根據本發明概念一些示例性實施例的半導體封裝的平面圖。 圖19說明沿著圖18所示線I-I’截取的剖視圖。 圖20說明示出根據本發明概念一些示例性實施例的半導體封裝的剖視圖。
100:基板
100L:底表面
100U:頂表面
110:第一基板焊墊
120:第二基板焊墊
130:下部凸塊
200:第二半導體晶片/第二記憶體晶片
200S1、300S1、400S1:第一表面
200S2、300S2、400S2:第二表面
200T、300T、500T:厚度
210、220、230:子半導體晶片
240:連接凸塊
250:貫通電極
260:第二凸塊
300:第一半導體晶片
310:第一晶片焊墊
320:電路層
360:第一凸塊
400:虛擬晶片
500:介電層
1000:半導體封裝
I-I’:線

Claims (20)

  1. 一種半導體封裝，包括： 基板； 第一半導體晶片，在所述基板上； 第二半導體晶片，在所述基板上，所述第二半導體晶片與所述第一半導體晶片橫向間隔開，所述第二半導體晶片被佈置成使得所述第一半導體晶片的頂表面低於所述第二半導體晶片的頂表面； 虛擬晶片，在所述第一半導體晶片上；以及 介電層，在所述第一半導體晶片與所述虛擬晶片之間， 所述介電層包含無機介電材料。
  2. 如請求項1所述的半導體封裝，其中所述第一半導體晶片的厚度小於所述第二半導體晶片的厚度。
  3. 如請求項1所述的半導體封裝，其中所述第一半導體晶片及所述第二半導體晶片是彼此不同的半導體晶片。
  4. 如請求項1所述的半導體封裝，其中 所述第二半導體晶片包括在與所述基板的頂表面垂直的方向上堆疊的多個子半導體晶片，且 所述第一半導體晶片的所述頂表面低於所述子半導體晶片中最上部的子半導體晶片的頂表面。
  5. 如請求項4所述的半導體封裝，其中所述第二半導體晶片包括穿透所述多個子半導體晶片的多個貫通電極。
  6. 如請求項4所述的半導體封裝，其中所述多個子半導體晶片包括多個記憶體晶片。
  7. 如請求項1所述的半導體封裝，其中 所述介電層在所述第一半導體晶片的所述頂表面上， 所述第一半導體晶片的底表面鄰近於所述基板，且 所述第一半導體晶片包括與所述第一半導體晶片的所述底表面鄰近的電路層。
  8. 如請求項7所述的半導體封裝，其中所述虛擬晶片不具有電路層。
  9. 如請求項1所述的半導體封裝，其中所述介電層包含氧化矽、氮化矽及碳氮化矽中的一或多種。
  10. 如請求項1所述的半導體封裝，更包括： 多個第一凸塊，在所述基板與所述第一半導體晶片的底表面之間，所述第一凸塊將所述基板連接至所述第一半導體晶片；以及 多個第二凸塊，在所述基板與所述第二半導體晶片的底表面之間，所述第二凸塊將所述基板連接至所述第二半導體晶片， 其中所述介電層在所述第一半導體晶片的所述頂表面上。
  11. 如請求項1所述的半導體封裝，其中所述基板是中介層基板。
  12. 如請求項1所述的半導體封裝，更包括： 虛擬半導體晶片，在所述基板上，所述虛擬半導體晶片與所述第一半導體晶片及所述第二半導體晶片橫向間隔開。
  13. 如請求項1所述的半導體封裝，更包括： 第三半導體晶片，在所述基板上，所述第三半導體晶片與所述第一半導體晶片及所述第二半導體晶片橫向間隔開；以及 上部半導體晶片，在所述第三半導體晶片上， 其中所述第三半導體晶片的頂表面低於所述第二半導體晶片的所述頂表面。
  14. 如請求項13所述的半導體封裝，其中 所述上部半導體晶片的底表面面對所述第三半導體晶片的所述頂表面， 所述第三半導體晶片包括與所述第三半導體晶片的所述頂表面鄰近的多個第一晶片焊墊， 所述上部半導體晶片包括與所述上部半導體晶片的所述底表面鄰近的多個第二晶片焊墊，且 所述多個第一晶片焊墊直接連接至所述多個第二晶片焊墊。
  15. 如請求項14所述的半導體封裝，其中 所述第三半導體晶片包括穿透所述第三半導體晶片內部的多個貫通電極， 所述多個貫通電極連接至所述多個第一晶片焊墊中對應的晶片焊墊。
  16. 如請求項15所述的半導體封裝，其中所述多個第一晶片焊墊中的至少一者與所述多個貫通電極電性分離。
  17. 如請求項14所述的半導體封裝，其中所述上部半導體晶片包括與所述上部半導體晶片的所述底表面鄰近的電路層。
  18. 一種半導體封裝，包括： 第一基板； 第二基板，在所述第一基板上並電性連接至所述第一基板； 第一半導體晶片，在所述第二基板上； 第二半導體晶片，在所述第二基板上，所述第二半導體晶片與所述第一半導體晶片橫向間隔開，所述第二半導體晶片被佈置成使得所述第一半導體晶片的頂表面低於所述第二半導體晶片的頂表面； 虛擬晶片，在所述第一半導體晶片上；以及 介電層，在所述第一半導體晶片與所述虛擬晶片之間，所述介電層包含無機介電材料。
  19. 如請求項18所述的半導體封裝，更包括： 熱輻射結構，在所述第一基板上，所述熱輻射結構覆蓋所述第二基板、所述第一半導體晶片、所述第二半導體晶片及所述虛擬晶片；以及 導熱層，在所述熱輻射結構與所述虛擬晶片的頂表面之間，所述導熱層在所述熱輻射結構與所述第二半導體晶片的所述頂表面之間。
  20. 如請求項18所述的半導體封裝，其中所述虛擬晶片的頂表面及所述第二半導體晶片的所述頂表面相對於所述第二基板處於實質上相同的高度。
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