TW202410334A - 半導體封裝 - Google Patents
半導體封裝 Download PDFInfo
- Publication number
- TW202410334A TW202410334A TW112127783A TW112127783A TW202410334A TW 202410334 A TW202410334 A TW 202410334A TW 112127783 A TW112127783 A TW 112127783A TW 112127783 A TW112127783 A TW 112127783A TW 202410334 A TW202410334 A TW 202410334A
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- semiconductor
- pad
- insulating layer
- layer
- semiconductor chip
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 480
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Abstract
本發明提供一種半導體封裝,包含:第一半導體晶片;多個第二半導體晶片,堆疊於第一半導體晶片上且分別具有窄於第一半導體晶片的寬度的寬度;以及模製層,位於第一半導體晶片的上部表面上。第一半導體晶片包含:第一正面襯墊;第一背面絕緣層,分為第一區及第二區,第一背面襯墊位於第一區中,虛設襯墊位於第二區中,虛設襯墊中的各者具有上面安置有金屬氧化物膜的上部表面;以及第一貫通電極,將第一正面襯墊與第一背面襯墊彼此電連接。多個第二半導體晶片中的各者包含:第二正面襯墊;第二背面襯墊;以及第二貫通電極,將第二正面襯墊與第二背面襯墊彼此電連接。
Description
[相關申請案的交叉參考]
本申請案主張2022年7月26日在韓國智慧財產局申請的韓國專利申請案第10-2022-0092676號的優先權,所述申請案的揭露內容以全文引用的方式併入本文中。
本發明是關於一種半導體封裝。
根據電子工業的發展及使用者的需求,電子裝置的尺寸及重量已經減小,且使用於電子裝置中的半導體封裝可能需要在減小尺寸及重量的同時提供高效能及高電容。為了在減小尺寸及重量的同時實現高效能及高電容,半導體晶片(包含矽通孔(through-silicon via;TSV)及半導體晶片堆疊其中的半導體封裝)已經不斷地進行研究及開發。
本發明的態樣提供一種半導體封裝,所述半導體封裝具有能夠保證半導體晶片之間的連接的改良可靠性且具有總體較強的接合強度。
根據本發明的態樣,提供一種半導體封裝,包含:第一半導體晶片;多個第二半導體晶片,堆疊於第一半導體晶片上且分別具有窄於第一半導體晶片的寬度的寬度;以及模製層,位於第一半導體晶片的上部表面上及多個第二半導體晶片的側表面上。第一半導體晶片可包含:第一半導體基底;第一半導體裝置層,位於第一半導體基底的正面上;第一正面襯墊,位於第一半導體裝置上;第一背面絕緣層,位於第一半導體基底的背面上且分成第一區及第二區;第一背面襯墊,位於第一背面絕緣層的第一區中;虛設襯墊,位於第一背面絕緣層的第二區中,其中虛設襯墊中的各者具有上面有金屬氧化物膜的上部表面;以及第一貫通電極,延伸穿過第一半導體基底且將第一正面襯墊與第一背面襯墊彼此電連接。多個第二半導體晶片中的各者可包含:第二半導體基底;第二半導體裝置層,位於第二半導體基底的正面上;第二正面絕緣層,位於第二半導體裝置層上;第二正面襯墊,位於第二正面絕緣層中;第二背面絕緣層,位於第二半導體基底的背面上;第二背面襯墊,位於第二背面絕緣層中;以及第二貫通電極,延伸穿過第二半導體基底且將第二正面襯墊與第二背面襯墊彼此電連接。多個第二半導體晶片當中的最下部第二半導體晶片的第二正面絕緣層可接合至第一背面絕緣層。最下部第二半導體晶片的第二正面襯墊可分別接合至第一背面襯墊。
根據本發明的另一態樣,提供一種半導體封裝,包含:基礎結構,具有分成第一區及第二區的上部表面,且包含上部表面上的基礎絕緣層、以基礎絕緣層為邊界且配置於第一區上的連接襯墊以及以基礎絕緣層為邊界且配置於第二區上的虛設襯墊,其中虛設襯墊中的各者具有上面安置有金屬氧化物膜的上部表面;至少一個半導體晶片,位於基礎結構的第一區上,且包含半導體基底、位於半導體基底的正面上的半導體裝置層、位於半導體裝置層上且接合至第一區中的基礎絕緣層的正面絕緣層以及以正面絕緣層為邊界且分別接合至連接襯墊的正面襯墊;以及模製層,位於基礎結構上且與至少一個半導體晶片的側表面毗鄰。
根據本發明的另一態樣,提供一種半導體封裝,包含:第一半導體晶片,具有上部表面及下部表面,其中上部表面分成第一區及與第一區毗鄰的第二區;多個第二半導體晶片,堆疊於第一半導體晶片的上部表面的第一區上且屬於不同於第一半導體晶片的類型的相同類型;以及模製層,位於第一半導體晶片上且與多個第二半導體晶片的側表面毗鄰。第一半導體晶片可包含:保護層,位於第一半導體晶片的下部表面上;外部連接襯墊,安置於保護層上;第一上部絕緣層,位於第一半導體晶片的上部表面上;第一上部襯墊,位於第一上部絕緣層中的上部表面的第一區上;虛設襯墊,位於第一上部絕緣層中的上部表面的第二區上;以及金屬氧化物膜,分別位於虛設襯墊上。多個第二半導體晶片中的各者可包含:半導體基底;半導體裝置層,位於半導體基底的正面上;正面絕緣層,位於半導體裝置層上;正面襯墊,安置於正面絕緣層中;背面絕緣層,位於半導體基底的背面上;背面襯墊,位於背面絕緣層中;以及貫通電極,延伸穿過半導體基底且將正面襯墊與背面襯墊彼此電連接。多個第二半導體晶片當中的最下部第二半導體晶片的正面絕緣層可接合至第一上部絕緣層,且最下部第二半導體晶片的正面襯墊可分別接合至第一上部襯墊。
當半導體晶片安裝於尺寸相對較大的基礎結構(例如,晶片或基底)上時,可在未安裝的上部表面區中形成虛設襯墊(例如,Cu)以改良基礎結構的接合表面的平坦化品質。此外,金屬氧化物膜(例如,Cu氧化物)可安置於虛設襯墊上,從而改良歸因於虛設襯墊的引入而導致的與模製層(例如,環氧樹脂模製化合物(epoxy molding compound;EMC))接合強度降低的可靠性問題。
示例性實施例的各種有益優勢及效應不限於上述描述,且在描述特定示例性實施例期間會更易於理解。
在下文中,將參考隨附圖式描述本發明的示例性實施例。然而,本發明可以許多不同形式體現且不應解釋為限於本文中所闡述的實施例。在整個申請案中,相同附圖標號指相同元件。如本文中所用,術語「及/或」包含相關聯的所列項目中的一或多個的任何及所有組合。應注意,儘管並未相對於不同實施例具體地描述一個實施例,但關於一個實施例所描述的態樣可併入於所述不同實施例中。亦即,所有實施例及/或任何實施例的特徵可以任何方式及/或組合進行組合。
圖1為示出根據本發明的示例性實施例的半導體封裝的側橫截面圖。圖2及圖3分別為示出圖1的半導體封裝的部分「A1」及部分「A2」的部分放大視圖。
參看圖1,根據本發明示例性實施例的半導體封裝500可包含基礎結構200及安置於基礎結構200上的晶片堆疊CS1。晶片堆疊CS1可包含在垂直於基礎結構200的上部表面的方向上堆疊的第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C,以及第四半導體晶片100D。
在本發明示例性實施例中,基礎結構200可具有上部表面,所述上部表面分成其中安置有晶片堆疊CS1的第一區及圍繞第一區的第二區。如圖4中所示出,當在平面視圖中查看時,第二區可安置成毗鄰或包圍第一區。特定而言,第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D可具有相同面積,而基礎結構200的面積可大於半導體晶片的面積。基礎絕緣層264亦可具有未由半導體晶片覆蓋或無半導體晶片的區。
基礎結構200可包含安置於其上部表面上的基礎絕緣層264、安置於基礎絕緣層264中的第一區上的連接襯墊254以及安置於基礎絕緣層264中的第二區上的虛設襯墊256。
在半導體封裝500的平面視圖中,連接襯墊254及虛設襯墊256可分別安置成與基礎絕緣層264毗鄰或由其包圍。連接襯墊254可具有與基礎絕緣層264的上部表面實質上共面的上部表面。連接襯墊254可配置成對應於多個半導體晶片當中的最下部半導體晶片(即,第一半導體晶片100A)的正面襯墊152。類似地,第一半導體晶片100A的正面襯墊152可具有與正面絕緣層162的上部表面實質上共面的上部表面。共面的上部表面可提供為基礎結構200及第一半導體晶片100A的接合表面。
參考圖2,基礎結構200的上部表面及第一半導體晶片100A的下部表面可直接彼此接合。特定而言,基礎結構200的連接襯墊254及第一半導體晶片100A的正面襯墊152可直接彼此接合以形成金屬對金屬接合(在下文中稱作「金屬接合」)DB1。因此,基礎結構200及第一半導體晶片100A可機械地固定至彼此,且在基礎結構200與第一半導體晶片100A之間形成電連接。
連接襯墊254及正面襯墊152可分別包含相同金屬,例如,銅(Cu)。彼此直接接觸的連接襯墊254及正面襯墊152可藉由經由高溫退火製程的銅相互擴散而彼此接合。連接襯墊254及正面襯墊152中包含的金屬不限於銅,且根據不同實施例可包含任何可相互耦合的材料(例如,Au)。
經由金屬接合DB1,基礎結構200及第一半導體晶片100A可彼此牢固地接合,且可實現電/機械連接而無需導電凸塊(例如,微凸塊)。用於傳輸及接收控制信號、電力信號、接地信號及/或資料信號的路徑可設置於基礎結構200與第一半導體晶片100A之間。路徑可不必穿過導電凸塊,從而減少傳輸損失。
以與金屬接合DB1類似的方式,基礎絕緣層264可直接接合至定位於第一半導體晶片100A的下部表面上的正面絕緣層162以形成介電質對介電質接合(在下文中稱作「介電質接合」)DB2。
基礎結構200的基礎絕緣層264及第一半導體晶片100A的正面絕緣層162可由相同材料形成。舉例而言,基礎絕緣層264及正面絕緣層162可包含氧化矽。在基礎絕緣層264及正面絕緣層162彼此直接接觸的狀態下,可進行高溫退火製程。基礎絕緣層264及正面絕緣層162可藉由共價接合彼此牢固地接合。基礎絕緣層264及正面絕緣層162中包含的介電材料不限於氧化矽,且根據不同實施例可包含任何可相互耦合的材料(例如,SiCN)。
因此,在本發明示例性實施例中,基礎結構200與第一半導體晶片100A之間的接合可具有基礎絕緣層264與正面絕緣層162之間的介電質接合DB2,以及連接襯墊254與正面襯墊152之間的金屬接合DB1,且此類接合可稱為「混合接合」。
如上所述,在基礎結構200的上部表面上,虛設襯墊256可配置於圍繞晶片堆疊CS1的區上(亦即,在第二區上)。虛設襯墊256可為不電連接至基礎結構200的固有配線的襯墊。以與上面安置有連接襯墊254的第一區類似的方式,虛設襯墊256可形成於第二區上,從而減少或防止在接合表面的平坦化製程期間歸因於襯墊密度的差異的局部介電質侵蝕。因此,基礎結構200的接合表面(亦即,上部表面)的平坦化品質可改良,從而可提供極佳的直接接合,其中在接合界面處不會出現非所要空隙。虛設襯墊256可以與連接襯墊254相同的製程製造。在一些示例性實施例中,虛設襯墊256可包含與連接襯墊254相同的金屬。舉例而言,虛設襯墊256及連接襯墊254可分別包含銅。
參考圖2及圖3,金屬氧化物膜257可形成於虛設襯墊256中的各者上。金屬氧化物膜257可與模製層180直接接觸。模製層180可形成於基礎結構200上以密封晶片堆疊CS1的至少一部分。在本發明示例性實施例中,模製層180可形成為毗鄰或包圍晶片堆疊CS1的側表面,以便打開晶片堆疊CS1的上部表面。本發明示例性實施例中使用的模製層180可包含由單一材料形成的單一或單體結構。舉例而言,模製層180可包含環氧樹脂模製化合物(EMC)。如圖3中所示出,模製層180可安置於基礎結構200上,且可具有與基礎結構200的側表面實質上共面的側表面。共面的側表面可理解為藉由相同切割製程得到的側表面。
虛設襯墊256可由具有實質上平坦的上部表面的金屬材料形成,使得與模製層180(諸如EMC)的接合強度可相對較低。特定而言,歸因於集中在基礎結構200、第一半導體晶片100A以及模製層180相接的三交點處的壓力,可自基礎結構200的上部表面的第二區剝掉模製層180。因此,為了平坦化品質引入的虛設襯墊256可充當誘發此剝落的因素。
為了解決此問題,金屬氧化物膜257可安置於虛設襯墊256上。因此,替代虛設襯墊256,金屬氧化物膜257可經組態以與模製層180直接接觸,從而增加基礎結構200的第二區與模製層180之間的接合強度。改良接合強度的效果可視金屬氧化物膜257的厚度t而變化。
圖5為示出根據虛設襯墊上的金屬氧化物膜的厚度的模製層與虛設襯墊上的金屬氧化物膜之間的接合強度的曲線圖(來源:導線框氧化對於氧化銅對環氧樹脂模製化合物-銅界面的黏著行為的Cu/EMC界面黏著效應的影響(The Influence of Leadframe oxidation on the Cu/EMC Interface Adhesion Effect of copper oxide on the adhesion behavior of Epoxy Molding Compound-Copper Interface),IEEE 2002)。
特定而言,圖5示出根據在不同溫度(150℃、200℃以及300℃)下銅虛設襯墊256上的氧化銅膜257的平均厚度的EMC模製層180與銅虛設襯墊256上的氧化銅膜257之間的接合強度的變化。
在金屬氧化物膜257的厚度t為約80奈米或小於80奈米時,通常展現高接合強度。為了穩定的改良效果(最小厚度),金屬氧化物膜257的厚度t可在約5奈米至約80奈米範圍內。在一些示例性實施例中,可藉由將金屬氧化物膜257的厚度t調整為約10奈米至約40奈米而獲得相對高的接合強度。
金屬氧化物膜257可包含含有虛設襯墊256中包含的金屬的氧化物。舉例而言,在一系列堆疊製程中,可暴露虛設襯墊256且可將金屬氧化物膜257理解為藉由使氧氣與虛設襯墊256的金屬接觸來進行反應而形成的產物(參見圖12B及圖12C)。在一些示例性實施例中,如上所述,連接襯墊254可具有與基礎絕緣層264的上部表面共面的上部表面。相反地,如圖3中所示出,金屬氧化物膜257的上部表面(參見圖12C中的257T)的層級L2可高於基礎絕緣層264的上部表面的層級L0。虛設襯墊的一些金屬可在形成金屬氧化物膜的同時進行反應,使得金屬氧化物膜的下部表面(參見圖12C中的256T')的層級L1可低於基礎絕緣層264的上部表面的層級L0。在一些示例性實施例中,金屬氧化物膜257可具有相對較小的厚度,且因此可能難以比較及測定層級。
在本發明示例性實施例中,如圖4中所示出,虛設襯墊256的尺寸及間距的配置可與連接襯墊254的尺寸及間距的配置實質上相同。亦即,虛設襯墊256的密度(例如,第二區中每單位面積虛設襯墊的數目)可實質上等於連接襯墊254的密度(例如,第一區中每單位面積連接襯墊的數目)。在一些示例性實施例中,虛設襯墊256的尺寸及間距中的至少一者可配置成在預定範圍內不同於連接襯墊254的尺寸及間距(參見圖8及圖11)。
晶片堆疊CS1中包含的第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D可分別具有彼此相對的正面(或「下部表面」)及背面(或「上部表面」),且可經堆疊使得不同表面(亦即,背面及正面)彼此相對。第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D可包含半導體基底110、半導體裝置層120、貫通電極130、正面襯墊152以及背面襯墊154。然而,如在本發明示例性實施例中,安置於最上部層級上的半導體晶片(亦即,第四半導體晶片100D)可不包含貫通電極130。
參考圖1及圖2,半導體裝置層120可安置於各半導體基底110的下部表面110A上。舉例而言,半導體基底110可包含矽或諸如SiC、SiGe或GaAs的化合物半導體。半導體基底110可具有導電區,例如,摻雜有雜質的井,或上面形成摻雜有雜質的結構的主動表面。此外,半導體基底110可具有各種裝置隔離結構,諸如淺溝槽隔離(shallow trench isolation;STI)結構。
半導體裝置層120可形成為包含形成於半導體基底110的主動表面上的多個個別裝置及配線層145。配線層145可包含金屬配線層142及通孔143,且可在配線絕緣層141中形成。舉例而言,配線層145可為多層配線,兩個或多於兩個金屬配線層142及/或兩個或多於兩個通孔143交替地堆疊於其中。配線層145可連接至安置於第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D中的各者的正面上的正面襯墊152。
貫通電極130可形成為通過或延伸穿過半導體基底110。貫通電極130的至少一部分可具有支柱形狀。貫通電極130可包含通孔插塞135及包圍通孔插塞135的側面絕緣膜131。側面絕緣膜131可將通孔插塞135與半導體基底110及半導體裝置層120電隔離。如上所述,安置於最上部層級上的第四半導體晶片100D可不包含貫通電極130。貫通電極130可連接至安置於第一半導體晶片100A、第二半導體晶片100B以及第三半導體晶片100C中的各者的背面上的背面襯墊154。此外,貫通電極130可連接至與正面襯墊152連接的配線層145。
因此,在第一半導體晶片100A、第二半導體晶片100B以及第三半導體晶片100C中的各者中,貫通電極130可將正面襯墊152及背面襯墊154彼此電連接。
第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D可藉由上述相鄰半導體晶片之間的混合接合而彼此堆疊。
特定而言,第一半導體晶片100A、第二半導體晶片100B以及第三半導體晶片100C的背面襯墊154可分別直接接合至第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D的正面襯墊152。特定而言,如圖1中所示出,背面襯墊154及正面襯墊152可在相鄰的第一半導體晶片100A與第二半導體晶片100B之間直接彼此接合以提供金屬接合,從而將第一半導體晶片100A及第二半導體晶片100B彼此固定且在第一半導體晶片100A與第二半導體晶片100B之間形成電連接。類似地,背面襯墊154與正面襯墊152之間的金屬接合可形成於第二半導體晶片100B與第三半導體晶片100C之間,及第三半導體晶片100C與第四半導體晶片100D之間形成。
背面襯墊154及正面襯墊152可包含相同金屬,例如,銅(Cu)。彼此直接接觸的背面襯墊154及正面襯墊152可藉由經由高溫退火製程的銅相互擴散而彼此耦接。背面襯墊154及正面襯墊152中包含的金屬不限於銅,且根據不同實施例可包含任何可相互耦接的材料(例如,Au)。
經由金屬接合,經堆疊的半導體晶片可彼此牢固地接合,且可實現電/機械連接而無需導電凸塊(例如,微凸塊)。用於傳輸及接收控制信號、電力信號、接地信號及/或資料信號的路徑可設置於第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D之間。路徑可不必穿過導電凸塊,從而減少傳輸損失。
在本發明示例性實施例中,以與金屬接合類似的方式,安置於第一半導體晶片100A、第二半導體晶片100B以及第三半導體晶片100C中的各者的上部表面上的背面絕緣層164及安置於第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D中的各者的下部表面上的正面絕緣層162可彼此直接接合以形成介電質接合DB2。背面絕緣層164及正面絕緣層162可由相同材料形成。舉例而言,背面絕緣層164及正面絕緣層162可包含氧化矽。在背面絕緣層164及正面絕緣層162彼此直接接觸的狀態下,可進行高溫退火製程。背面絕緣層164及正面絕緣層162可藉由共價接合彼此牢固地接合。背面絕緣層164及正面絕緣層162中包含的介電材料不限於氧化矽,且根據不同實施例可包含任何可相互耦接的材料(例如,SiCN)。
因此,在本發明示例性實施例中,可以混合接合的方式堆疊相鄰的半導體晶片。
本發明示例性實施例中使用的基礎結構200可為具有配線電路的基底或可為類型不同於第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D的類型的半導體晶片。
舉例而言,基礎結構200可為具有諸如重佈線電路的內部配線的插入件。在基礎結構200為插入件時,基礎結構200可包含將基底主體的下部表面及上部表面彼此連接的內部配線(未示出)。舉例而言,基底主體可為諸如矽的半導體。基礎結構200可包含安置於其上部表面上且連接至內部配線的連接襯墊254,及安置於其下部表面上且連接至內部配線的外部連接襯墊252,以及導電凸塊270,諸如焊料球可形成於外部連接襯墊252中的各者上。半導體封裝500可經由導電凸塊270電連接至諸如母板的外部裝置。
可經由導電凸塊270自外部或外部來源接收用於操作第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D的控制信號、電力信號及/或接地信號,可經由導電凸塊270自外部或外部來源接收要儲存在第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D中的資料信號,或可經由導電凸塊270將第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D中儲存的資料傳輸至外部或外部目的地。
第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D可為記憶體晶片或邏輯晶片。在實例中,所有第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D的類型可與記憶體晶片相同。
舉例而言,記憶體晶片可為諸如動態隨機存取記憶體(dynamic random access memory;DRAM)或靜態隨機存取記憶體(static random access memory;SRAM)的揮發性記憶體晶片,或諸如相變隨機存取記憶體(phase-change random access memory;PRAM)、磁阻式隨機存取記憶體(magnetoresistive random access memory;MRAM)、鐵電式隨機存取記憶體(ferroelectric random access memory;FeRAM)或電阻式隨機存取記憶體(resistive random access memory;RRAM)的非揮發性記憶體晶片。在一些示例性實施例中,第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D可為高頻寬記憶體(high bandwidth memory;HBM)。
此外,邏輯晶片可為例如微處理器、類比裝置或數位信號處理器。舉例而言,基礎結構200可為經組態以控制第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D的邏輯晶片。
在本發明示例性實施例中,將其中堆疊有第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D的半導體封裝500作為實例示出,但半導體封裝500中堆疊的半導體晶片的數目不限於此。舉例而言,兩個、三個或多於三個半導體晶片(例如,八個(參見圖6))可堆疊於半導體封裝500中。
如圖1中所示出,第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D可為相同類型的晶片,且可具有相同面積。在一些示例性實施例中,第一半導體晶片100A、第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D可具有不同面積。
圖6為示出根據本發明的示例性實施例的半導體封裝的側橫截面圖。圖7為示出圖6的半導體封裝中的部分「B」的部分放大視圖。圖8為示出圖6的半導體封裝中使用的基礎結構的頂部平面圖。
參考圖6至圖8,根據本發明示例性實施例的半導體封裝500A可理解為具有與圖1及圖2中所示出的示例性實施例中的結構類似的結構,不同之處在於,包含作為基礎結構引入的第一半導體晶片300,及在第一半導體晶片上依序堆疊的多個(八個)第二半導體晶片100A、100B、100C、100D、100E、100F、100G以及100H,半導體晶片(半導體晶片300及半導體晶片100A至半導體晶片100G)中的各者具有晶片虛設襯墊;且包含防熱板190。因此,除非另外規定,否則圖1及圖2中所示出的示例性實施例的描述可與本發明示例性實施例的描述組合。
在本發明示例性實施例中,尺寸大於多個經堆疊的第二半導體晶片的尺寸的第一半導體晶片300可作為基礎結構引入。舉例而言,多個經堆疊的第二半導體晶片的寬度分別窄於第一半導體晶片300的寬度。
第一半導體晶片300可包含:第一半導體基底310;安置於第一半導體基底310的正面(或下部表面)上的第一半導體裝置層320;安置於第一半導體裝置層320上的第一正面襯墊352;安置於第一半導體基底310的背面(或上部表面)上的第一背面絕緣層364;以第一背面絕緣層364為邊界或由第一背面絕緣層364包圍的第一背面襯墊(如圖6及圖7中所繪示的354中的354A)及虛設襯墊356;以及延伸穿過第一半導體基底310的第一貫通電極330。第一貫通電極330可將第一正面襯墊352與第一背面襯墊354A彼此電連接。第一半導體晶片300可更包含安置於第一半導體裝置層320上的保護層362。第一正面襯墊352可形成於保護層362上,且可電連接至第一半導體裝置層320。
第一背面絕緣層364可分成接合至第二半導體晶片100A至第二半導體晶片100G的晶片堆疊CS2的第一區及與第一區毗鄰或包圍第一區的第二區。第一背面襯墊354A可安置於第一背面絕緣層364的第一區中,且虛設襯墊356可安置於第一背面絕緣層364的第二區中。以與前述示例性實施例類似的方式,定位於第二區中的虛設襯墊356可抑制在接合表面的平坦化製程期間局部介電質侵蝕的發生。
因此,可改良第一半導體晶片300的接合表面(亦即,上部表面)的平坦化品質以提供極佳的直接接合,其中在接合界面處不會出現非所要空隙。
此外,以與上述示例性實施例類似的方式,金屬氧化物膜357可安置於虛設襯墊356的上部表面上。金屬氧化物膜357可與模製層180直接接觸。替代虛設襯墊356,金屬氧化物膜357可經組態以與模製層180直接接觸,從而增加第一半導體晶片300與模製層180之間的接合強度。
在本發明示例性實施例中,具有相同尺寸的八個第二半導體晶片100A至第二半導體100H可在第一半導體晶片300的第一區中堆疊以提供晶片堆疊CS。多個第二半導體晶片100A至第二半導體晶片100H的面積可各自小於第一半導體晶片300的面積。
多個第二半導體晶片100A至第二半導體晶片100H中的各者可包含:第二半導體基底110;安置於第二半導體基底110的正面(或下部表面)上的第二半導體裝置層120;安置於第二半導體裝置層120上的第二正面絕緣層162;安置於第二正面絕緣層162中的第二正面襯墊152A;安置於第二半導體基底110的背面(或上部表面)上的第二背面絕緣層164;安置於第二背面絕緣層164中的第二背面襯墊154A;以及延伸穿過第二半導體基底110且將第二正面襯墊152A與第二背面襯墊154A彼此電連接的第二貫通電極130。然而,安置於最上部層級上的上半導體晶片(亦即,半導體晶片100H)可不包含第二貫通電極130。在另一實施例中,半導體晶片100H可被稱為多個第二半導體晶片100A至100G當中的最上部第二半導體晶片上的第三半導體晶片。第三半導體晶片100H可包含:第三半導體基底110';位於第三半導體基底的正面的上第三半導體裝置層;位於第三半導體裝置層上且接合至最上部第二半導體晶片的第二背面絕緣層的第三正面絕緣層;以及位於第三正面絕緣層中且分別接合至最上部第二半導體晶片的第二背面襯墊的第三正面襯墊。
以與前述示例性實施例類似的方式,多個第二半導體晶片100A至100H當中的最下部第二半導體晶片100A的第二正面絕緣層162可接合至第一背面絕緣層364,且最下部第二半導體晶片100A的第二正面襯墊152A可分別接合至第一背面襯墊354A。此外,多個第二半導體晶片100A至100H中的各者的第二背面絕緣層164可接合至另一相鄰第二半導體晶片的第二正面絕緣層162,且多個第二半導體晶片100A至100H中的各者的第二背面襯墊154A可分別接合至另一相鄰半導體晶片的第二正面襯墊152A。
在本發明示例性實施例中,第一半導體晶片300可更包含安置於第一背面絕緣層364的第一區中的第一半導體基底310的背面上的第一背面虛設襯墊354B。在本發明示例性實施例中,第一背面虛設襯墊354B可安置於第一區中的第一背面襯墊354A周圍。此外,多個第二半導體晶片100A至100H可更包含安置於第二正面絕緣層162中的第二半導體基底110的正面上的第二正面虛設襯墊152B,及安置於第二背面絕緣層164中的第二半導體基底110的背面上的第二背面虛設襯墊154B。在本發明示例性實施例中,第二正面虛設襯墊152B及第二背面虛設襯墊154B可分別安置於第二正面襯墊152A及第二背面襯墊154A周圍。
第一背面虛設襯墊354B及第二正面虛設襯墊152B以及第二背面虛設襯墊154B可為不以與虛設襯墊356類似的方式電連接至各晶片的內部電路或裝置的襯墊。第一半導體晶片300的第一背面虛設襯墊354B可直接接合至最下部第二半導體晶片100A的第二正面虛設襯墊152B以確保更穩定的接合。類似地,即使在相鄰的第二半導體晶片之間,第二背面虛設襯墊154B及第二正面虛設襯墊152B亦可彼此直接接合以確保晶片堆疊CS2的更穩定接合。
在本發明示例性實施例中,晶片堆疊CS2中包含的第二半導體晶片100A至第二半導體晶片100H可為相同類型的記憶體晶片。第一半導體晶片300可為經組態以控制第二半導體晶片100A至第二半導體晶片100H的邏輯晶片。
在本發明示例性實施例中,如圖8中所示出,虛設襯墊356的間距P2可不同於第一背面襯墊354A及第一背面虛設襯墊354B的間距P1。因此,虛設襯墊356的密度(例如,第二區中每單位面積虛設襯墊的數目)可不同於第一背面襯墊354A及第一背面虛設襯墊354B的密度(例如,第一區中每單位面積第一背面襯墊354A及第一背面虛設襯墊354B的數目)。舉例而言,虛設襯墊356的密度可在第一背面襯墊354A及第一背面虛設襯墊354B的密度的約50%至約150%的範圍內。
此外,第一半導體晶片300可更包含安置於第一背面絕緣層364的第二區中的第一半導體基底310的背面上的至少一個對準鍵襯墊AK。舉例而言,本發明示例性實施例中使用的對準鍵襯墊AK可繪示為具有十字形狀,但可具有不同於虛設襯墊356的形狀及尺寸的各種形狀及尺寸。額外金屬氧化物膜357亦可安置於十字形狀的對準鍵襯墊AK上。
根據本發明示例性實施例的半導體封裝500A可更包含依序安置於最上部第二半導體晶片100H的上部表面上的導熱材料層192及防熱板190。導熱材料層192可安置於熱防板190與最上部第二半導體晶片100H之間,且可位於最上部第二半導體晶片100H的上部表面上及至少部分地覆蓋所述上部表面。導熱材料層192可幫助將半導體晶片300及半導體晶片100A至半導體晶片100H所產生的熱平穩地散發至防熱板190。導熱材料層192可由熱界面材料(thermal interface material;TIM)形成。舉例而言,導熱材料層192可由絕緣材料或能夠藉由包含絕緣材料而維持電絕緣的材料形成。導熱材料層192可包含例如環氧樹脂。導熱材料層192的具體實例可包含礦物油、滑脂、間隙填料油灰、相變凝膠、相變材料襯墊,及/或填充顆粒的環氧樹脂。
防熱板190可安置於導熱材料層192上。防熱板190可為例如散熱片、散熱器、散熱管及/或液冷式冷板。
圖9為示出根據本發明的示例性實施例的半導體封裝的側橫截面圖。圖10為示出圖9的半導體封裝中的部分「C」的部分放大視圖。圖11為示出圖9的半導體封裝中使用的基礎結構的頂部平面圖。
根據本發明示例性實施例的半導體封裝500B可理解為具有類似於圖1及圖2中所示出的示例性實施例的結構的結構,不同之處在於包含具有第一面積的第一半導體晶片200A及各自具有小於第一面積的第二面積的第二半導體晶片100,且虛設襯墊256具有窄於其他襯墊152及其他襯墊254的寬度的寬度。因此,除非另外規定,否則圖1及圖2中所示出的示例性實施例的描述可與本發明示例性實施例的描述組合。
第一半導體晶片200A可具有大於第二半導體晶片100的面積的面積,且第一半導體晶片200A及第二半導體晶片100可為不同類型的半導體晶片。第一半導體晶片200A及第二半導體晶片100可具有分別類似於圖6及圖7中所示出的第一半導體晶片300及第二半導體晶片100A至第二半導體晶片100H的組件的組件。
在本發明示例性實施例中,第一半導體晶片200A可包含:安置於第一半導體基底210的上部表面上的配線結構240;延伸穿過第一半導體基底210且連接至配線結構240的配線層245及外部連接襯墊252的第一貫通電極230;安置於配線結構240上的第一背面絕緣層264;以及分別連接至第一背面絕緣層264中的配線層245的第一背面襯墊254。
第二半導體晶片100可包含:第二半導體基底110;安置於第二半導體基底110的正面上的半導體裝置層120;安置於半導體裝置層120上且接合至第一背面絕緣層264的第二正面絕緣層162;以及連接至半導體裝置層120中的配線層145且接合至第一背面襯墊254的第二正面襯墊152。因此,當額外半導體晶片不堆疊於第二半導體晶片100的上部表面上時,第二半導體晶片100可能不更包含貫通電極及背面襯墊。
此外,第一半導體晶片200A可在圍繞第二半導體晶片100的其上部表面區中包含虛設襯墊256。金屬氧化物膜257可形成於虛設襯墊256的上部表面上。金屬氧化物膜257可與模製層180直接接觸以確保強接合。
在本發明示例性實施例中,如圖11中所示出,虛設襯墊256的寬度W2可不同於第一背面襯墊254的寬度W1。因此,虛設襯墊256的密度可不同於第一背面襯墊254的密度。舉例而言,虛設襯墊256的密度可在第一背面襯墊254的密度的約50%至約150%的範圍內。
圖12A至圖12D為示出製造根據本發明的示例性實施例的半導體封裝的方法的主製程的橫截面視圖。
參考圖12A,可製備用於多個基礎結構200的半導體晶圓200W。
半導體晶圓200W示出為包含兩個基礎結構200。各基礎結構200可包含安置於其下部表面上的外部連接襯墊252、安置於其上部表面上的基礎絕緣層264、安置於基礎絕緣層264中的連接襯墊254,以及虛設襯墊256。連接襯墊254可安置於安裝區(例如,第一區)中,且虛設襯墊256可安置於安裝區的周邊區(例如,第二區)中。
上面形成一或多個導電凸塊270的半導體晶圓200W可藉由黏接層620附接至載體基底610。半導體晶圓200W可附接至載體基底610上,使得導電凸塊270面向載體基底610。導電凸塊270可由黏接層620覆蓋。上面不形成導電凸塊270的半導體晶圓200W的下部表面的部分可接合至黏接層620以在後續製程期間穩定支撐。
在本操作中,連接襯墊254可具有與背面絕緣層264的上部表面264T實質上共面的上部表面254T。類似地,虛設襯墊256可具有與背面絕緣層264的上部表面264T實質上共面的上部表面256T。共面的上部表面可藉由平坦化製程(諸如CMP製程)形成。
在此平坦化製程中,安置於周邊區中的虛設襯墊256可減少或防止發生在其中定位有連接襯墊254的安裝區中的介電質侵蝕,且可改良接合表面的平坦化品質。
虛設襯墊256可以與連接襯墊254的製程相同的製程製造。在一些示例性實施例中,虛設襯墊256可包含與連接襯墊254的金屬相同的金屬。舉例而言,虛設襯墊256及連接襯墊254可分別包含銅。
在一些示例性實施例中,將外部連接襯墊252與連接襯墊254彼此電連接的通孔或內部配線可在基礎結構200的內部形成。導電凸塊270(諸如焊料球)可形成於基礎結構200的外部連接襯墊252上。在本發明示例性實施例中,基礎結構200示出為插入件,但根據不同實施例,基礎結構200可具有在其中實施邏輯晶片或記憶體晶片的形式。
隨後,參考圖12B,第一半導體晶片100A可安置於半導體晶圓200W的各基礎結構200上。
第一半導體晶片100A可直接接合至半導體晶圓200W的上部表面。各基礎結構200的連接襯墊254與第一半導體晶片100A的正面襯墊152可彼此直接接合,且基礎絕緣層264與第一半導體晶片100A的正面絕緣層162可彼此直接接合。
堆疊第一半導體晶片100A的製程可在虛設襯墊外部地暴露於外部的狀態下進行。金屬氧化物膜257'可在一系列製程中形成於虛設襯墊256上,所述製程諸如使用去離子水(例如,OH基團的吸收)的清潔製程、O
2電漿處理製程以及退火製程。金屬氧化物膜257'可理解為藉由部分氧化虛設襯墊256的金屬所形成的產物。金屬氧化物膜257'的厚度t0可相對較小(例如,約10奈米或小於10奈米)。
隨後,參考圖12C,可進行堆疊額外半導體晶片的製程以對應於所要數目個晶片。
堆疊第二半導體晶片100B、第三半導體晶片100C以及第四半導體晶片100D的製程可以直接接合的方式(例如,混合接合方式,以類似於堆疊第一半導體晶片100A的製程的方式)實施。額外堆疊製程可在虛設襯墊256暴露的狀態下反覆地進行,使得可增加金屬氧化物膜257的厚度t。與模製層的接合強度可由具有所要厚度的金屬氧化物膜257改良。
在金屬氧化物膜257的厚度t為約80奈米或小於80奈米時,通常可展現高接合強度。為了穩定的改良效果(最小厚度),金屬氧化物膜257的厚度t可在約5奈米至約80奈米範圍內。在一些示例性實施例中,可藉由將金屬氧化物膜257的厚度t調整為約10奈米至約40奈米來達到相對高的接合強度。
隨後,參考圖12D,毗鄰或包圍晶片堆疊CS1的模製層180'可形成於半導體晶圓200W上,且可進行研磨製程以暴露最上部半導體晶片100D的上部表面。
在研磨製程後,模製層180可毗鄰或包圍晶片堆疊CS1的側表面,以打開晶片堆疊CS1的上部表面。在本發明示例性實施例中,因為模製層180在堆疊製程完成的狀態下形成,所以模製層180可包含由單一材料(例如,EMC)形成的單一或單體結構。替代虛設襯墊256,形成於虛設襯墊256上的金屬氧化物膜257與模製層180直接接觸以增加基礎結構200與模製層180之間的接合強度。
隨後,所要半導體封裝500經可由切割製程形成。藉由此切割製程,模製層180可具有與基礎結構200的側表面實質上共面的表面。
雖然上文已繪示且描述示例性實施例,但對於熟習此項技術者將顯而易見的是,可在不脫離如隨附申請專利範圍所限定的本發明範疇的情況下進行修改及變化。
100、100E、100F、100G:第二半導體晶片
100A:第一半導體晶片/第二半導體晶片
100B:第二半導體晶片
100C:第二半導體晶片/第三半導體晶片
100D:第二半導體晶片/第四半導體晶片
100H:半導體晶片/第二半導體晶片/第三半導體晶片
110:半導體基底/第二半導體基底
110A:下部表面
110':第三半導體基底
120:半導體裝置層/第二半導體裝置層
130:貫通電極/第二貫通電極
131:側面絕緣膜
135:通孔插塞
141:配線絕緣層
142:金屬配線層
143:通孔
145、245:配線層
152:正面襯墊
152A:第二正面襯墊
152B:第二正面虛設襯墊
154:背面襯墊
154A:第二背面襯墊
154B:第二背面虛設襯墊
162:正面絕緣層/第二正面絕緣層
164:第二背面絕緣層
180、180':模製層
190:防熱板
192:導熱材料層
200:基礎結構
200A、300:第一半導體晶片
200W:半導體晶圓
210、310:第一半導體基底
230、330:第一貫通電極
240:配線結構
252:外部連接襯墊
254:連接襯墊
254T、256T、264T:上部表面
256、356:虛設襯墊
257、257':金屬氧化物膜
264:基礎絕緣層
270:導電凸塊
320:第一半導體裝置層
352:第一正面襯墊
354A:第一背面襯墊
354B:第一背面虛設襯墊
357:金屬氧化物膜
362:保護層
364:第一背面絕緣層
500、500A、500B:半導體封裝
610:載體基底
620:黏接層
A1、A2、B、C:部分
AK:對準鍵襯墊
CS、CS1、CS2:晶片堆疊
DB1:金屬對金屬接合
DB2:介電質對介電質接合
L0、L1、L2:層級
P1、P2:間距
t、t0:厚度
W1、W2:寬度
自結合隨附圖式進行的以下詳細描述,將更清楚地理解本發明概念的上述及其他態樣、特徵以及優勢,在隨附圖式中:
圖1為示出根據本發明的示例性實施例的半導體封裝的側橫截面圖。
圖2及圖3為分別示出圖1的半導體封裝的部分「A1」及部分「A2」的部分放大視圖。
圖4為示出圖1的半導體封裝中使用的基礎結構的頂部平面圖。
圖5為示出根據虛設襯墊上的金屬氧化物膜的厚度的模製層與虛設襯墊上的金屬氧化物膜之間的接合強度的曲線圖。
圖6為示出根據本發明的示例性實施例的半導體封裝的側橫截面圖。
圖7為示出圖6的半導體封裝中的部分「B」的部分放大視圖。
圖8為示出圖6的半導體封裝中使用的基礎結構的頂部平面圖。
圖9為示出根據本發明的示例性實施例的半導體封裝的側橫截面圖。
圖10為示出圖9的半導體封裝中的部分「C」的部分放大視圖。
圖11為示出圖9的半導體封裝中使用的基礎結構的頂部平面圖。
圖12A至圖12D為示出製造根據本發明的示例性實施例的半導體封裝的方法的主製程的橫截面視圖。
100A:第一半導體晶片
100B:第二半導體晶片
100C:第三半導體晶片
100D:第四半導體晶片
110:半導體基底
110':第三半導體基底
110A:下部表面
120:半導體裝置層
130:貫通電極
145:配線層
152:正面襯墊
154:背面襯墊
162:正面絕緣層
164:第二背面絕緣層
180:模製層
200:基礎結構
252:外部連接襯墊
254:連接襯墊
256:虛設襯墊
257:金屬氧化物膜
264:基礎絕緣層
270:導電凸塊
500:半導體封裝
A1、A2:部分
CS1:晶片堆疊
Claims (20)
- 一種半導體封裝,包括: 第一半導體晶片; 多個第二半導體晶片,堆疊於所述第一半導體晶片上,且分別具有窄於所述第一半導體晶片的寬度的寬度;以及 模製層,位於所述第一半導體晶片的上部表面上及所述多個第二半導體晶片的側表面上, 其中所述第一半導體晶片包含: 第一半導體基底;第一半導體裝置層,位於所述第一半導體基底的正面上;第一正面襯墊,位於所述第一半導體裝置層上;第一背面絕緣層,位於所述第一半導體基底的背面上且分成第一區及第二區;第一背面襯墊,位於所述第一背面絕緣層的所述第一區中;虛設襯墊,位於所述第一背面絕緣層的所述第二區中,其中所述虛設襯墊中的各者具有上面有金屬氧化物膜的上部表面;以及第一貫通電極,延伸穿過所述第一半導體基底且將所述第一正面襯墊與所述第一背面襯墊彼此電連接, 其中所述多個第二半導體晶片中的各者包含: 第二半導體基底;第二半導體裝置層,位於所述第二半導體基底的正面上;第二正面絕緣層,位於所述第二半導體裝置層上;第二正面襯墊,位於所述第二正面絕緣層中;第二背面絕緣層,位於所述第二半導體基底的背面上;第二背面襯墊,位於所述第二背面絕緣層中;以及第二貫通電極,延伸穿過所述第二半導體基底且將所述第二正面襯墊與所述第二背面襯墊彼此電連接, 其中所述多個第二半導體晶片當中的最下部第二半導體晶片的所述第二正面絕緣層接合至所述第一背面絕緣層,且所述最下部第二半導體晶片的所述第二正面襯墊分別接合至所述第一背面襯墊。
- 如請求項1所述的半導體封裝,其中所述第一背面襯墊具有與所述第一背面絕緣層的上部表面共面的上部表面,且所述第二正面襯墊具有與所述第二正面絕緣層的上部表面共面的上部表面。
- 如請求項1所述的半導體封裝,其中所述多個第二半導體晶片在第一方向上堆疊,以及 其中所述虛設襯墊中的各者的所述金屬氧化物膜具有在所述第一方向上高於所述第一背面絕緣層的上部表面的上部表面。
- 如請求項1所述的半導體封裝,其中所述金屬氧化物膜包含含有所述虛設襯墊中的各者中包含的金屬的氧化物。
- 如請求項1所述的半導體封裝,其中 所述第一半導體晶片更包含所述第一背面絕緣層的所述第一區中的所述第一半導體基底的所述背面上的第一背面虛設襯墊,以及 所述最下部第二半導體晶片更包含所述第二正面絕緣層中的所述第二半導體基底的所述正面上的第二正面虛設襯墊,且所述第二正面虛設襯墊分別接合至所述第一背面虛設襯墊。
- 如請求項1所述的半導體封裝,其中 所述第一半導體晶片更包含所述第一背面絕緣層的所述第二區中的所述第一半導體基底的所述背面上的至少一個對準鍵襯墊,以及 額外金屬氧化物膜位於所述至少一個對準鍵襯墊上。
- 如請求項1所述的半導體封裝,其中所述金屬氧化物膜與所述模製層直接接觸。
- 如請求項1所述的半導體封裝,其中所述模製層包含由單一材料形成的單體結構。
- 如請求項1所述的半導體封裝,其中所述多個第二半導體晶片中的各者的所述第二背面絕緣層接合至所述多個第二半導體晶片中的另一相鄰者的所述第二正面絕緣層,且所述多個第二半導體晶片中的各者的所述第二背面襯墊分別接合至所述多個第二半導體晶片中的另一相鄰者的所述第二正面襯墊。
- 如請求項1所述的半導體封裝,其中所述多個第二半導體晶片屬於不同於所述第一半導體晶片的類型的相同類型。
- 如請求項10所述的半導體封裝,其中 所述第一半導體晶片包含邏輯晶片,以及 所述多個第二半導體晶片分別包含記憶體晶片。
- 如請求項1所述的半導體封裝,其中,所述半導體封裝更包括: 第三半導體晶片,位於所述多個第二半導體晶片當中的最上部第二半導體晶片上,以及 所述第三半導體晶片包含: 第三半導體基底; 第三半導體裝置層,位於所述第三半導體基底的正面上; 第三正面絕緣層,位於所述第三半導體裝置層上且接合至所述最上部第二半導體晶片的所述第二背面絕緣層;以及 第三正面襯墊,位於所述第三正面絕緣層中且分別接合至所述最上部第二半導體晶片的所述第二背面襯墊。
- 一種半導體封裝,包括: 基礎結構,具有分成第一區及第二區的上部表面,且包含所述上部表面上的基礎絕緣層、以所述基礎絕緣層為邊界且配置於所述第一區上的連接襯墊以及以所述基礎絕緣層為邊界且配置於所述第二區上的虛設襯墊,其中所述虛設襯墊中的各者具有上面安置有金屬氧化物膜的上部表面; 至少一個半導體晶片,位於所述基礎結構的所述第一區上,包含半導體基底、位於所述半導體基底的正面上的半導體裝置層、位於所述半導體裝置層上且接合至所述第一區中的所述基礎絕緣層的正面絕緣層以及以所述正面絕緣層為邊界且分別接合至所述連接襯墊的正面襯墊;以及 模製層,位於所述基礎結構上且與所述至少一個半導體晶片的側表面毗鄰。
- 如請求項13所述的半導體封裝,其中所述金屬氧化物膜的上部表面在垂直於所述基礎結構的所述上部表面的方向上高於所述連接襯墊的上部表面。
- 如請求項13所述的半導體封裝,其中所述金屬氧化物膜具有5奈米至80奈米的厚度。
- 如請求項13所述的半導體封裝,其中所述基礎結構包含具有配線電路的基底。
- 如請求項13所述的半導體封裝,其中所述基礎結構包含類型與所述至少一個半導體晶片的類型不同的半導體晶片。
- 一種半導體封裝,包括: 第一半導體晶片,具有上部表面及下部表面,所述上部表面分成第一區及與所述第一區毗鄰的第二區; 多個第二半導體晶片,堆疊於所述第一半導體晶片的所述上部表面的所述第一區上,且屬於不同於所述第一半導體晶片的類型的相同類型;以及 模製層,位於所述第一半導體晶片上且與所述多個第二半導體晶片的側表面毗鄰, 其中所述第一半導體晶片包含: 保護層,位於所述第一半導體晶片的下部表面上;外部連接襯墊,位於所述保護層上;第一上部絕緣層,位於所述第一半導體晶片的上部表面上;第一上部襯墊,位於所述第一上部絕緣層中的所述上部表面的所述第一區上;虛設襯墊,位於所述第一上部絕緣層中的所述上部表面的所述第二區上;以及金屬氧化物膜,分別位於所述虛設襯墊上, 其中所述多個第二半導體晶片中的各者包含: 半導體基底;半導體裝置層,位於所述半導體基底的正面上;正面絕緣層,位於所述半導體裝置層上;正面襯墊,位於所述正面絕緣層中;背面絕緣層,位於所述半導體基底的背面上;背面襯墊,位於所述背面絕緣層中;以及貫通電極,延伸穿過所述半導體基底且將所述正面襯墊及所述背面襯墊彼此電連接,以及 其中所述多個第二半導體晶片當中的最下部第二半導體晶片的所述正面絕緣層接合至所述第一上部絕緣層,且所述最下部第二半導體晶片的所述正面襯墊分別接合至所述第一上部襯墊。
- 如請求項18所述的半導體封裝,其中 所述多個第二半導體晶片在第一方向上堆疊, 所述第一上部襯墊具有與所述第一上部絕緣層的上部表面共面的上部表面,以及 所述金屬氧化物膜具有在所述第一方向上高於所述第一上部絕緣層的所述上部表面的上部表面。
- 如請求項18的半導體封裝,其中所述第一上部襯墊及所述虛設襯墊分別包含銅,且所述金屬氧化物膜包含氧化銅。
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KR1020220092676A KR20240015225A (ko) | 2022-07-26 | 2022-07-26 | 반도체 패키지 |
KR10-2022-0092676 | 2022-07-26 |
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TW112127783A TW202410334A (zh) | 2022-07-26 | 2023-07-25 | 半導體封裝 |
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US (1) | US20240038728A1 (zh) |
KR (1) | KR20240015225A (zh) |
CN (1) | CN117457617A (zh) |
TW (1) | TW202410334A (zh) |
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2022
- 2022-07-26 KR KR1020220092676A patent/KR20240015225A/ko unknown
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- 2023-07-21 US US18/356,289 patent/US20240038728A1/en active Pending
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US20240038728A1 (en) | 2024-02-01 |
CN117457617A (zh) | 2024-01-26 |
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