TW202129027A - 基板處理方法、基板處理裝置及奈米線或奈米片之電晶體的製造方法 - Google Patents

基板處理方法、基板處理裝置及奈米線或奈米片之電晶體的製造方法 Download PDF

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TW202129027A
TW202129027A TW109136226A TW109136226A TW202129027A TW 202129027 A TW202129027 A TW 202129027A TW 109136226 A TW109136226 A TW 109136226A TW 109136226 A TW109136226 A TW 109136226A TW 202129027 A TW202129027 A TW 202129027A
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gas
processing
plasma
substrate
layer
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TW109136226A
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小山賢一
山內祥平
土橋和也
清水昭貴
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日商東京威力科創股份有限公司
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    • H01J37/32—Gas-filled discharge tubes
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Abstract

本發明係關於一種交互地層積有矽層與矽鍺層之基板的處理方法，使用經電漿化後且含有氟及氧的處理氣體，來將該矽鍺層之露出面的表層選擇性地改質而形成氧化膜。

Description

基板處理方法、基板處理裝置及奈米線或奈米片之電晶體的製造方法
本發明係關於一種基板處理方法、基板處理裝置及奈米線或奈米片之電晶體的製造方法。
專利文獻1中揭示一種在露出有矽鍺層與例如矽層之基板中，選擇性地蝕刻矽鍺層之方法。依據專利文獻1記載的蝕刻方法，係在真空氛圍下將含氟氣體及三氟化氯氣體同時供應至基板，藉此使蝕刻速度均勻來讓矽鍺層的蝕刻量一致。 [先前技術文獻] [專利文獻] 專利文獻1：日本特開2018-170380號公報
本發明相關之技術係在交互地層積有矽層與矽鍺層之基板的處理中來適當地縮短處理工序。 本發明一樣態為一種交互地層積有矽層與矽鍺層之基板的處理方法，係使用經電漿化後且含有氟及氧的處理氣體，來將該矽鍺層之露出面的表層選擇性地改質而形成氧化膜。 依據本發明，便可在交互地層積有矽層與矽鍺層之基板的處理中來適當地縮短處理工序。
在半導體元件中，含有矽之膜被廣範地應用於各種用途。例如矽鍺(SiGe)膜或矽(Si)膜係被使用於閘極電極或種晶層等。然後，過去，在稱作奈米片或奈米線之GAA(Gate all around)電晶體的製造工序中，如圖1所示，會依序進行(a)朝基板(晶圓W)之SiGe膜與Si膜的層積，(b)SiGe膜的選擇性蝕刻，(c)作為層間絕緣膜之內間隔物(IS)的埋入，(d)多餘內間隔物的蝕刻。此外，在(c)中被埋入的層間絕緣膜係作為在後續工序中被埋入之金屬閘極與通道間的絕緣膜而被加以構成。 上述專利文獻1所揭示之技術係用以進行該(b)SiGe膜的選擇性蝕刻之方法。上述般SiGe膜的選擇性蝕刻中，被要求須均勻地控制所層積之各SiGe膜的蝕刻量。然後，依據專利文獻1所揭示之蝕刻方法，係藉由同時供應含氟氣體及三氟化氯氣體來使SiGe膜的蝕刻量變得均勻。 然而，上述般傳統製造工序中，在前述(a)~(d)之各工序中，需要高精確度的加工而有良率降低或成本太高之課題，便有改善的餘地。 因此，本案發明人苦心進行檢討後，發現在針對晶圓W之自由基氧化處理中，會同時進行SiGe膜的蝕刻與氧化。亦即，新發現了藉此便可省略傳統製造工序中的前上述(a)~(d)工序之可能性。然而，以上見解亦未被記載於專利文獻1中。 本發明相關之技術係依據上述見解而發明的技術，可在交互地層積有矽(Si)層與矽鍺(SiGe)層之基板的處理中，來適當地縮短處理工序。以下，便針對作為本實施型態相關的基板處理裝置之電漿處理裝置，以及使用該電漿處理裝置所進行且作為基板處理方法之電漿處理，參照圖式來加以說明。此外，本說明書及圖式中，關於實質具有相同的功能構成之要素，係賦予相同的符號而省略重複說明。 ＜電漿處理裝置＞ 圖2係概略顯示電漿處理裝置1的構成概略之縱剖面圖。此外，以下的說明中，會有將交互地配列有SiGe層與Si層之各層所露出的端面稱作SiGe層及Si層的｢露出面｣之情況。 此外，電漿處理裝置1中，係將晶圓W上所層積形成之Si層及SiGe層當中的SiGe層選擇性地改質。具體來說，係選擇性地去除SiGe層之露出面上的附著物且使SiGe層氧化，藉此在晶圓W上之SiGe層的露出面表層，亦即，自露出面起而於深度方向上形成氧化膜(SiO2 膜)。 如圖2所示，電漿處理裝置1係具備會收納晶圓W之密閉構造的處理容器10。處理容器10係由例如鋁或鋁合金所構成且上端為開放，處理容器10的上端係藉由會成為頂部之蓋體10a而被加以封閉。處理容器10的側面係設置有晶圓W的搬出入口(圖中未顯示)，而透過此搬出入口來與電漿處理裝置1的外部相連接。搬出入口係構成為會藉由閘閥(圖中未顯示)而開閉自如。 處理容器10的內部係藉由分隔板11而被分隔為上方的電漿生成空間P與下方的處理空間S。亦即，本實施型態相關之電漿處理裝置1係構成為電漿生成空間P會和處理空間S分離之遠端電漿處理裝置。 分隔板11係具有從電漿生成空間P朝處理空間S而重疊般地配置之至少2個板狀組件12、13。板狀組件12、13之間係配置有會調節該板狀組件12、13的間隔之間隔物14。又，板狀組件12、13係分別具有貫穿於重疊方向所形成之槽縫12a、13a。各槽縫12a、13a係配置為在俯視觀看下不會重疊，藉此，當電漿生成空間P中生成電漿之際，分隔板11便會具有可抑制電漿中的離子朝處理空間S穿透(所謂的離子捕集器)之功能。更具體而言，係藉由槽縫12a及槽縫13a並未重疊般地配置之槽縫配置構造(即曲徑構造)，來阻止異向性地移動之離子的移動，另一方面，會使等向性地移動之自由基穿透。 此外，分隔板11的構造並未侷限於圖示之範例，可採用任意構成。 電漿生成空間P係具備會將處理氣體供應至處理容器10內之供氣部20，以及會將被供應至處理容器10內的處理氣體電漿化之電漿生成部30。 供氣部20係連接有複數氣體供應源(圖中未顯示)，該等氣體供應源會將包含有含氟氣體(例如NF3 氣體)、含氧氣體(例如O2 氣體)及稀釋氣體(例如Ar氣體)之處理氣體供應至處理容器10的內部。此外，含氟氣體、含氧氣體及稀釋氣體的種類並未侷限於此，可任意選擇。 又，供氣部20係設置有會調節對電漿生成空間P之處理氣體的供應量之流量調節器(圖中未顯示)。流量調節器係具備例如開閉閥及質流控制器。 電漿生成部30係構成為使用RF天線之感應耦合型裝置。處理容器10的蓋體10a係由例如石英板所形成，且係構成為介電窗。蓋體10a的上方係形成有用以於處理容器10的電漿生成空間P生成感應耦合電漿之RF天線31，RF天線31係透過匹配器32而連接於高頻電源33。 匹配器32係具備用以取得高頻電源33側之阻抗與負荷(RF天線31或電漿)側之阻抗的匹配之可變電抗的匹配電路(圖中未顯示)。 高頻電源33會以任意輸出值來輸出適於感應耦合之高頻放電所致的電漿生成之固定頻率(通常為13.56MHz以上)的高頻電功率。 處理空間S係具備會在處理容器10內載置晶圓W之載置台40，以及會排出處理容器10內的處理氣體之排氣部50。 載置台40係具備會載置晶圓W之上部台41，以及被固定在處理容器10的底面來支撐上部台41之下部台42。上部台41的內部係設置有會調節晶圓W的溫度之溫度調節機構43。 排氣部50係在載置台40的外側邊處，透過處理容器10的底部所設置之排氣管而連接於例如真空幫浦等排氣機構(圖中未顯示)。又，排氣管係設置有自動壓力控制閥(APC)。藉由該等排氣機構與自動壓力控制閥來控制處理容器10內的壓力。 上述電漿處理裝置1係設置有作為控制部之控制裝置60。控制裝置60為具備例如CPU或記憶體等之電腦，係具有程式儲存部(圖中未顯示)。程式儲存部係儲存有會控制電漿處理裝置1中之晶圓W的處理之程式。又，程式儲存部亦儲存有用以控制上述各種處理裝置或搬送裝置等驅動系統的動作，來實現電漿處理裝置1中的後述晶圓處理之程式。此外，上述程式亦可被記錄在能夠讓電腦讀取的記憶媒體H，且從該記憶媒體H被安裝在控制裝置60。 ＜電漿處理＞ 本實施型態相關之電漿處理裝置1係依上述方式構成。接下來，針對使用電漿處理裝置1所進行之電漿處理來加以說明。此外，被搬入至電漿處理裝置1的晶圓W係預先交互地層積形成有前述Si層與SiGe層。 首先，藉由電漿處理裝置1的外部所設置之晶圓搬送機構(圖中未顯示)來將如上述般交互地層積形成有Si層與SiGe層之晶圓W搬入並載置於載置台40。 關於被搬入的晶圓W，該晶圓W上所層積形成之Si層及SiGe層中的SiGe層會被選擇性地改質。具體而言，係從供氣部20來將處理氣體(本實施型態中為NF3 氣體、O2 氣體及Ar氣體)供應至電漿生成空間P，且將高頻電功率供應至RF天線31，來生成為感應耦合電漿而含有氧及氟之電漿。換言之，所生成之電漿係含有氟自由基(F* )及氧自由基(O* )。 此處，被供應至電漿生成空間P之處理氣體的流量較佳為O2 ：NF3 =100~2500sccm：1~20sccm，更佳地，NF3 氣體相對於O2 氣體的體積比率較佳為0.1vol%以上1.0vol%以下。又，電漿生成空間P中之高頻電功率的輸出較佳為100W~1000W，電漿生成空間P的壓力(真空度)較佳為6.67Pa~266.6Pa(50mTorr~2000mTorr)。又另外，電漿生成空間P的溫度較佳為0℃~120℃，更佳為15~100℃。 電漿生成空間P中所生成之電漿會透過分隔板11來朝處理空間S被供應。此處，由於分隔板11係如前述般地形成有曲徑構造，故只有電漿生成空間P中生成的自由基會朝處理空間S穿透。然後，藉由使得朝處理空間S被供應的自由基如圖3(a)所示般地作用在SiGe層的露出面，而如圖3(b)所示般地將SiGe層改質，來於SiGe層之露出面的表層形成氧化膜Ox。 此處，圖4為比較本實施型態相關之電漿處理中，Si層與SiGe層的氧化量之圖表。又，圖5係顯示本實施型態相關之電漿處理中，SiGe層之蝕刻量及氧化量的依時變化之圖表。此外，SiGe層的｢蝕刻量｣係指如圖5所示般地從晶圓W(Si層)的外端部到SiGe層的外端部之距離。又，SiGe層的｢氧化量｣係指如圖5所示般地SiGe層的露出面所形成之氧化膜Ox的徑向厚度。 如圖4所示，可得知本實施型態相關之電漿處理中，SiGe層的氧化量(氧化速度)係相對於Si層的氧化量(氧化速度)而為約6倍。換言之，可得知藉由本實施型態相關之電漿處理，便可適當地將SiGe層選擇性地改質(氧化)。 又，如圖5所示，可藉由層積Si及SiGe並進行電漿處理，來將SiGe層的蝕刻量(亦即殘留在晶圓W上之SiGe層的徑向尺寸)相對於處理時間而線性地控制。另一方面，可得知藉由層積Si及SiGe並進行電漿處理，SiGe層的氧化量(亦即形成於SiGe層的露出面上之氧化膜(SiO2 膜)的徑向厚度)係無關於處理時間而在約10nm呈飽和。換言之，依據本實施型態相關之電漿處理，由於可在將SiGe層的氧化量保持為期望值之情況下來適當地控制SiGe層的蝕刻量，故可將SiGe層的線寬，即後工序中所形成之通道寬度控制為任意尺寸。 針對SiGe層的改質來具體地說明。當自由基穿透處理空間S後，首先，附著在SiGe層的露出面上之沉積物(會因例如為前處理之反應性離子蝕刻(RIE：Reactive Ion Etching)處理而附著)會因F* 而被去除。接著，O* 會作用在SiGe層來將SiGe層的露出面氧化而形成氧化膜Ox(SiO2 膜)。在SiGe層的氧化中，O2 會取代Ge而鍵結於Si，藉此Ge便會氣體化(例如Ge2 F4 或GeOF2 )並飛散，且因例如F* 或Ar* 而被搬運至排氣部50並被回收。本實施型態中係將相關一連串沉積物的去除及SiGe層的氧化統稱為｢改質｣。 此處，本案發明人針對上述方式所形成的氧化膜(SiO2 膜)進行檢討後，發現上述氧化膜的溢漏電流較少而確保良好的絕緣性，又，係具有作為絕緣膜之良好的CV、IV特性。亦即，發現可利用來作為絕緣氧化膜。又另外，發現EOT(Equivalent Oxide Thickness)減少亦很輕微，且亦確保耐熱性。亦即，藉由利用上述方式所形成的氧化膜來作為內間隔物，便可將圖1所示之既有GAA電晶體的製造過程減少1/3左右的工序數。具體而言，由於可不進行圖1所示般之SiGe層的選擇性蝕刻、內間隔物的埋入及蝕刻，而僅藉由使得經電漿化後的處理氣體作用在SiGe層，來將SiGe層選擇性地氧化，且利用所形成之氧化膜來作為內間隔物，故可大幅減少工序數。 此外，當一次電漿處理中將自由基供應至處理空間S的時間變長之情況，便會有因該自由基而導致對於Si層的作用變大之虞。為了抑制上述對於Si層的影響，則進行電漿處理之每1組的處理時間較佳為例如30Sec~180Sec。 此處，電漿處理中之SiGe層的蝕刻量，即SiGe層的徑向尺寸係如圖5所示般地藉由電漿處理時間而被控制。因此，為了抑制自由基對Si層的作用，且以所欲深度來形成氧化膜，則最好是複數組且反覆地進行前述1組的電漿處理(30sec~180sec)。 又，當電漿處理中之輸出變高的情況，仍會有自由基對Si層造成影響之虞。為了抑制上述對於Si層的影響，則電漿處理的輸出較佳宜如前述般地為100W~1000W。 又另外，本實施型態中，係在不同於進行電漿處理之處理空間S而為其他的電漿生成空間P中進行電漿生成，即所謂的遠端電漿生成，並將電漿生成空間P中所生成的電漿朝處理空間S搬送。由於氟離子等離子容易在搬送中失去活性，故藉由如此般地使用遠端電漿，便可在處理空間S中進行以自由基作為主體之處理。然後，藉由如此般地使用自由基，便可降低對於Si層、SiGe層及晶圓W的損傷。 然後，藉由電漿處理裝置1的外部所設置之晶圓搬送機構(圖中未顯示)來將電漿處理裝置1中已結束電漿處理後的晶圓W從電漿處理裝置1搬出，便結束一連串的電漿處理。 以上，依據本實施型態，在相對於SiGe層之內間隔物的形成之際，由於可僅藉由以電漿處理裝置1而在所欲條件下供應經電漿化後的處理氣體來進行SiGe層的改質，故可減少電漿處理相關的工序數。又，藉由如此般地減少工序數，便可減少電漿處理相關的費用，且可提高內間隔物形成相關的加工精確度。 圖6係顯示本實施型態相關之電漿處理中，進行SiGe層之改質後的結果之SEM影像。可得知藉由本實施型態相關之電漿處理，便可僅將如圖6(a)所示般地形成於晶圓W上之Si層及SiGe層中的SiGe層適當地改質，來如圖6(b)所示般地形成氧化膜Ox。 又，依據本實施型態，由於係將F* 供應至處理空間S來進行沉積物的去除，故不須如過去般地在SiGe層的電漿處理前先進行前處理(例如藉由HF處理來去除自然氧化膜等)。 又，依據本實施型態，由於電漿處理裝置中會進行遠端電漿處理，故可抑制所產生之電漿到達Si層、SiGe層及晶圓W，從而可抑制對該等Si層、SiGe層及晶圓W造成損傷。具體而言，由於所生成之含有氟及氧的自由基是以失去活性之狀態到達晶圓W的露出面，故可適當地進行SiGe層的改質，且抑制對Si層及晶圓W造成影響。 又另外，依據本實施型態，由於遠端電漿處理係以100W~1000W的輸出來進行，且處理容器10的分隔板11係具有曲徑構造，故可適當地抑制所產生之離子到達Si層、SiGe層及晶圓W。亦即，可更適當地抑制對Si層及晶圓W造成影響。 此外，本實施型態相關之電漿處理中，雖是供應O2 、NF3 及Ar來作為處理氣體，但亦可進一步地追加供應Ar氣體來作為Add氣體。 此外，依據本實施型態，雖是選擇NF3 來作為處理氣體所包含之含氟氣體，但只要能夠在電漿生成中適當地生成F* ，則亦可選擇例如SF6 氣體或F2 氣體。又，稀釋氣體不限於Ar氣體，可選擇含有H2 氣體或稀有氣體的至少1種之任意氣體。 又，電漿生成空間P中的電漿源亦未限定於本實施型態般之感應耦合電漿，可採用例如微波電漿等任意構成。此外，本案發明人以平行平板型電漿處理裝置來進行相同實驗後，並無法如本實施型態所示般適當地進行SiGe層的選擇性改質，而亦會將Si層同時地改質。因此，電漿處理裝置中，較佳宜藉由遠端電漿生成來生成電漿。 此外，亦可在藉由本實施型態中的電漿處理來形成氧化膜後，於BT處理裝置(圖中未顯示)中進行氧化物的去除(BT處理)。 此外，針對如上述般地形成有作為內間隔物的氧化膜Ox之晶圓W，之後會有在例如該電漿處理裝置1的外部所設置之蝕刻處理裝置(圖中未顯示)中進行濕蝕刻處理的情況。因此，本實施型態相關之電漿處理裝置1中，亦可進一步進行用以提高上述實施型態中所形成之內間隔物(氧化膜Ox)的耐濕蝕刻性之電漿處理。 具體而言，可藉由使用包含有例如含氮氣體(例如N2 氣體、NH3 氣體或NF3 氣體等)的第2處理氣體來對形成有氧化膜Ox之晶圓W進一步地施予電漿處理，以提高內間隔物(氧化膜Ox)的耐濕蝕刻性。 若使用第2處理氣體來對晶圓W進行電漿處理，則N* 便會作用在氧化膜Ox來讓氧化膜Ox氮化，而圖8(a)所示般地於內間隔物的表層形成有作為保護膜之氮化膜Nt。作為氧化膜Ox之SiO2 膜的氮化中，N會取代O2 而鍵結於Si，藉此則O2 便會氣體化並飛散。然後，藉由如此般地於內間隔物的至少表層形成具耐濕蝕刻性之氮化膜Nt(例如SiN膜)，則在濕蝕刻處理之際，氧化膜Ox便會因氮化膜Nt而自蝕刻溶液被保護。亦即，可藉由殘留在氮化膜Nt內側的氧化膜Ox來維持作為內間隔物之特性，且藉由該氮化膜Nt來提高耐濕蝕刻性。 此外，本案發明人針對上述方式形成的氮化膜Nt進行檢討後，發現即便是藉由相關氮化膜Nt，仍可發揮至少作為內間隔物之特性。亦即，在圖8(a)之圖示中，雖是將氧化膜Ox的至少表層氮化來層積形成氧化膜Ox與氮化膜Nt，但亦可例如圖8(b)所示般地，將全部的氧化膜Ox置換為氮化膜Nt且利用該氮化膜Nt來作為內間隔物。此外，由於氧化膜Ox係較氮化膜Nt而具有作為絕緣膜之更良好的特性(CV、IV特性)，故更佳宜如圖8(a)亦有顯示般地使氮化膜Nt作為會作為內間隔物之氧化膜Ox的保護膜來使其作用。 此外，藉由用以提高耐濕蝕刻性之電漿處理所形成的膜並未侷限於上述般之氮化膜Nt。例如，亦可使用包含有含碳氣體之第2處理氣體來讓氧化膜Ox碳化，而如圖8(c)所示般地於內間隔物的至少表層形成具耐濕蝕刻性之碳化膜Cb(例如SiC膜)。可使用例如CH4 氣體、CHF3 氣體、CH2 F2 氣體、CH3 F氣體、CF4 氣體、C4 F6 氣體、C4 F8 氣體、CO氣體、CO2 氣體、COS氣體等來作為含碳氣體。然後，即便是如此般地形成碳化膜Cb情況，仍可與上述氮化膜Nt同樣地提高相對於後續處理工序中所進行的濕蝕刻處理之耐受性。 此外，本案發明人針對上述方式所形成之碳化膜Cb進行檢討後，發現相關碳化膜Cb係較氧化膜Ox而具有作為絕緣膜之良好特性(CV、IV特性)，且可更加降低內間隔物的介電率。亦即，圖8(c)之圖示中，雖係將氧化膜Ox的至少表層碳化來層積形成氧化膜Ox與碳化膜Cb，但例如圖8(d)所示般地，亦可將全部的氧化膜Ox置換為碳化膜Cb，且利用該碳化膜Cb來作為內間隔物。上述情況下，相較於利用氧化膜Ox來作為內間隔物之情況，可提高耐濕蝕刻性，且可更加提高內間隔物的絕緣性。 此外，本實施型態中，在電漿處理裝置1中，電漿生成空間P雖係一體地設置於與處理空間S相同腔室內，即處理容器10的上部，但電漿處理裝置1的構成並未侷限於此。例如圖7所示，亦可將電漿生成空間P設置在處理容器10的外部。 本說明書所揭示之實施型態應被認為所有要點僅為例示而非用以限制本發明之內容。上述實施型態可在未背離添附的申請專利範圍及其要旨之範圍內，而以各種型態來做省略、置換或變更。 此外，以下般之構成亦屬於本發明之技術範圍。 (1)一種基板處理方法，係交互地層積有矽層與矽鍺層之基板的處理方法；使用經電漿化後且含有氟及氧的處理氣體來將該矽鍺層之露出面的表層選擇性地改質而形成氧化膜。 依據前述(1)，則在交互地層積有矽層與矽鍺層之基板的電漿處理中，便可僅藉由含有氟及氧的處理氣體來生成電漿，且供應上述經電漿化後的處理氣體，來適當地進行矽鍺層的改質(附著物的去除及矽鍺層的氧化)。 (2)如前述(1)之基板處理方法，其中該處理氣體係包含有O2 氣體及含氟氣體，含氟氣體相對於O2 氣體的體積比率為0.1vol%以上，1.0vol%以下。 (3)如前述(2)之基板處理方法，其中該含氟氣體為NF3 氣體、F2 氣體或SF6 氣體。 (4)如前述(1)~前述(3)中任一基板處理方法，其中該處理氣體係另包含有H2 氣體或稀有氣體之至少1種。 (5)如前述(1)~前述(4)中任一基板處理方法，其中該處理氣體的電漿化中係使用遠端電漿。 依據前述(5)，藉由以遠端電漿來生成處理氣體，便可適當地抑制Si層、SiGe層及晶圓W的損傷，且可適當地進行SiGe層的改質。 (6)如前述(1)~前述(5)中任一基板處理方法，其中該矽鍺層自該露出面起的蝕刻量係與針對該基板之電漿處理時間成比例。 (7)如前述(1)~前述(6)中任一基板處理方法，其中該氧化膜的形成厚度係無關於針對該基板之電漿處理時間，而在所需數值呈飽和。 (8)如前述(6)或前述(7)之基板處理方法，其係反覆進行針對該基板之電漿處理，且1組的電漿處理時間為30sec~180sec。 依據前述(8)，藉由以上述時間來控制電漿處理的時間，便可更加適當地抑制Si層的損傷。又，藉由反覆進行電漿處理，便可適當地進行SiGe層之露出面表層的改質，亦即自露出面至所欲深度的改質。 (9)如前述(1)~前述(8)中任一基板處理方法，其係使用包含有經電漿化後的含氮氣體之第2處理氣體，來將該氧化膜的至少表層改質而形成氮化膜。 (10)如前述(1)~前述(8)中任一基板處理方法，其係使用包含有經電漿化後的含碳氣體之第2處理氣體，來將該氧化膜的至少表層改質而形成碳化膜。 依據前述(9)或前述(10)，藉由進一步地將露出面的表層所形成之氧化膜的至少表層改質來形成氮化膜或碳化膜，便可提高相對於例如內間隔物形成後的處理工序中所進行之濕蝕刻處理的耐受性。 (11)一種基板處理裝置，係會處理交互地層積有矽層與矽鍺層的基板之基板處理裝置；具有：處理部，係使用經電漿化後且含有氟及氧的處理氣體，來將該矽鍺層之露出面的表層選擇性地改質而形成氧化膜；以及控制部，係控制該處理部中的電漿處理。 (12)如前述(11)之基板處理裝置，其中該處理氣體係包含有O2 氣體及含氟氣體； 該控制部會控制該處理部中之處理氣體的供應量，來使含氟氣體相對於O2 氣體的體積比率成為0.1vol%以上，1.0vol%以下。 (13)如前述(12)之基板處理裝置，其中該含氟氣體為NF3 氣體、F2 氣體或SF6 氣體。 (14)如前述(11)~前述(13)中任一基板處理裝置，其中該控制部會控制該處理部中之該處理氣體的供應，來進一步供應H2 氣體或稀有氣體之至少1種。 (15)如前述(11)~前述(14)中任一基板處理裝置，其中該處理部中，該處理氣體的電漿化中係使用遠端電漿。 (16)如前述(11)~前述(15)中任一基板處理裝置，其中該電漿處理中，該矽鍺層自該露出面起的蝕刻量係與電漿處理時間成比例。 (17)如前述(11)~前述(16)中任一基板處理裝置，其中該電漿處理中，該氧化膜的形成厚度係無關於電漿處理時間而在所需數值呈飽和。 (18)如前述(16)或前述(17)之基板處理裝置，其中該控制部係反覆進行針對該基板之電漿處理，且將1組的電漿處理時間控制在30sec~180sec。 (19)如前述(11)~前述(18)中任一基板處理裝置，其中該控制部會控制該處理部中的電漿處理，俾能夠使用包含有經電漿化後的含氮氣體之第2處理氣體，來將該氧化膜的至少表層改質而形成氮化膜。 (20)如前述(11)~前述(18)中任一基板處理裝置，其中該控制部會控制該處理部中的電漿處理，俾能夠使用包含有經電漿化後的含碳氣體之第2處理氣體，來將該氧化膜的至少表層改質而形成碳化膜。 (21)一種奈米線或奈米片之電晶體的製造方法，係使用交互地層積有矽層與矽鍺層的基板所進行之奈米線或奈米片之電晶體的製造方法； 使用經電漿化後且含有氟及氧的處理氣體來將該矽鍺層之露出面的表層選擇性地改質而形成絕緣氧化膜。 (22)如前述(21)之奈米線或奈米片之電晶體的製造方法，其係使用包含有經電漿化後的含氮氣體之第2處理氣體，來將該絕緣氧化膜的至少表層改質而形成氮化膜。 (23)如前述(21)之奈米線或奈米片之電晶體的製造方法，其係使用包含有經電漿化後的含碳氣體之第2處理氣體，來將該絕緣氧化膜的至少表層改質而形成碳化膜。
1:電漿處理裝置 60:控制裝置 S:處理空間 W:晶圓 Ox:氧化膜
圖1係概略顯示傳統晶圓處理的樣態之說明圖。 圖2係顯示電漿處理裝置的一構成例之縱剖面圖。 圖3係概略顯示本實施型態相關之晶圓處理的一樣態例之說明圖。 圖4係比較本實施型態相關之電漿處理中，矽層與矽鍺層的氧化量之圖表。 圖5係顯示本實施型態相關之電漿處理中，矽鍺層之氧化量及蝕刻量的依時變化一範例之圖表。 圖6係顯示本實施型態相關之電漿處理的結果一範例之影像。 圖7係顯示電漿處理裝置的一其他構成例之縱剖面圖。 圖8係顯示氧化膜的改質樣態之說明圖。
Ox:氧化膜

Claims (23)

  1. 一種基板處理方法，係交互地層積有矽層與矽鍺層之基板的處理方法； 使用經電漿化後且含有氟及氧的處理氣體來將該矽鍺層之露出面的表層選擇性地改質而形成氧化膜。
  2. 如申請專利範圍第1項之基板處理方法，其中該處理氣體係包含有O2 氣體及含氟氣體，含氟氣體相對於O2 氣體的體積比率為0.1vol%以上，1.0vol%以下。
  3. 如申請專利範圍第2項之基板處理方法，其中該含氟氣體為NF3 氣體、F2 氣體或SF6 氣體。
  4. 如申請專利範圍第1至3項中任一項之基板處理方法，其中該處理氣體係另包含有H2 氣體或稀有氣體之至少1種。
  5. 如申請專利範圍第1至4項中任一項之基板處理方法，其中該處理氣體的電漿化中係使用遠端電漿。
  6. 如申請專利範圍第1至5項中任一項之基板處理方法，其中該矽鍺層自該露出面起的蝕刻量係與針對該基板之電漿處理時間成比例。
  7. 如申請專利範圍第1至6項中任一項之基板處理方法，其中該氧化膜的形成厚度係無關於針對該基板之電漿處理時間，而在所需數值呈飽和。
  8. 如申請專利範圍第6或7項之基板處理方法，其係反覆進行針對該基板之電漿處理，且1組的電漿處理時間為30sec~180sec。
  9. 如申請專利範圍第1至8項中任一項之基板處理方法，其係使用包含有經電漿化後的含氮氣體之第2處理氣體，來將該氧化膜的至少表層改質而形成氮化膜。
  10. 如申請專利範圍第1至8項中任一項之基板處理方法，其係使用包含有經電漿化後的含碳氣體之第2處理氣體，來將該氧化膜的至少表層改質而形成碳化膜。
  11. 一種基板處理裝置，係會處理交互地層積有矽層與矽鍺層的基板之基板處理裝置；具有： 處理部，係使用經電漿化後且含有氟及氧的處理氣體，來將該矽鍺層之露出面的表層選擇性地改質而形成氧化膜；以及 控制部，係控制該處理部中的電漿處理。
  12. 如申請專利範圍第11項之基板處理裝置，其中該處理氣體係包含有O2 氣體及含氟氣體； 該控制部會控制該處理部中之處理氣體的供應量，來使含氟氣體相對於O2 氣體的體積比率成為0.1vol%以上，1.0vol%以下。
  13. 如申請專利範圍第12項之基板處理裝置，其中該含氟氣體為NF3 氣體、F2 氣體或SF6 氣體。
  14. 如申請專利範圍第11至13項中任一項之基板處理裝置，其中該控制部會控制該處理部中之該處理氣體的供應，來進一步供應H2 氣體或稀有氣體之至少1種。
  15. 如申請專利範圍第11至14項中任一項之基板處理裝置，其中該處理部中，該處理氣體的電漿化中係使用遠端電漿。
  16. 如申請專利範圍第11至15項中任一項之基板處理裝置，其中該電漿處理中，該矽鍺層自該露出面起的蝕刻量係與電漿處理時間成比例。
  17. 如申請專利範圍第11至16項中任一項之基板處理裝置，其中該電漿處理中，該氧化膜的形成厚度係無關於電漿處理時間而在所需數值呈飽和。
  18. 如申請專利範圍第16或17項之基板處理裝置，其中該控制部係反覆進行針對該基板之電漿處理，且將1組的電漿處理時間控制在30sec~180sec。
  19. 如申請專利範圍第11至18項中任一項之基板處理裝置，其中該控制部會控制該處理部中的電漿處理，俾能夠使用包含有經電漿化後的含氮氣體之第2處理氣體，來將該氧化膜的至少表層改質而形成氮化膜。
  20. 如申請專利範圍第11至18項中任一項之基板處理裝置，其中該控制部會控制該處理部中的電漿處理，俾能夠使用包含有經電漿化後的含碳氣體之第2處理氣體，來將該氧化膜的至少表層改質而形成碳化膜。
  21. 一種奈米線或奈米片之電晶體的製造方法，係使用交互地層積有矽層與矽鍺層的基板所進行之奈米線或奈米片之電晶體的製造方法； 使用經電漿化後且含有氟及氧的處理氣體來將該矽鍺層之露出面的表層選擇性地改質而形成絕緣氧化膜。
  22. 如申請專利範圍第21項之奈米線或奈米片之電晶體的製造方法，其係使用包含有經電漿化後的含氮氣體之第2處理氣體，來將該絕緣氧化膜的至少表層改質而形成氮化膜。
  23. 如申請專利範圍第21項之奈米線或奈米片之電晶體的製造方法，其係使用包含有經電漿化後的含碳氣體之第2處理氣體，來將該絕緣氧化膜的至少表層改質而形成碳化膜。
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