TW202117689A - 畫素電路及其驅動方法 - Google Patents
畫素電路及其驅動方法 Download PDFInfo
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- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
一種畫素電路包含第一、第二、第三、第四、第五和第六電晶體、驅動電晶體和電容。第一電晶體之第一端接收參考電壓。第二電晶體之第一端和第三電晶體之第一端耦接第一電晶體之第二端。第二電晶體之第二端和驅動電晶體之控制端耦接第一節點。第四電晶體之第一端接收資料訊號。第五電晶體之第一端接收系統高電壓。第四電晶體之第二端、第五電晶體之第二端和驅動電晶體之第一端耦接第二節點。驅動電晶體之第二端耦接第三電晶體之第二端和第六電晶體之第一端。第六電晶體之第二端耦接發光元件。電容耦接於第一節點和第五電晶體之第一端之間。
Description
本揭示內容是關於一種畫素電路及其驅動方法,且特別是有關於一種適用於低畫面更新率的畫素電路及其驅動方法。
隨著數位顯示裝置的需求日益增加,低畫面更新率(或稱低幀率,Low Frame Rate)廣泛應用在顯示裝置中,用以降低電源消耗,達到省電、延長使用時間的目的。
然而,在畫面未進行更新時,維持先前畫面的幀數在發光階段顯示的亮度會不穩定,將導致閃爍。
本揭示內容的一態樣係關於一種畫素電路。畫素電路包含第一電晶體、第二電晶體、第三電晶體、第四電晶體、第五電晶體、第六電晶體、驅動電晶體和電容。第一電晶體之第一端接收參考電壓。第二電晶體之第一端耦接第一電晶體之第二端。第二電晶體之第二端耦接第一節點。第三電晶體之第一端耦接第一電晶體之第二端。第四電晶體之第一端接收資料
訊號。第四電晶體之第二端耦接第二節點。第五電晶體之第一端接收系統高電壓。第五電晶體之第二端耦接第二節點。驅動電晶體之控制端耦接第一節點。驅動電晶體之第一端耦接第二節點。驅動電晶體之第二端耦接第三電晶體之第二端。第六電晶體之第一端耦接驅動電晶體之第二端。第六電晶體之第二端耦接發光元件。電容耦接於第一節點和第五電晶體之第一端之間。
本揭示內容的一態樣係關於一種畫素電路驅動方法,包含:在第一幀中,寫入電路維持關斷;在第一幀之第一期間,重置發光元件之陽極端至重置電壓準位;以及在第一幀之第二期間,發光控制電路導通使得驅動電晶體根據系統高電壓輸出驅動電流至發光元件。
900‧‧‧顯示裝置
910‧‧‧控制器
920‧‧‧源極驅動器
930、940‧‧‧閘極驅動器
950‧‧‧顯示面板
100、100a、100b、100c‧‧‧畫素電路
120‧‧‧重置電路
140‧‧‧寫入電路
160‧‧‧補償電路
180‧‧‧發光控制電路
T1、T2、T3、T4、T5、T6、T7、Td‧‧‧電晶體
C1‧‧‧電容
OLED‧‧‧發光元件
N1、N2‧‧‧節點
VST、EMST‧‧‧起始訊號
CK1、CK2、CK3、CKA、CKB、EMA、EMB‧‧‧時脈訊號
S1[1]、S1[2]、S1[3]…S1[k]、S1[n-1]、S1[n]、S1[n+1]、S2[1]、S2[2]、S2[3]…S2[k]、S2[n-1]、S2[n]、S2[n+1]‧‧‧控制訊號
EM[1]、EM[2]、EM[3]…EM[k]、EM[n]、EM[n+1]‧‧‧發光控制訊號
Vref、Vref1、Vref2‧‧‧參考電壓
Vdata‧‧‧資料訊號
OVDD‧‧‧系統高電壓
OVSS‧‧‧系統低電壓
Id‧‧‧驅動電流
F_act、F_skp‧‧‧期間
P1、P2、P3、P4、P5、P6‧‧‧期間
第1圖係根據本揭示內容之部分實施例繪示一種顯示裝置的示意圖。
第2圖係根據本揭示內容之部分實施例繪示一種畫素電路的示意圖。
第3圖係根據本揭示內容之部分實施例繪示一種畫素電路的訊號時序示意圖。
第4A圖和第4B圖係根據本揭示內容之其他部分實施例繪示一種畫素電路的訊號時序放大示意圖。
第5圖係根據本揭示內容之部分實施例繪示在進行畫面更
新中第一期間內第2圖之畫素電路中各電晶體之狀態示意圖。
第6圖係根據本揭示內容之部分實施例繪示在進行畫面更新中第二期間內第2圖之畫素電路中各電晶體之狀態示意圖。
第7圖係根據本揭示內容之部分實施例繪示在進行畫面更新中第四期間內第2圖之畫素電路中各電晶體之狀態示意圖。
第8圖係根據本揭示內容之部分實施例繪示在進行畫面更新中第三期間內第2圖之畫素電路中各電晶體之狀態示意圖。
第9A圖係根據本揭示內容之其他部分實施例繪示另一種畫素電路的示意圖。
第9B圖係根據第9A圖之實施例繪示一種畫素電路的訊號時序示意圖。
第10A圖係根據本揭示內容之其他部分實施例繪示另一種畫素電路的示意圖。
第10B圖係根據第10A圖之實施例繪示一種畫素電路的訊號時序示意圖。
第11圖係根據本揭示內容之其他部分實施例繪示另一種畫素電路100c的示意圖。
下文係舉實施例配合所附圖式作詳細說明,但所描述的具體實施例僅用以解釋本案,並不用來限定本案,而結構操作之描述非用以限制其執行之順序,任何由元件重新組合之結構,所產生具有均等功效的裝置,皆為本揭示內容所涵蓋的範圍。
在全篇說明書與申請專利範圍所使用之用詞(terms),除有特別註明外,通常具有每個用詞使用在此領域中、在此揭示之內容中與特殊內容中的平常意義。
關於本文中所使用之『第一』、『第二』、『第三』...等,並非特別指稱次序或順位的意思,亦非用以限定本揭示,其僅僅是為了區別以相同技術用語描述的元件或操作而已。
另外,關於本文中所使用之「耦接」或「連接」,均可指二或多個元件相互直接作實體或電性接觸,或是相互間接作實體或電性接觸,亦可指二或多個元件相互操作或動作。
本案說明書和圖式中使用的元件編號和信號編號中的小寫英文索引(如:1~k),只是為了方便指稱個別的元件和信號,並非有意將前述元件和信號的數量侷限在特定數目。在本案說明書和圖式中,若使用某一元件編號或信號編號時以n作為該元件編號或信號編號的索引,則指稱所屬元件群組或信號群組中不特定的任一元件或信號。例如,元件編號S1[1]指稱的對象是第一控制訊號S1[1],而元件編號S1[n]指稱的對象則是第一控制訊號S1[1]~S1[k]中不特定的任意第一控制訊號。
請參考第1圖。第1圖係根據本揭示內容之部分實施例繪示一種顯示裝置900的示意圖。如第1圖所示,顯示裝置900包含控制器910、源極驅動器920、閘極驅動器930和940,以及顯示面板950。顯示面板950包含以陣列排列的複數個畫素電路100。結構上,控制器910耦接源極驅動器920、閘
極驅動器930和940。源極驅動器920透過資料線連接顯示面板950中的畫素電路100。閘極驅動器930和940設置於顯示面板950的兩側,透過掃描線連接顯示面板950中的畫素電路100。
操作上,控制器910用以輸出起始訊號VST、時脈訊號CK1、CK2、CK3、CKA和CKB至閘極驅動器930,並用以輸出起始訊號EMST、時脈訊號EMA和EMB至閘極驅動器940。閘極驅動器930用以根據起始訊號VST、時脈訊號CK1、CK2、CK3、CKA和CKB產生第一控制訊號S1[1]~S1[k]和第二控制訊號S2[1]~S2[k],並將第一控制訊號S1[1]~S1[k]和第二控制訊號S2[1]~S2[k]輸出至對應的畫素電路100。閘極驅動器940用以根據起始訊號EMST、時脈訊號EMA和EMB產生發光控制訊號EM[1]~EM[k],並將發光控制訊號EM[1]~EM[k]輸出至對應的畫素電路100。
值得注意的是,雖然在第1圖之實施例中,顯示裝置900包含設置於顯示面板950兩側的閘極驅動器930和940,分別用以輸出不同的控制訊號(如:第一控制訊號S1[1]~S1[k]和第二控制訊號S2[1]~S2[k],以及發光控制訊號EM[1]~EM[k]),但僅為方便說明之示例,並非用以限制本案。在其他部分實施例中,顯示裝置900亦可僅包含設置於顯示面板950任一側的單一閘極驅動器,用以輸出所有的控制訊號。
請參考第2圖。第2圖係根據本揭示內容之部分實施例繪示一種畫素電路100的示意圖。在部分實施例中,畫素電路100可用於主動式液晶顯示器(Active Matrix Liquid
Crystal Displays,AMLCD)、主動式有機發光二極體顯示器(Active Matrix Organic Light Emitting Display,AMOLED)、主動式微發光二極體顯示器(Active Matrix Micro Light Emitting Display,AMOLED,AMμLED)等等。顯示裝置900中可包含多個如第2圖所示的畫素電路100以組成完整的顯示畫面。
如第2圖所示,畫素電路100包含重置電路120、寫入電路140、補償電路160、發光控制電路180、電容C1、驅動電晶體Td和發光元件OLED。驅動電晶體Td包含第一端、第二端和控制端。結構上,重置電路120耦接補償電路160。補償電路160耦接驅動電晶體Td的控制端(即,節點N1)和驅動電晶體Td的第二端。寫入電路140耦接驅動電晶體Td的第一端(即,節點N2)。驅動電晶體Td的第二端透過發光控制電路180耦接發光元件OLED。
具體而言,在部分實施例中,重置電路120包含電晶體T1。補償電路160包含電晶體T2和T3。寫入電路140包含電晶體T4。發光控制電路180包含電晶體T5和T6。在其他部分實施例中,畫素電路100更包含電晶體T7。
驅動電晶體Td的第一端耦接節點N2。驅動電晶體Td的控制端耦接節點N1。驅動電晶體Td用以根據節點N1的電壓準位選擇性地導通或關斷。電容C1第一端用以接收系統高電壓OVDD。電容C1第二端耦接驅動電晶體Td的控制端(即,節點N1)。
電晶體T1的第一端用以接收參考電壓Vref。電晶
體T1的第二端耦接電晶體T2的第一端和電晶體T3的第一端。電晶體T1的控制端用以接收第一控制訊號S1[n]並根據第一控制訊號S1[n]選擇性地導通或關斷。
電晶體T2的第二端耦接驅動電晶體Td的控制端(即,節點N1)。電晶體T3的第二端耦接驅動電晶體Td的第二端。電晶體T2的控制端和電晶體T3的控制端用以接收第二控制訊號S2[n]並根據第二控制訊號S2[n]選擇性地導通或關斷。
電晶體T4的第一端用以接收資料訊號Vdata。電晶體T4的第二端耦接驅動電晶體Td的第一端(即,節點N2)。電晶體T4的控制端用以接收第二控制訊號S2[n]並根據第二控制訊號S2[n]選擇性地導通或關斷。
電晶體T5的第一端用以接收系統高電壓OVDD。電晶體T5的第二端耦接驅動電晶體Td的第一端(即,節點N2)。電晶體T5的控制端用以接收發光控制訊號EM[n]並根據發光控制訊號EM[n]選擇性地導通或關斷。
電晶體T6的第一端耦接驅動電晶體Td的第二端。電晶體T6的第二端耦接發光元件OLED的陽極端。電晶體T6的控制端用以接收發光控制訊號EM[n]並根據發光控制訊號EM[n]選擇性地導通或關斷。
電晶體T7的第一端耦接電晶體T7的控制端。電晶體T7的第二端耦接發光元件OLED的陽極端。電晶體T7用以接收續傳級的第一控制訊號S1[n+1]並根據續傳級的第一控制訊號S1[n+1]選擇性地導通或關斷。發光元件OLED的陽
極端耦接系統低電壓OVSS。
在本實施例中,如第2圖所示,電晶體T1、T2、T3、T4、T5、T6、T7和驅動電晶體Td皆為P型薄膜電晶體,但本案並不以此為限。在其他部分實施例中,本領域具有通常知識者亦可以N型薄膜電晶體據以實現。另外,在部分實施例中,發光元件OLED可為發光二極體或微發光二極體等等。
為便於說明起見,畫素電路100當中各個元件的具體操作將於以下段落中搭配圖式進行說明。請一併參考第2圖和第3圖。第3圖係根據本揭示內容之部分實施例繪示一種畫素電路100的訊號時序示意圖。如第3圖所示,期間F_act和期間F_skp皆為一幀(frame)的時間。為了方便說明起見,一幀中僅繪示兩個畫素電路(當級和續傳級)的控制訊號及其時脈訊號,本領域具有通常知識者可據此推知所有畫素電路(第1級至第k級)的控制訊號。其中,期間F_act中的訊號為一般進行畫面更新時的訊號,而期間F_skp中的訊號為維持前一幀畫面的訊號。換言之,在期間F_skp中不會寫入新的資料訊號Vdata至畫素電路100,然而,在本實施例中,在期間F_skp中仍會對畫素電路100進行發光元件OLED的陽極端重置並進行發光顯示。
在部分實施例中,在一般模式下,顯示裝置900每一幀的訊號皆如期間F_act所示。而在省電模式下,顯示裝置900每一幀的訊號如期間F_act和期間F_skp交替所示。舉例來說,在一般模式下,畫面更新頻率可約為45赫茲。而當顯示裝置900顯示靜態影像、變化幅度較小或變化速度較慢的畫
面內容時,顯示裝置900當前一幀的訊號如期間F_act所示,下一幀的訊號如期間F_skp所示,下下一幀的訊號如期間F_act所示,以此類推。又例如,顯示裝置900以i幀為一循環,循環中第1幀的訊號如期間F_act所示,第2~i幀的訊號如期間F_skp所示,其中i為大於1的任意正整數。如此一來,當i為3時,第1幀會進行畫面更新,第2幀和第3幀不進行畫面更新,則畫面更新頻率約為45/3=15赫茲。
具體而言,如第3圖所示,在期間F_act,時脈訊號CK1、CK2、CK3、CKA、CKB、EMA、EMB切換於低準位和高準位之間,起始訊號VST、控制訊號S1[n]、S2[n]、S1[n+1]、S2[n+1]依序由高準位轉為低準位,起始訊號EMST、發光控制訊號EM[n]、EM[n+1]依序由關斷電壓準位轉為導通電壓準位。
換言之,在期間F_act,閘極驅動器930用以根據時脈訊號CK1、CK2、CK3、CKA、CKB和起始訊號VST產生控制訊號S1[n]、S2[n]、S1[n+1]、S2[n+1],閘極驅動器940用以根據時脈訊號EMA、EMB和起始訊號EMST產生發光控制訊號EM[n]、EM[n+1],使得畫素電路100根據控制訊號S1[n]、S2[n]、S1[n+1]、S2[n+1]進行重置、寫入、補償和發光。
關於期間F_act中進行畫面更新時的訊號的進一步詳細說明,請參考第4A圖。第4A圖係根據本揭示內容之其他部分實施例繪示一種畫素電路100在期間F_act中的訊號時序放大示意圖。如第4A圖所示,在部分實施例中,期間F_act
包含期間P1、期間P2和期間P3。具體而言,期間P1為重置和寫入階段,期間P2為補償階段,期間P3為發光階段。在其他部分實施例中,期間F_act更包含期間P4。具體而言,期間P4為重置發光元件OLED的陽極端的階段。
請一併參考第4A圖和第5圖。第5圖係根據本揭示內容之部分實施例繪示在進行畫面更新(期間F_act)中第一期間P1(即重置和寫入階段)內第2圖之畫素電路100中各電晶體之狀態示意圖。如第4A圖所示,在期間P1中,發光控制訊號EM[n]先轉為關斷電壓準位,例如對於P型電晶體而言為高電壓準位(即第4A圖所示的高準位)。接著,第一控制訊號S1[n]和第二控制訊號S2[n]依序轉為導通電壓準位,例如對於P型電晶體而言為低電壓準位(如第4A圖所示的低準位)。
如第5圖所示,電晶體T5和T6根據高準位的發光控制訊號EM[n]關斷,接著,電晶體T1根據低準位的第一控制訊號S1[n]導通以提供參考電壓Vref至電晶體T2和T3的第一端。接著,電晶體T2和T3根據低準位的第二控制訊號S2[n]導通以提供參考電壓Vref至節點N1。同時,電晶體T4根據低準位的第二控制訊號S2[n]導通以提供資料訊號Vdata至節點N2。
因此,在期間P1,驅動電晶體Td的控制端(即,節點N1)被重置至參考電壓Vref,驅動電晶體Td的第一端(即,節點N2)接收寫入資料訊號Vdata。此外,在期間P1,續傳級的第一控制訊號S1[n+1]維持關斷電壓準位(如第4A圖所示的高準位),因此,電晶體T7維持關斷。
接著,請一併參考第4A圖和第6圖。第6圖係根據本揭示內容之部分實施例繪示在進行畫面更新(期間F_act)中第二期間P2(即補償階段)內第2圖之畫素電路100中各電晶體之狀態示意圖。如第4A圖所示,在期間P2中,第一控制訊號S1[n]轉為關斷電壓準位(如第4A圖所示的高準位)。由於其他訊號維持不變,在此不再贅述。如第6圖所示,電晶體T1根據高準位的第一控制訊號S1[n]關斷,電晶體T2、T3和T4維持導通,而電晶體T5、T6和T7維持關斷。
因此,在期間P2,驅動電晶體Td的第一端和控制端的電壓差為資料訊號Vdata減去參考電壓Vref,此電壓差大於驅動電晶體Td的臨界電壓而使得驅動電晶體Td導通。導通後的驅動電晶體Td根據其第一端的資料訊號Vdata對其第二端和其控制端充電,直到驅動電晶體Td的第一端和控制端之間的電壓差縮小至驅動電晶體Td的臨界電壓。也就是說,在期間P2,驅動電晶體Td的控制端(即,節點N1)被補償至補償電壓準位,此補償電壓準位即為資料訊號Vdata減去驅動電晶體Td的臨界電壓。
接著,請一併參考第4A圖和第7圖。第7圖係根據本揭示內容之部分實施例繪示在進行畫面更新(期間F_act)中第四期間P4(即重置發光元件OLED陽極端的階段)內第2圖之畫素電路100中各電晶體之狀態示意圖。如第4A圖所示,在期間P2結束時,第二控制訊號S2[n]轉為關斷電壓準位。而在期間P4中,續傳級的第一控制訊號S1[n+1]轉為導通電壓準位(如第4A圖所示的低準位)。由於其他訊號維持不變,在
此不再贅述。
如第7圖所示,電晶體T1、T2、T3、T4、T5和T6關斷,電晶體T7根據低準位的第一控制訊號S1[n+1]導通,使得發光元件OLED之陽極端被重置至重置電壓準位(即低準位)。如此一來,藉由續傳級的第一控制訊號S1[n+1],便能在發光階段前確保發光元件OLED沒有殘存的電荷。
接著,請一併參考第4A圖和第8圖。第8圖係根據本揭示內容之部分實施例繪示在進行畫面更新(期間F_act)中第三期間P3(即發光階段)內第2圖之畫素電路100中各電晶體之狀態示意圖。如第4A圖所示,在期間P3中,發光控制訊號EM[n]轉為導通電壓準位(如第4A圖所示的低準位),其他訊號維持不變,在此不再贅述。如第8圖所示,電晶體T1、T2、T3、T4和T7關斷,電晶體T5和T6根據低準位的發光控制訊號EM[n]導通,以提供系統高電壓OVDD至驅動電晶體Td的第一端(即,節點N1),使得驅動電晶體Td輸出驅動電流Id如下式(1)所示:
其中Vth為驅動電晶體Td的臨界電壓。k為導電參數(Conduction Parameter)。如此一來,藉由期間P2所產生的補償電壓進行補償,便能使畫素電路100進行顯示時,驅動電流Id的電流大小將不受驅動電晶體Td的元件特性(如臨界電壓不同)而影響,可提供相對穩定的驅動電流Id。
請回頭參考第3圖。在期間F_skp,相似於期間
F_act,時脈訊號CK1、CK2、CK3、EMA、EMB切換於低準位和高準位之間,起始訊號VST、控制訊號S1[n]、S1[n+1]依序由高準位轉為低準位,起始訊號EMST、發光控制訊號EM[n]、EM[n+1]依序由關斷電壓準位轉為導通電壓準位。然而,在期間F_skp,時脈訊號CKA、CKB、控制訊號S2[n]、S2[n+1]一直維持在高準位。
換言之,在期間F_skp,閘極驅動器930用以根據時脈訊號CK1、CK2、CK3和起始訊號VST產生控制訊號S1[n]、S1[n+1],閘極驅動器940用以根據時脈訊號EMA、EMB和起始訊號EMST產生發光控制訊號EM[n]、EM[n+1],使得畫素電路100根據控制訊號S1[n+1]進行發光元件OLED的陽極端的重置並進行發光,但不寫入資料訊號Vdata。此外,在期間F_skp,雖然仍會持續地提供參考電壓Vref,但由於在此期間控制訊號S2[n]不會作動,因此節點N1的電壓不會被重置。
關於期間F_skp中維持前一幀畫面的訊號的進一步詳細說明,請參考第4B圖。第4B圖係根據本揭示內容之其他部分實施例繪示一種畫素電路100在期間F_skp中的訊號時序放大示意圖。如第4B圖所示,在部分實施例中,期間F_skp包含期間P5和期間P6。具體而言,期間P5為重置發光元件OLED的陽極端的階段。期間P6為發光階段。
如第4B圖所示,在期間P5中,相似於期間F_act中的期間P4,續傳級的第一控制訊號S1[n+1]轉為導通電壓準位,其他訊號皆為關斷電壓準位。因此,電晶體T1、T2、T3、
T4、T5和T6關斷,電晶體T7根據低準位的第一控制訊號S1[n+1]導通,使得發光元件OLED之陽極端被重置至重置電壓準位(即低準位)。
在期間P6中,相似於期間F_act中的期間P3,發光控制訊號EM[n]轉為導通電壓準位,其他訊號皆為關斷電壓準位。因此,電晶體T1、T2、T3、T4和T7關斷,電晶體T5和T6根據低準位的發光控制訊號EM[n]導通,以提供系統高電壓OVDD至驅動電晶體Td的第一端(即,節點N1),使得驅動電晶體Td輸出驅動電流Id。
如此一來,即便在維持前一幀畫面訊號的期間F_skp中,由於起始訊號VST和時脈訊號CK1、CK2、CK3的持續作動,因此藉由續傳級的第一控制訊號S1[n+1],便能在發光階段前重置發光元件OLED的陽極端,以確保發光元件OLED沒有殘存的電荷影響發光亮度。並且,藉由本案提出的畫素電路100的設計,驅動電晶體Td的控制端(即,節點N1)的電壓準位較不容易受到影響,在期間F_skp中仍可保持與在期間F_act的期間P3中相近的電壓準位。因此,在期間F_skp中的期間P6和期間F_act中的期間P3的發光亮度能較為接近。此外,由於在期間F_skp中不提供進行重置的參考電壓Vref,也不寫入資料訊號Vdata,可達到節省電力消耗。
值得注意的是,雖然在本案實施例中,電晶體T7是以接收續傳級的第一控制訊號S1[n+1]為例進行說明,然而本揭示內容不以此為限,本領與具有通常知識者可依據實際需求進行調整設計。
請參考第9A圖和第9B圖。第9A圖係根據本揭示內容之其他部分實施例繪示另一種畫素電路100a的示意圖。第9B圖係根據第9A圖之實施例繪示一種畫素電路100a的訊號時序示意圖。如第9A圖所示,在部分實施例中,電晶體T7可用以接收當級的第一控制訊號S1[n]。如第9B圖所示之第一控制訊號S1[n]由高準位轉為低準位時,畫素電路100a的電晶體T1和T7一起導通。接著,第二控制訊號S2[n]也由高準位轉為低準位。如此一來,畫素電路100a在將節點N1重置到參考電壓Vref的同時,亦將發光元件OLED的陽極端重置到低準位。接著,再進行發光顯示。
請參考第10A圖和第10B圖。第10A圖係根據本揭示內容之其他部分實施例繪示另一種畫素電路100b的示意圖。第10B圖係根據第10A圖之實施例繪示一種畫素電路100b的訊號時序示意圖。如第10A圖所示,在其他部分實施例中,電晶體T7可用以接收前一級的第一控制訊號S1[n-1]。如第10B圖所示之第一控制訊號S1[n-1]由高準位轉為低準位時,畫素電路100b的電晶體T7導通,因而將發光元件OLED的陽極端重置到低準位。接著,第一控制訊號S1[n]和第二控制訊號S2[n]依序由高準位轉為低準位,畫素電路100b的電晶體T1和T2導通,再將節點N1重置到參考電壓Vref。最後,再進行發光顯示。
請參考第11圖。第10A圖係根據本揭示內容之其他部分實施例繪示另一種畫素電路100c的示意圖。如第11圖所示,在其他部份實施例中,電晶體T1的第一端用以接收參
考電壓Vref1。電晶體T7的第一端用以接收參考電壓Vref2。電晶體T7的控制端用以接收第一控制訊號S1[n+1]並根據第一控制訊號S1[n+1]選擇性地導通或關斷。其中,參考電壓Vref1、Vref2和上述的參考電壓Vref可以是相同、不完全相同,或者完全不同的電壓準位。此外,雖然在第11圖所繪示之實施例中,電晶體T7的控制端是以接收續傳級的第一控制訊號S1[n+1],然而本揭示內容不以此為限。相似於第9A圖~第10B圖及其相關說明,在其他部分實施例中,電晶體T7的控制端可用以接收當級的第一控制訊號S1[n],或者用以接收前一級的第一控制訊號S1[n-1]。
雖然本文將所公開的方法示出和描述為一系列的步驟或事件,但是應當理解,所示出的這些步驟或事件的順序不應解釋為限制意義。例如,部分步驟可以以不同順序發生和/或與除了本文所示和/或所描述之步驟或事件以外的其他步驟或事件同時發生。另外,實施本文所描述的一個或多個態樣或實施例時,並非所有於此示出的步驟皆為必需。此外,本文中的一個或多個步驟亦可能在一個或多個分離的步驟和/或階段中執行。
綜上所述,本案透過應用上述各個實施例中,在維持前一幀畫面訊號的期間F_skp中,不寫入新的資料訊號Vdata至畫素電路100,但仍對畫素電路100進行重置並進行發光顯示。藉由畫素電路100的設計以及重置發光元件OLED的陽極端,使得發光元件OLED不會有殘存的電荷影響發光亮度,且驅動電晶體Td的控制端的電壓準位較能保持與在進行
畫面訊號更新的期間F_act中相近的電壓準位。如此一來,便能在降低畫面更新率時,達到節省功耗並穩定發光亮度,避免產生閃爍的現象。
雖然本揭示內容已以實施方式揭露如上,然其並非用以限定本揭示內容,所屬技術領域具有通常知識者在不脫離本揭示內容之精神和範圍內,當可作各種更動與潤飾,因此本揭示內容之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧畫素電路
120‧‧‧重置電路
140‧‧‧寫入電路
160‧‧‧補償電路
180‧‧‧發光控制電路
T1、T2、T3、T4、T5、T6、T7、Td‧‧‧電晶體
C1‧‧‧電容
OLED‧‧‧發光元件
N1、N2‧‧‧節點
S1[n]、S2[n]、S1[n+1]‧‧‧控制訊號
EM[n]‧‧‧發光控制訊號
Vref‧‧‧參考電壓
Vdata‧‧‧資料訊號
OVDD‧‧‧系統高電壓
OVSS‧‧‧系統低電壓
Claims (11)
- 一種畫素電路,包含:一第一電晶體,該第一電晶體之一第一端接收一第一參考電壓;一第二電晶體,該第二電晶體之一第一端耦接該第一電晶體之一第二端,該第二電晶體之一第二端耦接一第一節點;一第三電晶體,該第三電晶體之一第一端耦接該第一電晶體之一第二端;一第四電晶體,該第四電晶體之一第一端接收一資料訊號,該第四電晶體之一第二端耦接一第二節點;一第五電晶體,該第五電晶體之一第一端接收一系統高電壓,該第五電晶體之一第二端耦接該第二節點;一驅動電晶體,該驅動電晶體之一控制端耦接該第一節點,該驅動電晶體之一第一端耦接該第二節點,該驅動電晶體之一第二端耦接該第三電晶體之該第二端;一第六電晶體,該第六電晶體之一第一端耦接該驅動電晶體之該第二端,該第六電晶體之一第二端耦接一發光元件;以及一電容,該電容耦接於該第一節點和該第五電晶體之該第一端之間。
- 如請求項1所述之畫素電路,更包含:一第七電晶體,該第七電晶體之一第一端和該第七電晶體之一控制端相互耦接,該第七電晶體之一第二端耦接該發 光元件之一陽極端。
- 如請求項2所述之畫素電路,其中該第一電晶體用以根據一第一控制訊號選擇性地導通,該第二電晶體、第三電晶體和第四電晶體用以根據一第二控制訊號選擇性地導通,該第七電晶體用以根據一第三控制訊號選擇性地導通,該第五電晶體和該第六電晶體用以根據一發光控制訊號選擇性地導通。
- 如請求項3所述之畫素電路,其中在一第一幀之一第一期間,該第一控制訊號和該第二控制訊號切換至一導通電壓準位,使得該第一電晶體、該第二電晶體、該第三電晶體和該第四電晶體導通,以提供該第一參考電壓至該第一節點,並提供該資料訊號至該第二節點,在該第一幀之一第二期間,該第一控制訊號切換至一關斷電壓準位,該第二控制訊號維持於該導通電壓準位,使得該第二電晶體、該第三電晶體和該第四電晶體導通,以提供一補償電壓至該第一節點,在該第一幀之一第三期間,該發光控制訊號切換至該導通電壓準位,使得該第五電晶體和第六電晶體導通,以輸出一驅動電流至該發光元件。
- 如請求項3所述之畫素電路,其中在一第二幀中,該第二控制訊號維持於一關斷電壓準位,在該第二幀之一第一期間,該第三控制訊號切換至一導 通電壓準位使得該第七電晶體導通,在該第二幀之一第二期間,該發光控制訊號切換至該導通電壓準位使得該發光元件接收一驅動電流進行發光。
- 如請求項1所述之畫素電路,更包含:一第七電晶體,該第七電晶體之一第一端用以接收一第二參考電壓,該第七電晶體之一控制端用以接收一第一控制訊號或一第三控制訊號,該第七電晶體之一第二端耦接該發光元件之一陽極端,該第二參考電壓不同於該第一參考電壓。
- 一種畫素電路驅動方法,包含:在一第一幀中,一寫入電路進行寫入,一發光元件進行發光;在一第二幀中,該寫入電路維持關斷;在該第二幀之一第一期間,重置一發光元件之一陽極端至一重置電壓準位;以及在該第二幀之一第二期間,一發光控制電路導通使得一驅動電晶體根據一系統高電壓輸出一驅動電流至該發光元件。
- 如請求項7所述之畫素電路驅動方法,更包含:在該第一幀之一第一期間,重置該驅動電晶體之一控制端至一第一參考電壓,並由一寫入電路提供一資料訊號至該 驅動電晶體之一第一端;在該第一幀之一第二期間,由一補償電路提供一補償電壓至該驅動電晶體之該控制端;以及在該第一幀之一第三期間,該發光控制電路導通使得該驅動電晶體根據該系統高電壓和該補償電壓輸出該驅動電流至該發光元件。
- 如請求項7所述之畫素電路驅動方法,更包含:在該第一幀之一第一期間,一第一電晶體根據一第一控制訊號導通,一第二電晶體、一第三電晶體和一第四電晶體根據一第二控制訊號導通,以重置該驅動電晶體之一控制端至一第一參考電壓,並提供一資料訊號至該驅動電晶體之一第一端;在該第一幀之一第二期間,該第一電晶體根據該第一控制訊號關斷,該第二電晶體、該第三電晶體和該第四電晶體根據該第二控制訊號導通,以提供一補償電壓至該驅動電晶體之該控制端;以及在該第一幀之一第三期間,一第五電晶體和一第六電晶體根據一發光控制訊號導通使得該驅動電晶體根據該系統高電壓和該補償電壓輸出該驅動電流至該發光元件。
- 如請求項9所述之畫素電路驅動方法,更包含:在該第一幀之一第四期間,一第七電晶體根據一第三控制訊號導通以重置該發光元件之該陽極端至該重置電壓準位。
- 如請求項10所述之畫素電路驅動方法,更包含:一閘極驅動器根據一第一組時脈訊號以產生該第一控制訊號和該第三控制訊號,並根據一第二組時脈訊號以產生該第二控制訊號,其中,在該第二幀,該第一組時脈訊號切換於一高準位和一低準位之間,該第二組時脈訊號維持於該高準位。
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TWI533278B (zh) * | 2014-10-31 | 2016-05-11 | 友達光電股份有限公司 | 畫素結構及其驅動方法 |
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CN108877664A (zh) * | 2017-05-12 | 2018-11-23 | 京东方科技集团股份有限公司 | 像素电路及其驱动方法、显示面板 |
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TWI652661B (zh) * | 2018-06-07 | 2019-03-01 | 友達光電股份有限公司 | 畫素電路 |
CN109243369A (zh) * | 2018-09-28 | 2019-01-18 | 昆山国显光电有限公司 | 显示面板、像素电路的驱动方法及显示装置 |
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2019
- 2019-10-17 TW TW108137549A patent/TWI720655B/zh active
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2020
- 2020-04-02 CN CN202010254787.XA patent/CN111341267B/zh active Active
- 2020-08-19 US US16/997,047 patent/US11244623B2/en active Active
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US20210118367A1 (en) | 2021-04-22 |
CN111341267B (zh) | 2021-04-16 |
CN111341267A (zh) | 2020-06-26 |
US11244623B2 (en) | 2022-02-08 |
TWI720655B (zh) | 2021-03-01 |
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