CN111341267B - 像素电路及其驱动方法 - Google Patents
像素电路及其驱动方法 Download PDFInfo
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Abstract
本发明公开了一种像素电路,包含第一、第二、第三、第四、第五和第六晶体管、驱动晶体管和电容。第一晶体管的第一端接收参考电压。第二晶体管的第一端和第三晶体管的第一端耦接第一晶体管的第二端。第二晶体管的第二端和驱动晶体管的控制端耦接第一节点。第四晶体管的第一端接收数据信号。第五晶体管的第一端接收系统高电压。第四晶体管的第二端、第五晶体管的第二端和驱动晶体管的第一端耦接第二节点。驱动晶体管的第二端耦接第三晶体管的第二端和第六晶体管的第一端。第六晶体管的第二端耦接发光元件。电容耦接于第一节点和第五晶体管的第一端之间。
Description
技术领域
本发明是关于一种像素电路及其驱动方法,且特别是有关于一种适用于低画面更新率的像素电路及其驱动方法。
背景技术
随着数字显示装置的需求日益增加,低画面更新率(或称低帧率,Low FrameRate)广泛应用在显示装置中,用以降低电源消耗,达到省电、延长使用时间的目的。
然而,在画面未进行更新时,维持先前画面的帧数在发光阶段显示的亮度会不稳定,将导致闪烁。
发明内容
本发明的一态样系关于一种像素电路。像素电路包含第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、驱动晶体管和电容。第一晶体管的第一端接收参考电压。第二晶体管的第一端耦接第一晶体管的第二端。第二晶体管的第二端耦接第一节点。第三晶体管的第一端耦接第一晶体管的第二端。第四晶体管的第一端接收数据信号。第四晶体管的第二端耦接第二节点。第五晶体管的第一端接收系统高电压。第五晶体管的第二端耦接第二节点。驱动晶体管的控制端耦接第一节点。驱动晶体管的第一端耦接第二节点。驱动晶体管的第二端耦接第三晶体管的第二端。第六晶体管的第一端耦接驱动晶体管的第二端。第六晶体管的第二端耦接发光元件。电容耦接于第一节点和第五晶体管的第一端之间。
本发明的一态样系关于一种像素电路驱动方法,包含:在第一帧中,写入电路维持关断;在第一帧的第一期间,重置发光元件的阳极端至重置电压电平;以及在第一帧的第二期间,发光控制电路导通使得驱动晶体管根据系统高电压输出驱动电流至发光元件。
附图说明
图1是根据本发明的部分实施例绘示一种显示装置的示意图。
图2是根据本发明的部分实施例绘示一种像素电路的示意图。
图3是根据本发明的部分实施例绘示一种像素电路的信号时序示意图。
图4A和图4B是根据本发明的其他部分实施例绘示一种像素电路的信号时序放大示意图。
图5是根据本发明的部分实施例绘示在进行画面更新中第一期间内图2的像素电路中各晶体管的状态示意图。
图6是根据本发明的部分实施例绘示在进行画面更新中第二期间内图2的像素电路中各晶体管的状态示意图。
图7是根据本发明的部分实施例绘示在进行画面更新中第四期间内图2的像素电路中各晶体管的状态示意图。
图8是根据本发明的部分实施例绘示在进行画面更新中第三期间内图2的像素电路中各晶体管的状态示意图。
图9A是根据本发明的其他部分实施例绘示另一种像素电路的示意图。
图9B是根据图9A的实施例绘示一种像素电路的信号时序示意图。
图10A是根据本发明的其他部分实施例绘示另一种像素电路的示意图。
图10B是根据图10A的实施例绘示一种像素电路的信号时序示意图。
图11是根据本发明的其他部分实施例绘示另一种像素电路100c的示意图。
其中,附图标记:
900:显示装置
910:控制器
920:源极驱动器
930、940:栅极驱动器
950:显示面板
100、100a、100b、100c:像素电路
120:重置电路
140:写入电路
160:补偿电路
180:发光控制电路
T1、T2、T3、T4、T5、T6、T7、Td:晶体管
C1:电容
OLED:发光元件
N1、N2:节点
VST、EMST:起始信号
CK1、CK2、CK3、CKA、CKB、EMA、EMB:时脉信号
S1[1]、S1[2]、S1[3]…S1[k]、S1[n-1]、S1[n]、S1[n+1]、S2[1]、S2[2]、S2[3]…S2[k]、S2[n-1]、S2[n]、S2[n+1]:控制信号
EM[1]、EM[2]、EM[3]…EM[k]、EM[n]、EM[n+1]:发光控制信号
Vref、Vref1、Vref2:参考电压
Vdata:数据信号
OVDD:系统高电压
OVSS:系统低电压
Id:驱动电流
F_act、F_skp:期间
P1、P2、P3、P4、P5、P6:期间
具体实施方式
下文系举实施例配合所附图式作详细说明,但所描述的具体实施例仅用以解释本案,并不用来限定本案,而结构操作的描述非用以限制其执行的顺序,任何由元件重新组合的结构,所产生具有均等功效的装置,皆为本发明所涵盖的范围。
在全篇说明书与申请专利范围所使用的用词(terms),除有特别注明外,通常具有每个用词使用在此领域中、在此揭示的内容中与特殊内容中的平常意义。
关于本文中所使用的“第一”、“第二”、“第三”…等,并非特别指称次序或顺位的意思,亦非用以限定本揭示,其仅仅是为了区别以相同技术用语描述的元件或操作而已。
另外,关于本文中所使用的“耦接”或“连接”,均可指二或多个元件相互直接作实体或电性接触,或是相互间接作实体或电性接触,亦可指二或多个元件相互操作或动作。
本案说明书和图式中使用的元件编号和信号编号中的小写英文索引(如:1~k),只是为了方便指称个别的元件和信号,并非有意将前述元件和信号的数量局限在特定数目。在本案说明书和图式中,若使用某一元件编号或信号编号时以n作为该元件编号或信号编号的索引,则指称所属元件群组或信号群组中不特定的任一元件或信号。例如,元件编号S1[1]指称的对象是第一控制信号S1[1],而元件编号S1[n]指称的对象则是第一控制信号S1[1]~S1[k]中不特定的任意第一控制信号。
请参考图1。图1是根据本发明的部分实施例绘示一种显示装置900的示意图。如图1所示,显示装置900包含控制器910、源极驱动器920、栅极驱动器930和940,以及显示面板950。显示面板950包含以阵列排列的多个像素电路100。结构上,控制器910耦接源极驱动器920、栅极驱动器930和940。源极驱动器920通过数据线连接显示面板950中的像素电路100。栅极驱动器930和940设置于显示面板950的两侧,通过扫描线连接显示面板950中的像素电路100。
操作上,控制器910用以输出起始信号VST、时脉信号CK1、CK2、CK3、CKA和CKB至栅极驱动器930,并用以输出起始信号EMST、时脉信号EMA和EMB至栅极驱动器940。栅极驱动器930用以根据起始信号VST、时脉信号CK1、CK2、CK3、CKA和CKB产生第一控制信号S1[1]~S1[k]和第二控制信号S2[1]~S2[k],并将第一控制信号S1[1]~S1[k]和第二控制信号S2[1]~S2[k]输出至对应的像素电路100。栅极驱动器940用以根据起始信号EMST、时脉信号EMA和EMB产生发光控制信号EM[1]~EM[k],并将发光控制信号EM[1]~EM[k]输出至对应的像素电路100。
值得注意的是,虽然在图1的实施例中,显示装置900包含设置于显示面板950两侧的栅极驱动器930和940,分别用以输出不同的控制信号(如:第一控制信号S1[1]~S1[k]和第二控制信号S2[1]~S2[k],以及发光控制信号EM[1]~EM[k]),但仅为方便说明的示例,并非用以限制本案。在其他部分实施例中,显示装置900亦可仅包含设置于显示面板950任一侧的单一栅极驱动器,用以输出所有的控制信号。
请参考图2。图2是根据本发明的部分实施例绘示一种像素电路100的示意图。在部分实施例中,像素电路100可用于主动式液晶显示器(Active Matrix Liquid CrystalDisplays,AMLCD)、主动式有机发光二极管显示器(Active Matrix Organic LightEmitting Display,AMOLED)、主动式微发光二极管显示器(Active Matrix Micro LightEmitting Display,AMOLED,AMμLED)等等。显示装置900中可包含多个如图2所示的像素电路100以组成完整的显示画面。
如图2所示,像素电路100包含重置电路120、写入电路140、补偿电路160、发光控制电路180、电容C1、驱动晶体管Td和发光元件OLED。驱动晶体管Td包含第一端、第二端和控制端。结构上,重置电路120耦接补偿电路160。补偿电路160耦接驱动晶体管Td的控制端(即,节点N1)和驱动晶体管Td的第二端。写入电路140耦接驱动晶体管Td的第一端(即,节点N2)。驱动晶体管Td的第二端通过发光控制电路180耦接发光元件OLED。
具体而言,在部分实施例中,重置电路120包含晶体管T1。补偿电路160包含晶体管T2和T3。写入电路140包含晶体管T4。发光控制电路180包含晶体管T5和T6。在其他部分实施例中,像素电路100更包含晶体管T7。
驱动晶体管Td的第一端耦接节点N2。驱动晶体管Td的控制端耦接节点N1。驱动晶体管Td用以根据节点N1的电压电平选择性地导通或关断。电容C1的第一端用以接收系统高电压OVDD。电容C1的第二端耦接驱动晶体管Td的控制端(即,节点N1)。
晶体管T1的第一端用以接收参考电压Vref。晶体管T1的第二端耦接晶体管T2的第一端和晶体管T3的第一端。晶体管T1的控制端用以接收第一控制信号S1[n]并根据第一控制信号S1[n]选择性地导通或关断。
晶体管T2的第二端耦接驱动晶体管Td的控制端(即,节点N1)。晶体管T3的第二端耦接驱动晶体管Td的第二端。晶体管T2的控制端和晶体管T3的控制端用以接收第二控制信号S2[n]并根据第二控制信号S2[n]选择性地导通或关断。
晶体管T4的第一端用以接收数据信号Vdata。晶体管T4的第二端耦接驱动晶体管Td的第一端(即,节点N2)。晶体管T4的控制端用以接收第二控制信号S2[n]并根据第二控制信号S2[n]选择性地导通或关断。
晶体管T5的第一端用以接收系统高电压OVDD。晶体管T5的第二端耦接驱动晶体管Td的第一端(即,节点N2)。晶体管T5的控制端用以接收发光控制信号EM[n]并根据发光控制信号EM[n]选择性地导通或关断。
晶体管T6的第一端耦接驱动晶体管Td的第二端。晶体管T6的第二端耦接发光元件OLED的阳极端。晶体管T6的控制端用以接收发光控制信号EM[n]并根据发光控制信号EM[n]选择性地导通或关断。
晶体管T7的第一端耦接晶体管T7的控制端。晶体管T7的第二端耦接发光元件OLED的阳极端。晶体管T7用以接收续传级的第一控制信号S1[n+1]并根据续传级的第一控制信号S1[n+1]选择性地导通或关断。发光元件OLED的阳极端耦接系统低电压OVSS。
在本实施例中,如图2所示,晶体管T1、T2、T3、T4、T5、T6、T7和驱动晶体管Td皆为P型薄膜晶体管,但本案并不以此为限。在其他部分实施例中,本领域具有通常知识者亦可以N型薄膜晶体管据以实现。另外,在部分实施例中,发光元件OLED可为发光二极管或微发光二极管等等。
为便于说明起见,像素电路100当中各个元件的具体操作将于以下段落中搭配图式进行说明。请一并参考图2和图3。图3是根据本发明的部分实施例绘示一种像素电路100的信号时序示意图。如图3所示,期间F_act和期间F_skp皆为一帧(frame)的时间。为了方便说明起见,一帧中仅绘示两个像素电路(当级和续传级)的控制信号及其时脉信号,本领域具有通常知识者可据此推知所有像素电路(第1级至第k级)的控制信号。其中,期间F_act中的信号为一般进行画面更新时的信号,而期间F_skp中的信号为维持前一帧画面的信号。换言之,在期间F_skp中不会写入新的数据信号Vdata至像素电路100,然而,在本实施例中,在期间F_skp中仍会对像素电路100进行发光元件OLED的阳极端重置并进行发光显示。
在部分实施例中,在一般模式下,显示装置900每一帧的信号皆如期间F_act所示。而在省电模式下,显示装置900每一帧的信号如期间F_act和期间F_skp交替所示。举例来说,在一般模式下,画面更新频率可约为45赫兹。而当显示装置900显示静态影像、变化幅度较小或变化速度较慢的画面内容时,显示装置900当前一帧的信号如期间F_act所示,下一帧的信号如期间F_skp所示,下下一帧的信号如期间F_act所示,以此类推。又例如,显示装置900以i帧为一循环,循环中第1帧的信号如期间F_act所示,第2~i帧的信号如期间F_skp所示,其中i为大于1的任意正整数。如此一来,当i为3时,第1帧会进行画面更新,第2帧和第3帧不进行画面更新,则画面更新频率约为45/3=15赫兹。
具体而言,如图3所示,在期间F_act,时脉信号CK1、CK2、CK3、CKA、CKB、EMA、EMB切换于低电平和高电平之间,起始信号VST、控制信号S1[n]、S2[n]、S1[n+1]、S2[n+1]依序由高电平转为低电平,起始信号EMST、发光控制信号EM[n]、EM[n+1]依序由关断电压电平转为导通电压电平。
换言之,在期间F_act,栅极驱动器930用以根据时脉信号CK1、CK2、CK3、CKA、CKB和起始信号VST产生控制信号S1[n]、S2[n]、S1[n+1]、S2[n+1],栅极驱动器940用以根据时脉信号EMA、EMB和起始信号EMST产生发光控制信号EM[n]、EM[n+1],使得像素电路100根据控制信号S1[n]、S2[n]、S1[n+1]、S2[n+1]进行重置、写入、补偿和发光。
关于期间F_act中进行画面更新时的信号的进一步详细说明,请参考图4A。图4A是根据本发明的其他部分实施例绘示一种像素电路100在期间F_act中的信号时序放大示意图。如图4A所示,在部分实施例中,期间F_act包含期间P1、期间P2和期间P3。具体而言,期间P1为重置和写入阶段,期间P2为补偿阶段,期间P3为发光阶段。在其他部分实施例中,期间F_act更包含期间P4。具体而言,期间P4为重置发光元件OLED的阳极端的阶段。
请一并参考图4A和图5。图5是根据本发明的部分实施例绘示在进行画面更新(期间F_act)中第一期间P1(即重置和写入阶段)内图2的像素电路100中各晶体管的状态示意图。如图4A所示,在期间P1中,发光控制信号EM[n]先转为关断电压电平,例如对于P型晶体管而言为高电压电平(即图4A所示的高电平)。接着,第一控制信号S1[n]和第二控制信号S2[n]依序转为导通电压电平,例如对于P型晶体管而言为低电压电平(如图4A所示的低电平)。
如图5所示,晶体管T5和T6根据高电平的发光控制信号EM[n]关断,接着,晶体管T1根据低电平的第一控制信号S1[n]导通以提供参考电压Vref至晶体管T2和T3的第一端。接着,晶体管T2和T3根据低电平的第二控制信号S2[n]导通以提供参考电压Vref至节点N1。同时,晶体管T4根据低电平的第二控制信号S2[n]导通以提供数据信号Vdata至节点N2。
因此,在期间P1,驱动晶体管Td的控制端(即,节点N1)被重置至参考电压Vref,驱动晶体管Td的第一端(即,节点N2)接收写入数据信号Vdata。此外,在期间P1,续传级的第一控制信号S1[n+1]维持关断电压电平(如图4A所示的高电平),因此,晶体管T7维持关断。
接着,请一并参考图4A和图6。图6是根据本发明的部分实施例绘示在进行画面更新(期间F_act)中第二期间P2(即补偿阶段)内图2的像素电路100中各晶体管的状态示意图。如图4A所示,在期间P2中,第一控制信号S1[n]转为关断电压电平(如图4A所示的高电平)。由于其他信号维持不变,在此不再赘述。如图6所示,晶体管T1根据高电平的第一控制信号S1[n]关断,晶体管T2、T3和T4维持导通,而晶体管T5、T6和T7维持关断。
因此,在期间P2,驱动晶体管Td的第一端和控制端的电压差为数据信号Vdata减去参考电压Vref,此电压差大于驱动晶体管Td的临界电压而使得驱动晶体管Td导通。导通后的驱动晶体管Td根据其第一端的数据信号Vdata对其第二端和其控制端充电,直到驱动晶体管Td的第一端和控制端之间的电压差缩小至驱动晶体管Td的临界电压。也就是说,在期间P2,驱动晶体管Td的控制端(即,节点N1)被补偿至补偿电压电平,此补偿电压电平即为数据信号Vdata减去驱动晶体管Td的临界电压。
接着,请一并参考图4A和图7。图7是根据本发明的部分实施例绘示在进行画面更新(期间F_act)中第四期间P4(即重置发光元件OLED阳极端的阶段)内图2的像素电路100中各晶体管的状态示意图。如图4A所示,在期间P2结束时,第二控制信号S2[n]转为关断电压电平。而在期间P4中,续传级的第一控制信号S1[n+1]转为导通电压电平(如图4A所示的低电平)。由于其他信号维持不变,在此不再赘述。
如图7所示,晶体管T1、T2、T3、T4、T5和T6关断,晶体管T7根据低电平的第一控制信号S1[n+1]导通,使得发光元件OLED的阳极端被重置至重置电压电平(即低电平)。如此一来,藉由续传级的第一控制信号S1[n+1],便能在发光阶段前确保发光元件OLED没有残存的电荷。
接着,请一并参考图4A和图8。图8是根据本发明的部分实施例绘示在进行画面更新(期间F_act)中第三期间P3(即发光阶段)内图2的像素电路100中各晶体管的状态示意图。如图4A所示,在期间P3中,发光控制信号EM[n]转为导通电压电平(如图4A所示的低电平),其他信号维持不变,在此不再赘述。如图8所示,晶体管T1、T2、T3、T4和T7关断,晶体管T5和T6根据低电平的发光控制信号EM[n]导通,以提供系统高电压OVDD至驱动晶体管Td的第一端(即,节点N1),使得驱动晶体管Td输出驱动电流Id如下式(1)所示:
其中Vth为驱动晶体管Td的临界电压。k为导电参数(Conduction Parameter)。如此一来,藉由期间P2所产生的补偿电压进行补偿,便能使像素电路100进行显示时,驱动电流Id的电流大小将不受驱动晶体管Td的元件特性(如临界电压不同)而影响,可提供相对稳定的驱动电流Id。
请回头参考图3。在期间F_skp,相似于期间F_act,时脉信号CK1、CK2、CK3、EMA、EMB切换于低电平和高电平之间,起始信号VST、控制信号S1[n]、S1[n+1]依序由高电平转为低电平,起始信号EMST、发光控制信号EM[n]、EM[n+1]依序由关断电压电平转为导通电压电平。然而,在期间F_skp,时脉信号CKA、CKB、控制信号S2[n]、S2[n+1]一直维持在高电平。
换言之,在期间F_skp,栅极驱动器930用以根据时脉信号CK1、CK2、CK3和起始信号VST产生控制信号S1[n]、S1[n+1],栅极驱动器940用以根据时脉信号EMA、EMB和起始信号EMST产生发光控制信号EM[n]、EM[n+1],使得像素电路100根据控制信号S1[n+1]进行发光元件OLED的阳极端的重置并进行发光,但不写入数据信号Vdata。此外,在期间F_skp,虽然仍会持续地提供参考电压Vref,但由于在此期间控制信号S2[n]不会作动,因此节点N1的电压不会被重置。
关于期间F_skp中维持前一帧画面的信号的进一步详细说明,请参考图4B。图4B是根据本发明的其他部分实施例绘示一种像素电路100在期间F_skp中的信号时序放大示意图。如图4B所示,在部分实施例中,期间F_skp包含期间P5和期间P6。具体而言,期间P5为重置发光元件OLED的阳极端的阶段。期间P6为发光阶段。
如图4B所示,在期间P5中,相似于期间F_act中的期间P4,续传级的第一控制信号S1[n+1]转为导通电压电平,其他信号皆为关断电压电平。因此,晶体管T1、T2、T3、T4、T5和T6关断,晶体管T7根据低电平的第一控制信号S1[n+1]导通,使得发光元件OLED的阳极端被重置至重置电压电平(即低电平)。
在期间P6中,相似于期间F_act中的期间P3,发光控制信号EM[n]转为导通电压电平,其他信号皆为关断电压电平。因此,晶体管T1、T2、T3、T4和T7关断,晶体管T5和T6根据低电平的发光控制信号EM[n]导通,以提供系统高电压OVDD至驱动晶体管Td的第一端(即,节点N1),使得驱动晶体管Td输出驱动电流Id。
如此一来,即便在维持前一帧画面信号的期间F_skp中,由于起始信号VST和时脉信号CK1、CK2、CK3的持续作动,因此藉由续传级的第一控制信号S1[n+1],便能在发光阶段前重置发光元件OLED的阳极端,以确保发光元件OLED没有残存的电荷影响发光亮度。并且,藉由本案提出的像素电路100的设计,驱动晶体管Td的控制端(即,节点N1)的电压电平较不容易受到影响,在期间F_skp中仍可保持与在期间F_act的期间P3中相近的电压电平。因此,在期间F_skp中的期间P6和期间F_act中的期间P3的发光亮度能较为接近。此外,由于在期间F_skp中不提供进行重置的参考电压Vref,也不写入数据信号Vdata,可达到节省电力消耗。
值得注意的是,虽然在本案实施例中,晶体管T7是以接收续传级的第一控制信号S1[n+1]为例进行说明,然而本发明不以此为限,本领与具有通常知识者可依据实际需求进行调整设计。
请参考图9A和图9B。图9A是根据本发明的其他部分实施例绘示另一种像素电路100a的示意图。图9B是根据图9A的实施例绘示一种像素电路100a的信号时序示意图。如图9A所示,在部分实施例中,晶体管T7可用以接收当级的第一控制信号S1[n]。如图9B所示的第一控制信号S1[n]由高电平转为低电平时,像素电路100a的晶体管T1和T7一起导通。接着,第二控制信号S2[n]也由高电平转为低电平。如此一来,像素电路100a在将节点N1重置到参考电压Vref的同时,亦将发光元件OLED的阳极端重置到低电平。接着,再进行发光显示。
请参考图10A和图10B。图10A是根据本发明的其他部分实施例绘示另一种像素电路100b的示意图。图10B是根据图10A的实施例绘示一种像素电路100b的信号时序示意图。如图10A所示,在其他部分实施例中,晶体管T7可用以接收前一级的第一控制信号S1[n-1]。如图10B所示的第一控制信号S1[n-1]由高电平转为低电平时,像素电路100b的晶体管T7导通,因而将发光元件OLED的阳极端重置到低电平。接着,第一控制信号S1[n]和第二控制信号S2[n]依序由高电平转为低电平,像素电路100b的晶体管T1和T2导通,再将节点N1重置到参考电压Vref。最后,再进行发光显示。
请参考图11。图10A是根据本发明的其他部分实施例绘示另一种像素电路100c的示意图。如图11所示,在其他部份实施例中,晶体管T1的第一端用以接收参考电压Vref1。晶体管T7的第一端用以接收参考电压Vref2。晶体管T7的控制端用以接收第一控制信号S1[n+1]并根据第一控制信号S1[n+1]选择性地导通或关断。其中,参考电压Vref1、Vref2和上述的参考电压Vref可以是相同、不完全相同,或者完全不同的电压电平。此外,虽然在图11所绘示的实施例中,晶体管T7的控制端是以接收续传级的第一控制信号S1[n+1],然而本发明不以此为限。相似于图9A~图10B及其相关说明,在其他部分实施例中,晶体管T7的控制端可用以接收当级的第一控制信号S1[n],或者用以接收前一级的第一控制信号S1[n-1]。
虽然本文将所公开的方法示出和描述为一系列的步骤或事件,但是应当理解,所示出的这些步骤或事件的顺序不应解释为限制意义。例如,部分步骤可以以不同顺序发生和/或与除了本文所示和/或所描述的步骤或事件以外的其他步骤或事件同时发生。另外,实施本文所描述的一个或多个态样或实施例时,并非所有于此示出的步骤皆为必需。此外,本文中的一个或多个步骤亦可能在一个或多个分离的步骤和/或阶段中执行。
综上所述,本案通过应用上述各个实施例中,在维持前一帧画面信号的期间F_skp中,不写入新的数据信号Vdata至像素电路100,但仍对像素电路100进行重置并进行发光显示。藉由像素电路100的设计以及重置发光元件OLED的阳极端,使得发光元件OLED不会有残存的电荷影响发光亮度,且驱动晶体管Td的控制端的电压电平较能保持与在进行画面信号更新的期间F_act中相近的电压电平。如此一来,便能在降低画面更新率时,达到节省功耗并稳定发光亮度,避免产生闪烁的现象。
虽然本发明已以实施方式揭露如上,然其并非用以限定本发明,所属技术领域具有通常知识者在不脱离本发明的精神和范围内,当可作各种更动与润饰,因此本发明的保护范围当视后附的申请专利范围所界定者为准。
Claims (9)
1.一种像素电路,其特征在于,包含:
一第一晶体管,该第一晶体管的一第一端接收一第一参考电压;
一第二晶体管,该第二晶体管的一第一端耦接该第一晶体管的一第二端,该第二晶体管的一第二端耦接一第一节点;
一第三晶体管,该第三晶体管的一第一端耦接该第一晶体管的一第二端;
一第四晶体管,该第四晶体管的一第一端接收一数据信号,该第四晶体管的一第二端耦接一第二节点;
一第五晶体管,该第五晶体管的一第一端接收一系统高电压,该第五晶体管的一第二端耦接该第二节点;
一驱动晶体管,该驱动晶体管的一控制端耦接该第一节点,该驱动晶体管的一第一端耦接该第二节点,该驱动晶体管的一第二端耦接该第三晶体管的该第二端;
一第六晶体管,该第六晶体管的一第一端耦接该驱动晶体管的该第二端,该第六晶体管的一第二端耦接一发光元件;
一电容,该电容耦接于该第一节点和该第五晶体管的该第一端之间;以及
一第七晶体管,该第七晶体管的一第一端和该第七晶体管的一控制端相互耦接,该第七晶体管的一第二端耦接该发光元件的一阳极端;
该第一晶体管用以根据一第一控制信号选择性地导通,该第二晶体管、该第三晶体管和该第四晶体管用以根据一第二控制信号选择性地导通,该第七晶体管用以根据一第三控制信号选择性地导通,该第五晶体管和该第六晶体管用以根据一发光控制信号选择性地导通。
2.如权利要求1所述的像素电路,其特征在于,
在一第一帧的一第一期间,该第一控制信号和该第二控制信号切换至一导通电压电平,使得该第一晶体管、该第二晶体管、该第三晶体管和该第四晶体管导通,以提供该第一参考电压至该第一节点,并提供该数据信号至该第二节点,
在该第一帧的一第二期间,该第一控制信号切换至一关断电压电平,该第二控制信号维持于该导通电压电平,使得该第二晶体管、该第三晶体管和该第四晶体管导通,以提供一补偿电压至该第一节点,
在该第一帧的一第三期间,该发光控制信号切换至该导通电压电平,使得该第五晶体管和第六晶体管导通,以输出一驱动电流至该发光元件。
3.如权利要求1所述的像素电路,其特征在于,
在一第二帧中,该第二控制信号维持于一关断电压电平,
在该第二帧的一第一期间,该第三控制信号切换至一导通电压电平使得该第七晶体管导通,
在该第二帧的一第二期间,该发光控制信号切换至该导通电压电平使得该发光元件接收一驱动电流进行发光。
4.一种像素电路,其特征在于,包含:
一第一晶体管,该第一晶体管的一第一端接收一第一参考电压;
一第二晶体管,该第二晶体管的一第一端耦接该第一晶体管的一第二端,该第二晶体管的一第二端耦接一第一节点;
一第三晶体管,该第三晶体管的一第一端耦接该第一晶体管的一第二端;
一第四晶体管,该第四晶体管的一第一端接收一数据信号,该第四晶体管的一第二端耦接一第二节点;
一第五晶体管,该第五晶体管的一第一端接收一系统高电压,该第五晶体管的一第二端耦接该第二节点;
一驱动晶体管,该驱动晶体管的一控制端耦接该第一节点,该驱动晶体管的一第一端耦接该第二节点,该驱动晶体管的一第二端耦接该第三晶体管的该第二端;
一第六晶体管,该第六晶体管的一第一端耦接该驱动晶体管的该第二端,该第六晶体管的一第二端耦接一发光元件;
一电容,该电容耦接于该第一节点和该第五晶体管的该第一端之间;以及
一第七晶体管,该第七晶体管的一第一端用以接收一第二参考电压,该第七晶体管的一控制端用以接收一第一控制信号或一第三控制信号,该第七晶体管的一第二端耦接该发光元件的一阳极端,该第二参考电压不同于该第一参考电压;
该第一晶体管用以根据该第一控制信号选择性地导通,该第二晶体管、该第三晶体管和该第四晶体管用以根据一第二控制信号选择性地导通,该第七晶体管用以根据该第一控制信号或该第三控制信号选择性地导通,该第五晶体管和该第六晶体管用以根据一发光控制信号选择性地导通。
5.一种像素电路驱动方法,其特征在于,包含:
在一第一帧中,一写入电路进行写入,一发光元件进行发光;
在一第二帧中,该写入电路维持关断;
在该第二帧的一第一期间,重置一发光元件的一阳极端至一重置电压电平;以及
在该第二帧的一第二期间,一发光控制电路导通使得一驱动晶体管根据一系统高电压输出一驱动电流至该发光元件。
6.如权利要求5所述的像素电路驱动方法,其特征在于,更包含:
在该第一帧的一第一期间,重置该驱动晶体管的一控制端至一第一参考电压,并由一写入电路提供一数据信号至该驱动晶体管的一第一端;
在该第一帧的一第二期间,由一补偿电路提供一补偿电压至该驱动晶体管的该控制端;以及
在该第一帧的一第三期间,该发光控制电路导通使得该驱动晶体管根据该系统高电压和该补偿电压输出该驱动电流至该发光元件。
7.如权利要求5所述的像素电路驱动方法,其特征在于,更包含:
在该第一帧的一第一期间,一第一晶体管根据一第一控制信号导通,一第二晶体管、一第三晶体管和一第四晶体管根据一第二控制信号导通,以重置该驱动晶体管的一控制端至一第一参考电压,并提供一数据信号至该驱动晶体管的一第一端;
在该第一帧的一第二期间,该第一晶体管根据该第一控制信号关断,该第二晶体管、该第三晶体管和该第四晶体管根据该第二控制信号导通,以提供一补偿电压至该驱动晶体管的该控制端;以及
在该第一帧的一第三期间,一第五晶体管和一第六晶体管根据一发光控制信号导通使得该驱动晶体管根据该系统高电压和该补偿电压输出该驱动电流至该发光元件。
8.如权利要求7所述的像素电路驱动方法,其特征在于,更包含:
在该第一帧的一第四期间,一第七晶体管根据一第三控制信号导通以重置该发光元件的该阳极端至该重置电压电平。
9.如权利要求8所述的像素电路驱动方法,其特征在于,更包含:
一栅极驱动器根据一第一组时脉信号以产生该第一控制信号和该第三控制信号,并根据一第二组时脉信号以产生该第二控制信号,
其中,在该第二帧,该第一组时脉信号切换于一高电平和一低电平之间,该第二组时脉信号维持于该高电平。
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CN110085161A (zh) * | 2018-04-18 | 2019-08-02 | 友达光电股份有限公司 | 显示面板和像素电路 |
CN109493789A (zh) * | 2018-06-07 | 2019-03-19 | 友达光电股份有限公司 | 像素电路 |
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US20210118367A1 (en) | 2021-04-22 |
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