WO2019201171A1 - 像素电路、显示面板和显示装置及其驱动方法 - Google Patents

像素电路、显示面板和显示装置及其驱动方法 Download PDF

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Publication number
WO2019201171A1
WO2019201171A1 PCT/CN2019/082465 CN2019082465W WO2019201171A1 WO 2019201171 A1 WO2019201171 A1 WO 2019201171A1 CN 2019082465 W CN2019082465 W CN 2019082465W WO 2019201171 A1 WO2019201171 A1 WO 2019201171A1
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Prior art keywords
sub
data
circuit
transistor
reset
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PCT/CN2019/082465
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English (en)
French (fr)
Inventor
杨盛际
董学
陈小川
王辉
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京东方科技集团股份有限公司
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Priority to US16/608,368 priority Critical patent/US11094260B2/en
Publication of WO2019201171A1 publication Critical patent/WO2019201171A1/zh

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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/066—Adjustment of display parameters for control of contrast
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G09G2360/144—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light being ambient light

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit, a display panel, a display device, and a method of driving the same.
  • Organic light emitting diode display panels have been widely used. Since the OLED display panel can actively emit light, there is no need to additionally set a backlight, so that the user's demand for the thinning of the display device can be satisfied.
  • At least some embodiments of the present disclosure provide a pixel circuit, a display panel, and a display device and a method of driving the same.
  • the pixel circuit can realize two working modes of high brightness and high contrast, and the structure is simple and easy to implement.
  • At least some embodiments of the present disclosure provide a pixel circuit including: a driving sub circuit, a first data writing sub circuit, a second data writing sub circuit, and a storage sub circuit, wherein the first data writing sub circuit and The first end of the storage subcircuit is electrically connected, and is configured to write a first data voltage to the first end of the storage subcircuit when the conduction under the control of the first data scan signal; the second data Writing a sub-circuit electrically coupled to the second end of the storage sub-circuit and configured to write a second data voltage to the second end of the storage sub-circuit when turned on under control of the second data scan signal, Controlling a voltage of the first end of the storage sub-circuit based on the second data voltage; a first end of the storage sub-circuit is further electrically coupled to a control end of the drive sub-circuit; the drive sub-circuit is configured The light emitting element is driven to emit light under the control of the voltage at the first end of the storage subcircuit.
  • the second data writing sub-circuit includes a first data writing transistor, and a gate of the first data writing transistor is configured to receive the second a data scan signal, the first pole of the first data write transistor is configured to receive the second data voltage, and the second pole of the first data write transistor is electrically coupled to the second end of the memory subcircuit connection.
  • the first data write transistor when the second data scan signal is at a first level, the first data write transistor is turned on, and the second data scan signal is at a second At the level, the first data write transistor is turned off, and the first level and the second level are levels opposite to each other.
  • the first data write transistor is a P-type transistor.
  • a control end of the first data writing sub-circuit is configured to receive the first data scan signal, and the first data is written to a control end of the sub-circuit
  • the first sub-control signal and the second sub-control end, the first data scan signal includes a first sub-data scan signal and a second sub-data scan signal
  • the first sub-control terminal is configured to receive the first a sub-data scan signal
  • the second sub-control terminal being configured to receive the second sub-data scan signal.
  • the first data writing sub-circuit includes an N-type data writing transistor and a P-type data writing transistor, and the first pole of the N-type data writing transistor And the first pole of the P-type data write transistor is configured to receive the first data voltage, the second pole of the N-type data write transistor and the second pole of the P-type data write transistor Each is electrically coupled to a first end of the memory subcircuit, the first sub-control terminal includes a gate of the N-type data write transistor, and the second sub-control terminal includes the P-type data write transistor The gate.
  • a pixel circuit provided by some embodiments of the present disclosure further includes a reset sub-circuit, a first output end of the reset sub-circuit is electrically connected to a second end of the storage sub-circuit, and a second output end of the reset sub-circuit Electrically connected to the anode of the light emitting element, the reset subcircuit is configured to reset the second end of the storage subcircuit under the control of the first reset control signal, under the control of the second reset control signal The anode of the light-emitting element is reset.
  • an input end of the reset sub-circuit is electrically connected to a first reference level signal end and a second reference level signal end
  • the reset sub-circuit is configured to be Writing a first reference level signal of the first reference level signal end to the second end of the storage sub-circuit to reset the second end of the storage sub-circuit under the control of the first reset control signal
  • the reset sub-circuit is further configured to write a second reference level signal of the second reference level signal terminal to an anode of the light emitting element under control of the second reset control signal to illuminate the light The anode of the component is reset.
  • the reset sub-circuit includes a first reset transistor and a second reset transistor
  • an input terminal of the reset sub-circuit includes a first pole of the first reset transistor and a first pole of the second reset transistor
  • the first output terminal includes a second pole of the first reset transistor
  • the second output terminal includes a second pole of the second reset transistor, a gate of a reset transistor configured to receive the first reset control signal, a first pole of the first reset transistor being configured to be electrically coupled to the first reference level signal terminal, the first reset transistor a second pole is electrically coupled to the second end of the storage subcircuit
  • a gate of the second reset transistor is configured to receive the second reset control signal
  • a first pole of the second reset transistor is configured
  • the second pole of the second reset transistor is electrically connected to the anode of the light emitting element.
  • a pixel circuit provided by some embodiments of the present disclosure further includes an illumination control sub-circuit configured to implement a connection between the driving sub-circuit and the light-emitting element under control of an illumination control signal Pass or disconnect.
  • the light emission control sub-circuit includes a light emission control transistor, and a gate of the light emission control transistor is configured to receive the light emission control signal, the light emission control transistor One pole is electrically connected to the first level signal terminal, and the second pole of the light emission control transistor is electrically connected to the driving subcircuit.
  • the driving sub-circuit includes a driving transistor, a first pole of the driving transistor is electrically connected to the lighting control sub-circuit, and a second pole of the driving transistor is An anode of the light emitting element is electrically connected, a control end of the driving subcircuit includes a gate of the driving transistor, a gate of the driving transistor and a first end of the storage subcircuit, and a cathode of the light emitting element It is electrically connected to the second level signal terminal.
  • the storage sub-circuit includes a storage capacitor, a first end of the storage sub-circuit includes a first end of the storage capacitor, and a second end of the storage sub-circuit The terminal includes a second end of the storage capacitor.
  • At least some embodiments of the present disclosure also provide a display panel comprising the pixel circuit of any of the above.
  • the display panel provided by some embodiments of the present disclosure further includes a plurality of pixel units arranged in a plurality of rows and columns, and the pixel circuits are disposed in each of the pixel units.
  • the plurality of rows of pixel units of the plurality of pixel units are respectively in one-to-one correspondence with the plurality of gate line groups, and the plurality of columns of the plurality of pixel units are respectively Column data line groups are in one-to-one correspondence;
  • each of the plurality of gate line groups includes a first gate line and a second gate line, the first gate line being configured to provide the first data scan signal,
  • the second gate line is configured to provide the second data scan signal, in a pixel unit of the same row, a first data write sub-circuit of each of the pixel units is electrically connected to the first gate line to receive the a first data scan signal, a second data write subcircuit of each of the pixel units being electrically coupled to the second gate line to receive the second data scan signal;
  • each of the plurality of data line groups A first data line configured to provide the first data voltage, the second data line configured to provide the second data voltage in a pixel unit of the same column The first number of
  • the first gate line includes a first a sub-gate line and a second sub-gate line
  • a first sub-control terminal of the first data writing sub-circuit of each of the pixel units is electrically connected to the first sub-gate line
  • each A second sub-control terminal of the first data writing sub-circuit of the pixel unit is electrically connected to the second sub-gate line.
  • At least some embodiments of the present disclosure also provide a display device comprising the display panel of any of the above.
  • some embodiments of the present disclosure provide a display device further including a photosensitive element for detecting brightness of an environment in which the display device is located, and generating a first when the brightness is higher than or equal to a preset brightness And triggering a signal to control the display device to be in a first working mode, and generating a second trigger signal to control the second operating mode of the display device when the brightness is lower than the preset brightness.
  • the display brightness of the display device in the first working mode is greater than the display brightness of the display device in the second working mode.
  • a display device provided by some embodiments of the present disclosure further includes a data driver configured to be electrically connected to a pixel circuit in the display panel through a first data line and a second data line, and through the A data line provides the first data voltage to the pixel circuit, and the second data voltage is provided to the pixel circuit through the second data line.
  • a data driver configured to be electrically connected to a pixel circuit in the display panel through a first data line and a second data line, and through the A data line provides the first data voltage to the pixel circuit, and the second data voltage is provided to the pixel circuit through the second data line.
  • some embodiments of the present disclosure provide a display device further including a gate driver configured to provide the first data scan signal and the second data scan signal to a pixel circuit in the display panel .
  • a duty cycle of the display panel includes a charging phase and a voltage a driving phase and a lighting phase
  • the driving method comprising: controlling, in the charging phase, the first data writing sub-circuit to write the first data voltage to a first end of the storage sub-circuit; In the voltage jump phase, controlling the second data write sub-circuit to write the second data voltage to the second end of the storage sub-circuit to control the voltage of the first end of the storage sub-circuit, wherein The voltage at the first end of the storage subcircuit is different from the voltage at the first end of the storage subcircuit in the voltage hopping phase during the charging phase; during the illuminating phase, the driving The sub-circuit drives the light-emitting element to emit light based on a voltage of the first end of the storage sub-circuit.
  • At least some embodiments of the present disclosure further provide a driving method of a display device according to any one of the preceding claims, wherein when the photosensitive element generates the second trigger signal, a duty cycle of the display panel includes a charging phase and a light emitting
  • the driving method includes: controlling, in the charging phase, the first data writing sub-circuit to write the first data voltage to a first end of the storage sub-circuit; in the lighting stage, The driver sub-circuit drives the light-emitting element to emit light based on a voltage of the first end of the storage sub-circuit.
  • FIG. 1A is a schematic diagram of a pixel circuit according to some embodiments of the present disclosure.
  • FIG. 1B is a schematic diagram of another pixel circuit according to some embodiments of the present disclosure.
  • FIG. 2A is a schematic diagram of a circuit structure of a pixel circuit according to some embodiments of the present disclosure
  • FIG. 2B is a schematic diagram of a circuit structure of another pixel circuit according to some embodiments of the present disclosure.
  • FIG. 3A is a timing signal diagram of a pixel circuit in operation according to some embodiments of the present disclosure.
  • FIG. 3B is another timing signal diagram of a pixel circuit in operation according to some embodiments of the present disclosure.
  • FIG. 3C is still another timing signal diagram of a pixel circuit in operation according to some embodiments of the present disclosure.
  • FIG. 4A is a diagram showing a relationship between voltages at both ends and luminance of a light-emitting element according to some embodiments of the present disclosure
  • 4B is a diagram showing a relationship between voltages at both ends and luminance of light emitted by another light-emitting element according to some embodiments of the present disclosure
  • FIG. 5 is a schematic diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 6 is a schematic diagram of a display device according to some embodiments of the present disclosure.
  • FIG. 7 is a schematic flowchart of a driving method of a display device according to some embodiments of the present disclosure.
  • FIG. 1A is a schematic diagram of a pixel circuit provided by some embodiments of the present disclosure
  • FIG. 1B is a schematic diagram of another pixel circuit according to some embodiments of the present disclosure
  • FIG. 2A is a pixel circuit provided by some embodiments of the present disclosure.
  • FIG. 2B is a schematic diagram of a circuit structure of another pixel circuit according to some embodiments of the present disclosure
  • FIG. 3A is a timing signal diagram of a pixel circuit according to some embodiments of the present disclosure
  • FIG. Another timing signal diagram of a pixel circuit in operation is provided by some embodiments of the present disclosure;
  • FIG. 3C is a timing signal diagram of a pixel circuit in operation according to some embodiments of the present disclosure.
  • FIG. 4A is a disclosure of the present disclosure;
  • FIG. 4B is a diagram showing a relationship between voltages at both ends of a light-emitting element and luminance of light emitted by some embodiments of the present disclosure.
  • FIG. 4A is a disclosure of the present disclosure.
  • FIG. 4B is a diagram showing a relationship between voltages at both ends of a light-emitting element and luminance of light emitted by some embodiments of the present disclosure.
  • pixel circuit 10 includes drive sub-circuit 100, first data write sub-circuit 110, second data write sub-circuit 120, and memory sub-circuit 140.
  • the pixel circuit 10 is for driving the light emitting element OLED to emit light.
  • the first data write sub-circuit 110 is electrically coupled to the first end of the storage sub-circuit 140. Under the control of the first data scan signal, when the first data write sub-circuit 110 is turned on, the first data write sub-circuit 110 is configured to write the first data voltage to the first end of the memory sub-circuit 140.
  • the second data write sub-circuit 120 is electrically coupled to the second end of the memory sub-circuit 140. That is, the first data writing sub-circuit 110 and the second data writing sub-circuit 120 are respectively connected to both ends of the storage sub-circuit 140. Under the control of the second data scan signal, when the second data write sub-circuit 120 is turned on, the second data write sub-circuit 120 is configured to write the second data voltage to the second end of the storage sub-circuit 140, The voltage at the first end of the storage sub-circuit 140 is controlled based on the second data voltage.
  • the first end of the storage sub-circuit 140 is also electrically connected to the control terminal of the driving sub-circuit 100; the driving sub-circuit 100 is driven to illuminate the light-emitting element OLED under the control of the voltage of the first end of the storage sub-circuit 140.
  • the pixel circuit provided by the embodiment of the present disclosure can realize two working modes of high brightness and low brightness, while ensuring high contrast, and the structure is simple and easy to implement.
  • an embodiment of the present disclosure provides a design of a Micro OLED driving scheme for implementing high voltage driving using a low voltage Wafer (wafer) Mos process, by adding a second data writing sub-circuit in a pixel circuit, using voltage hopping The mode, together with the value of each control signal, achieves two modes of operation.
  • the Micro OLED device Under the established low-voltage Mos process limitation (for example, 0.11um, 6V process), the Micro OLED device can satisfy high brightness within the specific pressure range of the wafer. At the same time, it is compatible with high contrast, so that high-voltage light-emitting elements can be driven under low-voltage TFT process technology to achieve high brightness while ensuring high contrast.
  • the pixel circuit 10 further includes a reset sub-circuit 130 and an illumination control sub-circuit 150.
  • the pixel circuit 10 includes a driving sub-circuit 100, a first data writing sub-circuit 110, The second data is written to the sub-circuit 120, the reset sub-circuit 130, the storage sub-circuit 140, and the illumination control sub-circuit 150.
  • the output of the first data write sub-circuit 110 is electrically coupled to the first end of the storage sub-circuit 140, and the input of the first data write sub-circuit 140 and the output of the first data write sub-circuit 140 can It is turned on under the control of the first data scan signal received by the control terminal of the first data writing sub-circuit 110.
  • the output of the second data write sub-circuit 120 is electrically coupled to the second end of the memory sub-circuit 140, and the input of the second data write sub-circuit 120 and the output of the second data write sub-circuit 120 can It is turned on under the control of the second data scan signal received by the control terminal of the second data writing sub-circuit 120.
  • the reset sub-circuit 130 is configured to reset the second end of the storage sub-circuit 140 under the control of the first reset control signal, and reset the anode of the light-emitting element OLED under the control of the second reset control signal.
  • the input terminal of the reset sub-circuit 130 is electrically connected to the first reference level signal terminal Vcom1 and the second reference level signal terminal Vcom2, and the first output terminal of the reset sub-circuit 130 is electrically connected to the second terminal of the storage sub-circuit 140.
  • the second output of the reset sub-circuit 130 is electrically connected to the anode of the light-emitting element OLED.
  • the input terminal of the reset sub-circuit 130 and the first output terminal of the reset sub-circuit 130 can be turned on under the control of the first reset control signal received by the control terminal of the reset sub-circuit 130, and the input terminal of the reset sub-circuit 130 and the reset The second output of the sub-circuit 130 can be turned on under the control of the second reset control signal received by the control terminal of the reset sub-circuit 130. That is, the reset sub-circuit 130 is configured to write the first reference level signal of the first reference level signal terminal Vcom1 to the second end of the storage sub-circuit 140 under the control of the first reset control signal to the storage sub-circuit 140.
  • the second end performs resetting
  • the reset sub-circuit 130 is further configured to write the second reference level signal of the second reference level signal terminal Vcom2 to the anode of the light emitting element OLED under the control of the second reset control signal to the light emitting element The anode of the OLED is reset.
  • the first end of the storage sub-circuit 140 is electrically connected to the control terminal of the driving sub-circuit 100, and the storage sub-circuit 140 is for storing the first data voltage written by the first data writing sub-circuit 110 and writing by the second data.
  • the second data voltage written into the sub-circuit 120 is electrically connected to the control terminal of the driving sub-circuit 100, and the storage sub-circuit 140 is for storing the first data voltage written by the first data writing sub-circuit 110 and writing by the second data.
  • the second data voltage written into the sub-circuit 120 is for example, the first end of the storage sub-circuit 140 is electrically connected to the control terminal of the driving sub-circuit 100, and the storage sub-circuit 140 is for storing the first data voltage written by the first data writing sub-circuit 110 and writing by the second data.
  • the second data voltage written into the sub-circuit 120 is for example, the first end of the storage sub-circuit 140 is electrically connected to the control terminal of the driving sub-circuit 100, and
  • the illumination control sub-circuit 150 is configured to effect conduction or disconnection of the connection between the drive sub-circuit 100 and the light-emitting element OLED under the control of the illumination control signal.
  • the lighting control signal includes a first sub-lighting control signal and a second sub-lighting control signal.
  • the cathode of the light-emitting element OLED is electrically connected to the second level signal terminal Vss, and the light-emitting control sub-circuit 150 is configured to allow the first level signal terminal Vdd when receiving the first sub-lighting control signal.
  • a first end of the driving sub-circuit 100, a second end of the driving sub-circuit 100, a light-emitting element OLED, and a second level signal terminal Vss form a path
  • the light-emitting control sub-circuit 150 is further configured to receive the second sub- When the light-emitting control signal is emitted, the first level signal terminal Vdd, the first end of the driving sub-circuit 100, the second end of the driving sub-circuit 100, the light-emitting diode OLED, and the second level signal terminal Vss are disconnected.
  • the light emitting element OLED may be a light emitting diode or the like.
  • the light emitting diode may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED) or the like.
  • the light emitting element OLED is configured to receive a light emitting signal (eg, may be a current signal) while in operation and emit light of a strength corresponding to the light emitting signal.
  • one of the first level signal terminal Vdd and the second level signal terminal Vss is a high level signal terminal, and the other is a low level signal terminal.
  • the first level signal terminal Vdd is a voltage source to output a constant positive voltage
  • the second level signal terminal Vss may be a voltage source to output a constant negative voltage, or Can be grounded, etc.
  • the signal output from the second level signal terminal Vss remains unchanged.
  • the first data writing sub-circuit 110 and the second data writing sub-circuit 120 are included in two data writing sub-circuits.
  • the pixel circuit 10 can be applied to a display panel, such as an AMOLED display panel or the like, and the final display brightness and picture contrast of the display panel are related to the voltage difference V EL between the anode and the cathode of the light emitting element OLED.
  • the light emitting element OLED has two working modes, and when the voltage difference V EL between the anode and the cathode of the light emitting element OLED is within the first interval, the high brightness mode one (ie, the first working mode) can be realized, when the light emitting element When the pressure difference between the anode and the cathode of the OLED is within the second interval, mode 2 of high contrast (ie, the second mode of operation) can be achieved.
  • Fig. 4A is an operation mode of a specific light-emitting element, as shown in Fig. 4B, which is another mode of operation of the light-emitting element.
  • a high contrast mode 2 can be achieved; when the anode of the light-emitting diode
  • the mode 1 of high luminance can be realized, that is, the first interval is 4.3V to 5.4V, and the second interval is 5.1V to 6.1V.
  • the present disclosure is not limited thereto, and for example, in other examples, shown in Figure 4B, when the pressure V EL between the anode and the cathode of the light emitting element is between 4.5V to 7.0V, a high contrast can be realized Mode 2; when the voltage difference V EL between the anode and the cathode of the light-emitting element is between 6.2V and 8.5V, a mode 1 of high brightness can be realized, that is, the first interval is 4.5V to 7.0V, and the second The interval is 6.2V to 8.5V.
  • the second data scanning signal is provided to the control end of the second data writing sub-circuit 120, and Providing a second data voltage to the input end of the second data writing sub-circuit 120 to boost the first end of the storage sub-circuit 140, thereby increasing the voltage difference across the OLED of the OLED to ensure high brightness and high contrast The display effect.
  • the input of the second data voltage to the storage sub-circuit 140 through the second data writing sub-circuit 120 is stopped.
  • the first data voltage is supplied to the storage sub-circuit 140 through the second data writing sub-circuit 120 to ensure that the voltage difference across the light-emitting element OLED is small, achieving a low-brightness, high-contrast display effect.
  • the pixel circuit 10 when the two different operating modes are implemented by the pixel circuit 10 provided by the present disclosure, it is not necessary to provide two low-level signal terminals, and it is not necessary to provide a complicated voltage switching circuit, and the pixel circuit 10 is easy to implement.
  • the transistor used in the embodiment of the present disclosure may also be a thin film transistor or a field effect transistor or other switching device having the same characteristics, and the thin film transistor may include an oxide semiconductor thin film transistor, an amorphous silicon thin film transistor or a polysilicon thin film transistor. Wait.
  • the source and drain of the transistor can be symmetrical in structure, so the source and drain of the transistor can be physically indistinguishable.
  • the transistors except for the gate as the gate, one of the first poles and the other pole are directly described. Therefore, in the embodiment of the present disclosure, all or part of the transistors are The poles and the second pole are interchangeable as needed.
  • the driving transistor used in the pixel circuit 10 provided by the present disclosure is a silicon-based transistor.
  • the problem of threshold voltage drift is less likely to occur, and thus, the present disclosure provides It is also not necessary to provide a threshold compensation sub-circuit in the pixel circuit 10.
  • the present disclosure is not limited thereto, and the threshold compensation sub-circuit may be provided in the pixel circuit 10 provided by the present disclosure.
  • the transistor can be divided into an N-type transistor and a P-type transistor.
  • the embodiments of the present disclosure use the transistors P1-P3 and the driving transistor DTFT as P-type transistors (for example, P-type MOS transistors).
  • P-type transistors for example, P-type MOS transistors.
  • the transistor of the embodiment of the present disclosure is not limited to the above case, and the transistors of the embodiments of the present disclosure are not limited to the above, and the person skilled in the art may also It is necessary to set the type of transistor in the present disclosure.
  • the reset sub-circuit 130 is used to reset the storage sub-circuit 140 and the anode of the light-emitting element OLED for preventing the light-emitting element OLED from emitting light before the light-emitting phase.
  • FIG. 2A is a schematic diagram showing a circuit configuration of the pixel circuit shown in FIG. 1B, and the pixel circuit of the present disclosure will be described in detail below with reference to FIG. 2A.
  • the driving sub-circuit 100 includes a driving transistor DTFT.
  • the first electrode of the driving transistor DTFT is electrically connected to the light-emitting control sub-circuit 150, and the second electrode of the driving transistor DTFT is electrically connected to the anode of the light-emitting element OLED, and is driven.
  • the control terminal of the sub-circuit 100 includes a gate of a driving transistor DTFT, and a gate of the driving transistor DTFT is electrically connected to a first end of the memory sub-circuit 140.
  • the cathode of the light emitting element OLED is electrically connected to the second level signal terminal Vss.
  • control terminal of the first data write sub-circuit 110 is configured to electrically connect the first gate line to receive the first data scan signal.
  • control end of the first data writing sub-circuit 110 includes a first sub-control terminal and a second sub-control terminal, and the first data scan signal includes a first sub-data scan signal and a second sub-data scan signal.
  • the first sub-control terminal is configured to receive the first sub-data scan signal, and the second sub-control terminal is configured to receive the second sub-data scan signal.
  • the first sub-control terminal is an N-type control terminal and the second sub-control terminal is a P-type control terminal.
  • the first sub-data scan signal is an N-type data scan signal
  • the second sub-data scan signal is a P-type data scan signal.
  • the first data writing sub-circuit 110 includes an N-type data writing transistor N1 and a P-type data writing transistor P1.
  • the input end of the first data writing sub-circuit 140 includes a first pole of the N-type data writing transistor N1 and a first pole of the P-type data writing transistor P1, and an output terminal of the first data writing sub-circuit 110 includes an N-type
  • the second electrode of the data writing transistor N1 and the second electrode of the P-type data writing transistor P1 the control terminal of the first data writing sub-circuit 110 includes the gate of the N-type data writing transistor N1 and P-type data writing.
  • the first pole of the N-type data write transistor N1 and the first pole of the P-type data write transistor P1 are both configured to receive the first data voltage, for example, the first pole and the P of the N-type data write transistor N1.
  • the first pole of the type data write transistor P1 is electrically connected to the first data signal line D1 to receive the first data voltage.
  • the second pole of the N-type data write transistor N1 and the second pole of the P-type data write transistor P1 are both electrically coupled to the first terminal of the memory sub-circuit 140.
  • the first sub-control terminal includes a gate of the N-type data write transistor N1
  • the second sub-control terminal includes a gate of the P-type data write transistor P1, that is, the gate of the N-type data write transistor N1 is configured To receive the first sub-data scan signal, the gate of the P-type data write transistor P1 is configured to receive the second sub-data scan signal.
  • the first gate line includes a first sub-gate line G1 and a second sub-gate line G2, the first sub-gate line G1 is configured to output a first sub-data scan signal, and the second sub-gate line G2 is configured to output a second Sub data scan signal.
  • the gate of the N-type data write transistor N1 is electrically connected to the first sub-gate line G1 to receive the first sub-data scan signal
  • the gate of the P-type data write transistor P1 is electrically connected to the The second gate line G2 receives the second sub-data scan signal.
  • the first data writing sub-circuit 110 employs two different types of transistors, which can increase the voltage range of the write data voltage, the N-type data writing transistor N1 corresponds to the first high-level data voltage, and the P-type data is written.
  • the transistor P1 corresponds to a first data voltage of a low level.
  • the second data write sub-circuit 120 includes a first data write transistor P3.
  • the input end of the second data write sub-circuit 120 includes a first pole of the first data write transistor P3, and the output end of the second data write sub-circuit 120 includes a second pole of the first data write transistor P3, a second
  • the control terminal of the data write sub-circuit 120 includes the gate of the first data write transistor P3.
  • the first data write transistor P3 may be, for example, a P-type transistor, but the disclosure is not limited thereto, and the first data write transistor P3 may also be an N-type transistor.
  • the gate of the first data write transistor P3 is configured to be electrically connected to the second gate line G3 to receive the second data scan signal, and the first pole of the first data write transistor P3 is configured to be electrically connected to the second
  • the data line D2 receives the second data voltage, and the second pole of the first data write transistor P3 is electrically coupled to the second end of the memory sub-circuit 140.
  • the first data write transistor P3 when the second data scan signal is at the first level, the first data write transistor P3 is turned on, and when the second data scan signal is at the second level, the first data write transistor P3 is turned off, the first level is The second level is a level opposite to each other.
  • the first data write transistor P3 when the first data write transistor P3 is a P-type transistor, the first level is a low level and the second level is a high level; when the first data write transistor P3 is an N-type transistor, the first The level is high and the second level is low.
  • the memory sub-circuit 140 includes a storage capacitor C.
  • the first end of the storage sub-circuit 140 includes a first end of the storage capacitor C
  • the second end of the storage sub-circuit 140 includes a second end of the storage capacitor C. That is, the first end of the storage capacitor C is electrically connected to the N-type
  • the data is written to the second electrode of the transistor N1 and the second electrode of the P-type data write transistor P1, and the second terminal of the storage capacitor C is electrically connected to the second electrode of the first data write transistor P3.
  • the voltage of the first end of the storage capacitor C changes correspondingly due to the bootstrap effect of the storage capacitor C, and changes.
  • the amount can be a second data voltage to achieve a pull-up or pull-down of the voltage at the first end of the storage capacitor C.
  • the second data voltage is a positive voltage
  • the voltage of the first terminal of the storage capacitor C is pulled high
  • the second data voltage is a negative voltage
  • the voltage of the first terminal of the storage capacitor C is pulled low.
  • the voltage of the second end of the storage capacitor C may be 0V.
  • the reset sub-circuit 130 includes a first reset transistor N2 and a second reset transistor N3.
  • the input terminal of the reset sub-circuit 130 includes a first pole of the first reset transistor N2 and a first pole of the second reset transistor N3, and the first output terminal of the reset sub-circuit 130 includes a second pole of the first reset transistor N2, the resetter
  • the second output of circuit 130 includes a second pole of a second reset transistor N3.
  • the gate of the first reset transistor N2 is configured to be connected to the first reset control signal line RS1 to receive the first reset control signal
  • the first pole of the first reset transistor N2 is configured to be
  • a reference level signal terminal Vcom1 is electrically connected to receive the first reference level signal
  • the second pole of the first reset transistor N2 is electrically connected to the second end of the storage sub-circuit 140, that is, the second pole of the first reset transistor N2
  • the second end of the storage capacitor C is electrically connected.
  • the gate of the second reset transistor N3 is configured to be connected to the second reset control signal line RS2 to receive the second reset control signal, and the first pole of the second reset transistor N3 is configured to be
  • the second reference level signal terminal Vcom2 is electrically connected to receive the second reference level signal
  • the second electrode of the second reset transistor N3 is electrically connected to the anode of the light emitting element OLED.
  • the first reset control signal and the second reset control signal may be different signals, but in other embodiments, as shown in FIG. 2B, the first reset control signal And the second reset control signal is the same signal, so that the first reset control signal line RS1 or the second reset control signal line RS2 may not be set. That is, when only the first reset control signal line RS1 is set, the gate of the first reset transistor N2 and the gate of the second reset transistor N3 may be electrically connected to the first reset control signal line RS1; When the control signal line RS2 is reset, the gate of the first reset transistor N2 and the gate of the second reset transistor N3 are electrically connected to the second reset control signal line RS2.
  • first reference level signal and the second reference level signal may be different, but embodiments of the present disclosure are not limited thereto, as shown in FIG. 2B, in other embodiments, first The reference level signal and the second reference level signal may be the same.
  • first reference level signal and the second reference level signal are the same, only the first reference level signal terminal Vcom1 or the second reference level signal terminal Vcom2 may be set.
  • the first pole of the first reset transistor N2 and the first pole of the second reset transistor N3 may be electrically connected to the first reference level signal terminal Vcom1;
  • the first pole of the first reset transistor N2 and the first pole of the second reset transistor N3 may be electrically connected to the second reference level signal terminal Vcom2.
  • the first reference level signal and the second reference level signal may both be set to 0V.
  • the illumination control sub-circuit 150 includes an illumination control transistor P2.
  • the gate of the light emission control transistor P2 is configured to receive the light emission control signal
  • the first pole of the light emission control transistor P2 is electrically connected to the first level signal terminal Vdd
  • the second pole of the light emission control transistor P2 is electrically connected to the driving sub circuit 100
  • the gate of the light emission control transistor P2 is connected to the light emission control signal line EM to receive the light emission control signal
  • the second electrode of the light emission control transistor P2 is electrically connected to the first electrode of the drive transistor DTFT.
  • one duty cycle of the pixel circuit includes a reset phase T1, a charging phase T2, a hopping phase T3, and an illuminating phase T4.
  • the first reset control signal and the second reset control signal are the same signal, and the first reference level signal and the second reference level signal are both set to 0V as an example.
  • the driving transistor DTFT is an N-type transistor, and in the example shown in FIG. 3C, the driving transistor DTFT is a P-type transistor.
  • the operation principle of the pixel circuit is as follows.
  • a first reset control signal is provided to the first control terminal of the reset sub-circuit 130 through the first reset control signal line RS1 to input the input terminal of the reset sub-circuit 130 and the first output terminal of the reset sub-circuit 130.
  • the first reference level signal provided by the first reference level signal terminal Vcom1 is written to the second end of the storage sub-circuit 140, thereby resetting the second end of the storage sub-circuit 140 to facilitate the subsequent stage. The writing of the second data voltage.
  • a second reset control signal is provided to the second control terminal of the reset sub-circuit 130 through the second reset control signal line RS2, and the input terminal of the reset sub-circuit 130 and the second of the reset sub-circuit 130
  • the output terminal is turned on, so that the second reference level signal provided by the second reference level signal terminal Vcom2 can be written into the anode of the light emitting element OLED to realize resetting of the anode of the light emitting element OLED.
  • the first sub-data scan signal and the second sub-data scan signal are provided to the control end of the first data writing sub-circuit 110 through the first sub-gate line G1 and the second sub-gate line G2, and the first data is passed through the first data.
  • the line D1 supplies a first data voltage to the input end of the first data writing sub-circuit 110 to turn on the input end of the first data writing sub-circuit 110 and the output end of the first data writing sub-circuit 110, thereby The first data voltage is written into the first end of the storage sub-circuit 140, and the gate voltage of the driving transistor DTFT is brought to the first voltage V1.
  • the first sub-data scan signal provided by the first sub-gate line G1 is at a high level
  • the second sub-data scan signal provided by the second sub-gate line G2 is at a high level.
  • the low level is such that the N-type data write transistor and the P-type data write transistor in the first data write sub-circuit 110 are both turned on.
  • embodiments of the present disclosure are not limited thereto, and in some examples, in the charging phase T2, one of the N-type data writing transistor and the P-type data writing transistor is turned on, and the other is turned off.
  • the N-type data write transistor when the first data voltage is a positive voltage, the N-type data write transistor can be turned on, and the P-type data write transistor can be turned off; when the first data voltage is a negative voltage, the N-type data write transistor can be turned off.
  • the P-type data write transistor can be turned on.
  • the second data scan signal is supplied to the control terminal of the second data write sub-circuit 120 through the second gate line G3, so that the input end and the output end of the second data write sub-circuit 120 are turned on.
  • the second data voltage written by the input of the second data write sub-circuit 120 is thus stored into the second end of the memory sub-circuit 140.
  • the voltage jump phase T3 due to the bootstrap effect of the storage capacitor C, when the voltage of the second end of the storage sub-circuit 140 (ie, the second end of the storage capacitor C) is from the first reference level signal in the charging phase T2, That is, 0V, when jumping to the second data voltage of the voltage jump phase T3, the first terminal of the storage sub-circuit 140, that is, the gate voltage of the driving transistor DTFT (jumps from the first voltage V1 in the charging phase T2 to the voltage) The second voltage V2 of the transition phase T3.
  • the voltage threshold of the transistor is a fixed threshold (ie, the voltage difference between any two of the three electrodes of the transistor does not exceed the above fixed threshold, for example, 6V), therefore, The control signals of the remaining transistors should also jump with each other to ensure the normal operation of each transistor. Specifically, the level of the first sub-data scan signal is supplied to the control terminal of the first data writing sub-circuit through the first sub-gate line G1.
  • the second sub-gate line G2 is supplied to the control terminal of the first data writing sub-circuit to provide a higher level of the second sub-data scanning signal than in the charging The first in stage T2 Sub-data level scan signal, thereby to ensure that the range of writing a first data sub-circuit transistor operates in the allowable voltage threshold.
  • the level of the first sub-data scan signal is the first data level
  • the level of the second sub-data scan signal is the second data level
  • first The levels of the reset control signal and the second reset control signal are the first reset level
  • the level of the first sub-data scan signal is the third data level
  • the level of the second sub-data scan signal is a fourth data level
  • a level of the first reset control signal and the second reset control signal is a second reset level
  • a level of the first sub-data scan signal is a fifth data level
  • the level of the second sub-data scan signal is a sixth data level
  • the levels of the first reset control signal and the second reset control signal are third reset levels.
  • the first data level is less than the third data level
  • the third data level is less than the fifth data level
  • the second data level is greater than the fourth data level
  • the sixth data level is greater than the second data level
  • the first The reset level is greater than the second reset level
  • the first reset level is equal to the third reset level. That is, in the voltage jump phase T3, the level of the first sub-data scan signal jumps, from the first data level to the fifth data level, and the level of the second sub-data scan signal jumps. Changing from the second data level to the sixth data level, the levels of the first reset control signal and the second reset control signal are changed from the second reset level to the third reset level.
  • the light-emission control signal is supplied to the light-emission control sub-circuit 150 through the light-emission control signal line EM, so that the first-level signal terminal Vdd can be driven.
  • the first electrode of the transistor DTFT, the second electrode of the driving transistor DTFT, the light emitting diode OLED, and the second level signal terminal Vss form a via to drive the light emitting element OLED to emit light.
  • the levels of the illumination control signals are all the first illumination control levels; in the voltage transition phase T3, the illumination control signals are The level is the second lighting control level; in the lighting phase T4, the level of the lighting control signal is the third lighting control level.
  • the first illumination control level is lower than the second illumination control level, and the first illumination control level is equal to the third illumination control level, that is, in the voltage transition phase T3, the level of the illumination control signal is changed, from The first lighting control level jumps to the second lighting control level; in the lighting phase T4, the level of the lighting control signal also changes from the second lighting control level to the third lighting control level.
  • the level of the first sub-data scan signal is the seventh data level, the seventh data level is less than the fifth data level, and the seventh data is The level can be equal to the third data level, that is, the level of the first sub-data scan signal jumps, from the fifth data level to the third data level; the level of the second sub-data scan signal Maintaining the sixth data level, the levels of the first reset control signal and the second reset control signal are also maintained at the third reset level, that is, the level of the first reset control signal and the electrical average of the second sub-data scan signal are not maintained. A jump occurs.
  • the level of the first sub-data scan signal remains at the fifth data level; the level of the second sub-data scan signal remains at the sixth level.
  • the data level, the levels of the first reset control signal and the second reset control signal are also maintained at the third reset level, that is, the levels of the first reset control signal and the second reset control signal, and the first sub-data scan signal The level and the electrical average of the second sub-data scan signal do not jump.
  • the operation principle of the pixel circuit is similar to that when the driving transistor DTFT is a P-type transistor, except that the levels of the respective control signals are different.
  • the level of the first sub-data scan signal is the first data level
  • the level of the second sub-data scan signal is the second data level
  • the first reset control signal and the second reset control signal The level of the first reset level, the level of the illumination control signal is the first illumination control level
  • the level of the first sub-data scan signal is the third data level
  • the second sub-data scan The level of the signal is the fourth data level, the level of the first reset control signal and the second reset control signal is the second reset level, and the level of the illumination control signal is the first illumination control level
  • the level of the first sub-data scan signal is the fifth data level
  • the level of the second sub-data scan signal is the sixth data level
  • the levels of the first reset control signal and the second reset control signal are a third reset level
  • the level of the illumination control signal is a second illumination control level
  • the level of the first sub-data scan signal is a fifth data level
  • the level of the second sub-data scan signal is a fifth data level
  • the first data level is less than the third data level
  • the fifth data level is less than the first data level
  • the second data level is greater than the fourth data level
  • the fourth data level is greater than the sixth data level
  • the first reset level is greater than the second reset level
  • the second reset level is greater than the third reset level
  • the first illumination control level is greater than the second illumination control level
  • the second illumination control level is greater than the third illumination control level level. That is, in the voltage jump phase T3, the level of the first sub-data scan signal jumps, from the first data level to the fifth data level, and the level of the second sub-data scan signal jumps.
  • the levels of the first reset control signal and the second reset control signal are hopped, jumping from the second reset level to the third reset level,
  • the level of the illumination control signal jumps from the first illumination control level to the second illumination control level.
  • the third lighting control level is less than the second lighting control level to ensure that the lighting control transistor P2 is turned on during the lighting phase T4.
  • the second data scan signal is at the second level; in the voltage transition phase T3, the second data scan signal is at the first level.
  • the second level is high and the first level is low.
  • the voltage between the anode and the cathode of the light-emitting element OLED can be calculated from the relationship between the gate voltage of the silicon-based driving transistor DTFT, the threshold voltage of the driving transistor DTFT, and the voltage difference VEL between the anode and the cathode of the light-emitting element OLED. Poor V EL .
  • the gate voltage of the driving transistor DTFT when the gate voltage of the driving transistor DTFT is between 1V and 5V, the threshold voltage of the driving transistor DTFT is 1V, and the voltage supplied by the second level signal terminal Vss is -3V, the voltage of the cathode of the light emitting element OLED is -3V, the source voltage of the driving transistor DTFT is between 0V and 4V, that is, the voltage of the anode of the light emitting element OLED is between 0V and 4V, so that the voltage difference V EL between the anode and the cathode of the light emitting element OLED is 3V to 7V, as can be seen from FIG. 4B, the light-emitting element OLED operates in a mode 2 in which low brightness and high contrast can be achieved.
  • the second data scan signal is provided to the control terminal of the second data writing sub-circuit 120 in the voltage jump phase T3, and the second data is written to the sub-circuit 120.
  • the input provides a second data voltage, which may be higher than the first data voltage.
  • the gate voltage of the driving transistor DTFT may be between 5V and 9V, so that the source voltage of the driving transistor DTFT is between 4V and 8V, that is, the voltage of the anode of the light emitting element OLED is between 4V and 8V, thereby obtaining
  • the voltage difference V EL between the anode and the cathode of the light-emitting element OLED is 7V to 11V, and the light-emitting element OLED operates in a mode 1 in which high brightness and high contrast can be realized.
  • the specific structure of the first data writing sub-circuit 110 is not particularly limited.
  • the control end of the first data writing sub-circuit 110 includes an N-type control terminal (ie, a sub-control terminal) and a P-type control terminal (ie, the second sub-control terminal), respectively, wherein the first data scan signal comprises a first N-type data scan signal and a first P-type data scan signal.
  • the first N-type data scanning signal is supplied to the N-type control terminal of the first data writing sub-circuit 110, and the first P-type data scanning is provided to the P-type control terminal of the first data writing sub-circuit 110. signal.
  • the first data writing sub-circuit 110 includes an N-type data writing transistor N1 and a P-type data writing transistor P1, and a first electrode of the N-type data writing transistor N1 and a P-type transistor P1.
  • the first pole is electrically connected to form an input end of the first data writing sub-circuit 110
  • the second pole of the N-type data writing transistor N1 is electrically connected to the second pole of the P-type data writing transistor P1 to form
  • the first data is written to the output of sub-circuit 110.
  • a gate of the N-type data write transistor N1 is formed as the N-type control terminal
  • a gate of the P-type data write transistor P1 is formed as the P-type control terminal. It can be seen that the N-type data write transistor N1 and the P-type data write transistor P1 form a transfer gate.
  • the first pole of the N-type data write transistor N1 and the second pole of the N-type data write transistor N1 can be turned on when the gate of the N-type data write transistor N1 receives the first N-type data scan signal, N
  • the first electrode of the type data write transistor N1 and the second electrode of the N-type data write transistor N1 can be turned off when the gate of the N-type data write transistor N1 receives the third N-type data scan signal.
  • the first sub-data scan signal includes a first N-type data scan signal and a third N-type data scan signal, and the first N-type data scan signal is a high level signal, and the third N-type data scan signal is a low level signal.
  • the first pole of the P-type data write transistor P1 and the second pole of the P-type data write transistor P1 can be turned on when the gate of the P-type data write transistor P1 receives the first P-type data scan signal, P
  • the first electrode of the type data write transistor P1 and the second electrode of the P-type data write transistor P1 can be turned off when the gate of the P-type data write transistor P1 receives the third P-type data scan signal.
  • the second sub-data scan signal includes a first P-type data scan signal and a third P-type data scan signal, and the first P-type data scan signal is a low-level signal, and the third P-type data scan signal is a high-level signal.
  • the first data writing sub-circuit 110 is formed in the form of a transmission gate including a P-type data writing transistor and an N-type data writing transistor, and can increase a range of data voltages allowed by the first data writing sub-circuit 110, specifically Ground, the N-type data write transistor N1 can allow a data voltage with a higher input voltage value, and the P-type data write transistor P1 can allow a data voltage with a lower input voltage value.
  • the specific structure of the reset sub-circuit 130 is not particularly limited.
  • the reset sub-circuit 130 includes a first reset transistor N2 and a second reset transistor N3, and A reset transistor N2 is an N-type transistor. Both the gate of the first reset transistor N2 and the gate of the second reset transistor N3 receive the first reset control signal, that is, the first reset transistor N2 and the second reset transistor N3 are controlled by the same first reset control signal.
  • the gate of the first reset transistor N2 is formed as a control terminal of the reset sub-circuit 130, and the first electrode of the first reset transistor N2 is formed as an input terminal of the reset sub-circuit 130, and the first reset transistor N2 is The second pole is formed as a first output terminal of the reset sub-circuit 130, and the first pole of the first reset transistor N2 and the second pole of the first reset transistor N2 are capable of receiving the first sub-reset control at the gate of the first reset transistor N2 When the signal is turned on, the first pole of the first reset transistor N2 and the second pole of the first reset transistor N2 can be turned off when receiving the second sub-reset control signal, and the first reset control signal includes the first sub-reset control And a second sub-reset control signal, and the first sub-reset control signal and the second sub-reset control signal are in opposite phases.
  • the first pole of the first reset transistor N2 is electrically coupled to the first reference level signal terminal Vcom1. Therefore, the reset of the second terminal of the
  • the gate of the second reset transistor N3 is electrically connected to the gate of the first reset transistor N2, the first pole of the second reset transistor N3 is electrically connected to the first pole of the first reset transistor N2, and the second of the second reset transistor N3
  • the pole is formed as a second output terminal of the reset sub-circuit 130, and the first pole of the second reset transistor N3 and the second pole of the second reset transistor N3 are capable of receiving the first sub-reset control at the gate of the second reset transistor N3
  • the signal is turned on, and the first pole of the second reset transistor N3 and the second pole of the second reset transistor N3 can be turned off when the gate of the second reset transistor N3 receives the second sub-reset control signal.
  • the first pole of the second reset transistor N3 is electrically connected to the first reference level signal terminal Vcom1, and therefore, the anode of the light emitting element OLED can be reset by the second reset transistor N3.
  • the type of the second reset transistor N3 is not particularly limited.
  • the second reset transistor N3 is an N-type transistor.
  • the specific structure of the second data writing sub-circuit 120 is not particularly limited.
  • the second data writing sub-circuit 120 includes a first data writing transistor P3.
  • a gate of the first data write transistor P3 is formed as a control terminal of the second data write sub-circuit 120, and a first electrode of the first two data write transistor P3 is formed as an input end of the second data write sub-circuit 120, The second electrode of the first data write transistor P3 is formed as an output of the second data write sub-circuit 120.
  • the first pole of the first data write transistor P3 and the second pole of the first data write transistor P3 can be turned on when the gate of the first data write transistor P3 receives the third sub-data scan signal, and a first pole of a data write transistor P3 and a second pole of the first data write transistor P3 can be turned on when the gate of the first data write transistor P3 receives the fourth sub-data scan signal, for example,
  • the two data scan signals include a third sub-data scan signal and a fourth sub-data scan signal, and the third sub-data scan signal and the fourth sub-data scan signal are in opposite phases.
  • the third sub-data scan signal is a signal when the second data scan signal is at the first level
  • the fourth sub-data scan signal is a signal when the second data scan signal is at the second level
  • the first data write transistor P3 is a P-type transistor.
  • the third sub-data scan signal is a low level signal
  • the fourth sub-data scan signal is a high level signal.
  • the present disclosure is not limited thereto, and for example, the first data writing transistor P3 may be provided as an N-type transistor.
  • the specific structure of the light emission control sub-circuit 150 is not particularly limited.
  • the light emission control sub-circuit 150 includes the light emission control transistor P2.
  • the gate of the light emission control transistor P2 is formed as a control end of the light emission control sub-circuit 150, the first electrode of the light emission control transistor P2 is electrically connected to the first level signal terminal Vdd, and the second electrode of the light emission control transistor P2 and the driving transistor The first pole of the DTFT is electrically connected.
  • the first pole of the light-emission control transistor P2 and the second pole of the light-emission control transistor P2 can be turned on when the gate of the light-emitting control transistor P2 receives the first sub-light-emitting control signal, and the first pole of the light-emitting control transistor P2 and the light-emitting
  • the second pole of the control transistor P2 can be turned off when the gate of the light emission control transistor P2 receives the second sub-lighting control signal.
  • the lighting control signal includes a first sub-lighting control signal and a second sub-lighting control signal, and the first sub-lighting control signal is opposite in phase to the second sub-lighting control signal.
  • the light-emission control transistor P2 is a P-type transistor, and the first sub-light-emitting control signal is low-power.
  • the flat signal, the second sub-lighting control signal is a high level signal.
  • the light emission control transistor may be an N-type transistor. Accordingly, the first sub-light emission control signal is a high level signal, and the second sub-light emission control signal is a low level signal.
  • the storage sub-circuit 140 includes a storage capacitor C.
  • the first end of the storage capacitor C is formed as a first end of the storage sub-circuit 140, and the second end of the storage capacitor C is formed to be stored. The second end of the sub-circuit 140.
  • the first data write sub-circuit 110 includes an N-type data write transistor N1 and a P-type data write transistor P1
  • the second data write sub-circuit 120 includes a first data write.
  • the reset sub-circuit 130 includes a first reset transistor N2 and a second reset transistor N3
  • the memory sub-circuit 140 includes a storage capacitor C
  • the illumination control sub-circuit 150 includes an emission control transistor P2.
  • the N-type data write transistor N1, the first reset transistor N2, and the second reset transistor N3 are all N-type transistors, a P-type data write transistor P1, and an emission control transistor P2.
  • a data write transistor P3 is a P-type transistor.
  • the gate of the N-type data write transistor N1 is electrically connected to the first N-type gate line G1, the gate of the P-type data write transistor P1 is electrically connected to the first P-type gate line G2, and the gate of the first reset transistor N2
  • the first reset control signal line RS1 is electrically connected to the first reset control signal line RS1
  • the gate of the second reset transistor N3 is electrically connected to the first reset control signal line RS1
  • the gate of the first data write transistor P3 is electrically connected to the second gate line G3 to emit light.
  • the gate of the control transistor P2 is electrically connected to the light emission control signal line EM.
  • the input of the first data write sub-circuit 110 is electrically coupled to the first data line D1
  • the input of the second data write sub-circuit 120 is electrically coupled to the second data line D2.
  • the first N-type gate line G1 provides a third N-type data scan signal of a low level
  • the first P-type gate line G2 provides a third P-type data scan signal of a high level
  • the first reset control signal line RS1 provides a first sub-reset control signal of a high level
  • the illumination control signal line EM provides a first sub-emission control signal of a high level, and neither the first data line D1 nor the second data line D2 signal input.
  • no signal is supplied to the second gate line G3, or a high level signal is supplied to the second gate line G3.
  • the N-type data write transistor N1 and the P-type data write transistor P1 are both turned off, the first data write transistor P3 and the light-emission control transistor P2 are also turned off, the first reset transistor N2 and the second reset.
  • the transistor N3 is turned on to reset the second end of the storage capacitor C and the anode of the light emitting element OLED. Resetting the second end of the storage capacitor C and resetting the anode of the light emitting element OLED can prevent the display device including the pixel circuit from exhibiting motion blur when displayed.
  • a first N-type data scan signal of a high level is supplied to the first N-type gate line G1
  • a first P-type data scan signal of a low level is supplied to the first P-type gate line G2
  • the reset control signal line RS1 provides a second sub-reset control signal of a low level, supplies a first sub-emission control signal of a high level to the illumination control signal line EM, and supplies a first data voltage to the first data line D1, not to the first The second data line D2 provides the data voltage.
  • a high level signal is supplied to the second gate line G3.
  • the N-type data writing transistor N1 and the P-type data writing transistor P1 are both turned on, and the first data voltage is written into the first terminal of the storage capacitor C.
  • the first data write transistor P3, the light emission control transistor P2, the first reset transistor N2, and the second reset transistor N3 are all turned off, and at this time, the gate voltage of the driving transistor DTFT is the first voltage V1, that is, the first A data voltage.
  • the fourth sub-data scan signal of the low-level signal is supplied to the second gate line G3, and the first data write transistor P3 is controlled to be turned on, so that the second data voltage can be transmitted through the second data line D2.
  • the first terminal of the storage capacitor C that is, the gate voltage of the driving transistor DTFT rises to the second voltage V2
  • the second voltage V2 is the first data voltage and the second data voltage. with.
  • the transistors are silicon-based transistors, in order to ensure that the voltage difference between any two poles of the N-type data writing transistor N1 is within the threshold voltage range, the voltage difference between any two poles of the P-type data writing transistor P1 is within the threshold voltage range. Accordingly, the voltage of the signal written by the first N-type gate line G1 and the voltage of the signal written by the first P-type gate line G2 should be higher than the voltage in the charging phase T2, as shown in FIG. 3A. Show.
  • a low-level signal is supplied to the first N-type gate line G1, and a high-level signal is supplied to the first P-type gate line G2 to ensure that both the N-type data write transistor N1 and the P-type data write transistor P2 are provided. It is in the cutoff state. And, a high level signal is supplied to the second gate line G3 to ensure that the first data writing transistor P3 is turned off.
  • the gate voltage of the driving transistor DTFT is maintained at the second voltage V2.
  • the voltage of the source of the driving transistor DTFT (ie, the second electrode of the driving transistor DTFT) is V2-Vth, where Vth is the threshold voltage of the driving transistor DTFT.
  • V2 the second voltage
  • the source of the driving transistor DTFT ie, the anode of the light emitting element OLED
  • Mode 1 of the brightness display mode is the first voltage range.
  • the duty cycle of the pixel circuit may include only the reset phase T1, the charging phase T2, and the lighting phase T4, and does not include the voltage transition phase T3.
  • the present disclosure is not limited thereto, and the duty cycle of the pixel circuit may also include a voltage hopping phase T3, except that in the voltage hopping phase T3, a voltage of 0 V is supplied through the second data line D2.
  • the voltage of the first N-type gate line G1 maintains the voltage of the charging phase T2
  • the voltage of the first P-type gate line G2 maintains the voltage of the charging phase T2
  • the gate voltage of the driving transistor DTFT remains
  • the first data voltage V1 the source voltage of the driving transistor DTFT is V1-Vth. Since the first voltage V1 is lower than the second voltage V2, the source voltage of the driving transistor DTFT is also lower than V2-Vth, so that the voltage difference between the anode and the cathode of the light emitting element OLED can be ensured to be small, and the low brightness is satisfied. Mode two.
  • FIG. 5 is a schematic diagram of a display panel according to some embodiments of the present disclosure.
  • the display panel 50 includes a plurality of pixel units 500, and each of the pixel units 500 is provided with a pixel circuit 501.
  • the pixel circuit 501 is provided in any of the above embodiments of the present disclosure.
  • the pixel circuit 10 further includes a light-emitting element 502 in each of the pixel units 500.
  • the light-emitting element 502 is the light-emitting element OLED described in any of the above embodiments, and the pixel circuit 501 is used to drive the light-emitting element 502 to emit light.
  • the plurality of pixel units 500 are arranged in a plurality of rows and columns, and the plurality of rows of pixel units of the plurality of pixel units 500 are respectively in one-to-one correspondence with the plurality of gate line groups, and the plurality of pixel units of the plurality of pixel units 500 are respectively Column data line groups correspond one-to-one.
  • each of the plurality of gate line groups includes a first gate line and a second gate line G3, the first gate line being configured to provide a first data scan signal,
  • the second gate line G3 is configured to provide a second data scan signal.
  • Each of the gate line groups further includes a first reset control signal line RS1, a second reset control signal line RS2, and an emission control signal line EM.
  • a control end of the first data writing sub-circuit 110 of each of the pixel units 500 is electrically connected to the first gate line to receive a first data scan signal, each of the pixel units 500
  • the control end of the second data writing sub-circuit 120 is electrically connected to the second gate line G3 to receive the second data scanning signal, and the control end of the reset sub-circuit of each of the pixel units 500 and the first reset control signal line RS1
  • the second reset control signal line RS2 is electrically connected, and the control end of the light emission control sub-circuit 150 of each of the pixel units 500 is electrically connected to the light emission control signal line EM.
  • Each of the plurality of data line groups includes a first data line D1 configured to provide a first data voltage and a second data line D2 configured to provide The second data voltage.
  • an input end of the first data writing sub-circuit 110 of each of the pixel units 500 is electrically connected to the first data line D1 to receive a first data voltage, the first of each of the pixel units 500
  • the input of the two data write subcircuit 120 is electrically coupled to the second data line D2 to receive the second data voltage.
  • the control end of the first data writing sub-circuit 110 includes an N-type control terminal (ie, a first sub-control terminal) and a P-type control terminal (ie, a second sub-control terminal), and the first data scan signal includes The first N-type data scan signal and the first P-type data scan signal.
  • the first data writing sub-circuit 110 includes an N-type data writing transistor N1 and a P-type data writing transistor N2.
  • the first gate line includes a first sub-gate line G1 (ie, a first N The gate line G1) and the second gate line G2 (ie, the first P-type gate line G2), in the same row of pixel units, the N-type control terminal of each of the pixel units is electrically connected to the first N-type gate line G1 Connected, the P-type control terminal of the pixel unit is electrically connected to the first P-type gate line G2.
  • FIG. 6 is a schematic diagram of a display device according to some embodiments of the present disclosure.
  • the display device 60 includes a display panel 600 and a photosensitive element 603.
  • the display panel 600 is the display panel 50 provided by the present disclosure
  • the photosensitive element 603 is configured to detect the Displaying the brightness of the environment in which the device 60 is located, and generating a first trigger signal to control the display device 60 to be in the first operating mode when the brightness of the environment is higher than or equal to the preset brightness, wherein the brightness of the environment is lower than the preset brightness
  • a second trigger signal is generated to control the display device 60 to be in the second mode of operation.
  • display brightness of display device 60 in the first mode of operation is greater than display brightness of display device 60 in the second mode of operation.
  • the first mode of operation is mode one described above in Figures 4A and 4B
  • the second mode of operation is mode two described above in Figures 4A and 4B.
  • display device 60 also includes a data driver 601.
  • the data driver 601 is configured to be electrically connected to the pixel circuits in the display panel 600 through the first data line D1 and the second data line D2, and to provide a first data voltage to the pixel circuits in the display panel 600 through the first data line D1, A second data voltage is supplied to the pixel circuits in the display panel 600 through the second data line D2.
  • the data driver 601 when the display device 60 is in the first working mode, during the charging phase, the data driver 601 supplies the first data voltage to the pixel circuit in the display panel 600 through the first data line D1; during the voltage transition phase, the data The driver 601 supplies a second data voltage to the pixel circuits in the display panel 600 through the second data line D2.
  • the data driver 601 can supply the first data voltage to the pixel circuits in the display panel 600 through the first data line D1 only during the charging phase.
  • display device 60 also includes a gate driver 602.
  • the gate driver 602 is configured to provide a first data scan signal and a second data scan signal to pixel circuits in the display panel 600.
  • the level of the first data scan signal and the electrical average of the second data scan signal are toggled, and FIGS. 3A-3C illustrate the first data scan.
  • FIGS. 3A-3C illustrate the first data scan.
  • FIG. 7 is a schematic flowchart of a driving method of a display device according to some embodiments of the present disclosure.
  • the duty cycle of the display panel includes a reset phase T1, a charging phase T2, and a voltage transition phase.
  • T3 and illumination stage T4 as shown in FIG. 7, the driving method includes:
  • the driving subcircuit drives the light emitting element to emit light based on the voltage of the first end of the storage subcircuit.
  • step S11 when the driving transistor is an N-type transistor, the voltage of the first terminal of the storage sub-circuit in the charging phase is less than the voltage of the first terminal of the storage sub-circuit in the voltage hopping phase; when the driving transistor is In the case of a P-type transistor, the voltage at the first terminal of the storage sub-circuit during the charging phase is greater than the voltage at the first terminal of the storage sub-circuit during the voltage transition phase.
  • the driving method further includes: in the reset phase, writing a first reference level signal to the second end of the storage sub-circuit through the reset sub-circuit to reset the second end of the storage sub-circuit, and to the light-emitting element through the reset sub-circuit
  • the anode writes a first reference level signal to reset the anode of the light emitting element.
  • the display device can also include a drive circuit configured to perform various steps in the above described drive methods.
  • the driver circuit is used to:
  • a first sub-reset control signal is supplied to all of the first reset control signal lines and all of the second reset control signal lines, and a third N-type data scan signal and a third P-type data scan are supplied to all of the first gate lines.
  • a second sub-reset control signal is provided to all of the first reset control signal lines and all of the second reset control signal lines, and the first N-type data scan signals are sequentially supplied to the respective first gate lines in accordance with a predetermined scanning order.
  • a first P-type data scan signal providing a fourth sub-data scan signal to all of the second gate lines, a second sub-emission control signal to all of the illumination control signal lines, and a first data voltage to the first data line;
  • a second sub-reset control signal is supplied to all of the first reset control signal lines and all of the second reset control signal lines, and the fifth N-type data scan signal and the fifth P-type are supplied to all of the first gate lines.
  • a data scan signal which sequentially supplies a third sub-data scan signal to each of the second gate lines in accordance with the predetermined scan order, a second sub-light emission control signal to all of the light emission control signal lines, and a second data voltage to the second data line
  • the second data voltage is higher than the first data voltage by a preset value, for example, the first sub-data scan signal may further include a fifth N-type data scan signal, and the second sub-data scan signal may further include a fifth P The type data scanning signal, as shown in FIG.
  • the voltage of the fifth N-type data scanning signal is higher than the voltage of the first N-type data scanning signal, and is also higher than the voltage of the third N-type data scanning signal, and the fifth The voltage of the P-type data scan signal is higher than the voltage of the first P-type data scan signal, and higher than the voltage of the third P-type data scan signal;
  • a second sub-reset control signal is provided to all of the first reset control signal lines and all of the second reset control signal lines, and a third N-type data scan signal and a third P-type data scan are provided to all of the first gate lines.
  • the signal provides a fourth sub-data scan signal to all of the second gate lines and a first sub-emission control signal to all of the illumination control signal lines.
  • the driving circuit may also supply the fifth N-type data scanning signal and the fifth P-type data scanning signal to all the first gate lines.
  • the "preset value" is not particularly limited.
  • a data voltage range of high contrast (for example, 20,000:1) and high brightness (>1500 nit) is achieved. 5V to 9V, and high contrast (for example, 20000:1) and low brightness (375nit) data voltage range of 1V to 5V.
  • the preset value is 3V.
  • the working period of the display panel includes three stages of a reset phase, a charging phase, and an illumination phase.
  • the driving method includes: in the charging phase, controlling the first data writing sub-circuit to write the first data voltage to the first end of the storage sub-circuit; in the lighting phase, the driving sub-circuit is based on the voltage of the first end of the storage sub-circuit The light emitting element is driven to emit light.
  • the duty cycle of the display panel also includes a reset phase, a charging phase, a voltage hopping phase, and an illuminating control phase, except that the charging phase and the voltage hopping phase
  • the signals are the same, and during the voltage transition phase, the second data voltage is 0V.
  • control terminal of the first data writing sub-circuit includes an N-type control terminal and a P-type control terminal
  • the first data writing sub-circuit includes an N-type data writing transistor and a P-type data writing transistor.
  • the first data scan signal includes a first N-type data scan signal supplied to the first N-type gate line, and a first P-type data scan signal supplied to the first P-type gate line, to the a third N-type data scan signal provided by an N-type gate line and a third P-type data scan signal supplied to the first P-type gate line, the first N-type data scan signal being a high level signal,
  • the third N-type data scan signal is a low level signal
  • the first P-type data scan signal is a low level signal
  • the third P-type data scan signal is a high level signal;
  • the first data scan signal may further include a fifth N-type data scan signal supplied to the first N-type gate line and a fifth P-type data scan signal supplied to the first P-type gate line,
  • the fifth N-type data scan signal is higher than the voltage of the first N-type data scan signal
  • the voltage of the fifth P-type data scan signal is higher than the voltage of the first P-type data scan signal.
  • the fifth N-type data scan signal is also higher than the voltage of the third N-type data scan signal
  • the voltage of the fifth P-type data scan signal is also higher than the third P-type data. The voltage of the scan signal.
  • the specific structure of the display device 60 is not particularly limited.
  • the display device 60 may be a near-eye device (for example, VR glasses), so that the virtual scene can be better simulated according to the surrounding environment, which is advantageous. Improve the user experience.
  • a near-eye device for example, VR glasses

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Abstract

一种像素电路(10,501)、显示面板(50)和显示装置(60)及其驱动方法，像素电路(10,501)包括驱动子电路(100)、第一数据写入子电路(110)、第二数据写入子电路(120)和存储子电路(140)，第一数据写入子电路(110)被配置为在第一数据扫描信号的控制下导通时向存储子电路(140)的第一端写入第一数据电压；第二数据写入子电路(120)被配置为在第二数据扫描信号的控制下导通时向存储子电路(140)的第二端写入第二数据电压，以基于第二数据电压控制存储子电路(140)的第一端的电压；存储子电路(140)的第一端还与驱动子电路(100)的控制端电连接；驱动子电路(100)被配置在存储子电路(140)的第一端的电压的控制下驱动发光元件(OLED,502)发光。

Description

像素电路、显示面板和显示装置及其驱动方法
本申请要求于2018年04月19日递交的中国专利申请第201810353782.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种像素电路、显示面板、显示装置及其驱动方法。
背景技术
有机发光二极管显示面板已经得到了广泛的应用。由于有机发光二极管显示面板能够主动发光，因此，不需要额外设置背光源，从而可以满足对用户对显示设备轻薄化的需求。
随着用户要求的提升，已经出现了随着环境亮度不同而改变显示装置对比度的技术。例如，在夜间显示时需要高对比度和低亮度，而在日间显示时，需要低对比度和高亮度。
发明内容
本公开至少一些实施例提供一种像素电路、显示面板和显示装置及其驱动方法。像素电路可以实现高亮度和高对比度的两种工作模式，并且结构简单易于实现。
本公开至少一些实施例提供一种像素电路，包括：驱动子电路、第一数据写入子电路、第二数据写入子电路和存储子电路，其中，所述第一数据写入子电路与所述存储子电路的第一端电连接，且被配置为在第一数据扫描信号的控制下导通时向所述存储子电路的第一端写入第一数据电压；所述第二数据写入子电路与所述存储子电路的第二端电连接，且被配置为在第二数据扫描信号的控制下导通时向所述存储子电路的第二端写入第二数据电压，以基于所述第二数据电压控制所述存储子电路的第一端的电压；所述存储子电路的第一端还与所述驱动子电路的控制端电连接；所述驱动子电路被配置在所述存储子电路的第一端的电压的控制下驱动发光元件发光。
例如，在本公开一些实施例提供的像素电路中，所述第二数据写入子电路 包括第一数据写入晶体管，所述第一数据写入晶体管的栅极被配置为接收所述第二数据扫描信号，所述第一数据写入晶体管的第一极被配置为接收所述第二数据电压，所述第一数据写入晶体管的第二极与所述存储子电路的第二端电连接。
例如，在本公开一些实施例提供的像素电路中，在所述第二数据扫描信号处于第一电平时，所述第一数据写入晶体管导通，在所述第二数据扫描信号处于第二电平时，所述第一数据写入晶体管断开，所述第一电平和所述第二电平为彼此相反的电平。
例如，在本公开一些实施例提供的像素电路中，所述第一数据写入晶体管为P型晶体管。
例如，在本公开一些实施例提供的像素电路中，所述第一数据写入子电路的控制端被配置为接收所述第一数据扫描信号，所述第一数据写入子电路的控制端包括第一子控制端和第二子控制端，所述第一数据扫描信号包括第一子数据扫描信号和第二子数据扫描信号，所述第一子控制端被配置为接收所述第一子数据扫描信号，所述第二子控制端被配置为接收所述第二子数据扫描信号。
例如，在本公开一些实施例提供的像素电路中，所述第一数据写入子电路包括N型数据写入晶体管和P型数据写入晶体管，所述N型数据写入晶体管的第一极与所述P型数据写入晶体管的第一极均被配置为接收所述第一数据电压，所述N型数据写入晶体管的第二极与所述P型数据写入晶体管的第二极均与所述存储子电路的第一端电连接，所述第一子控制端包括所述N型数据写入晶体管的栅极，所述第二子控制端包括所述P型数据写入晶体管的栅极。
例如，本公开一些实施例提供的像素电路还包括复位子电路，所述复位子电路的第一输出端与所述存储子电路的第二端电连接，所述复位子电路的第二输出端与所述发光元件的阳极电连接，所述复位子电路被配置为在第一复位控制信号的控制下对所述存储子电路的第二端进行复位，在第二复位控制信号的控制下对所述发光元件的阳极进行复位。
例如，在本公开一些实施例提供的像素电路中，所述复位子电路的输入端与第一参考电平信号端和第二参考电平信号端电连接，所述复位子电路被配置为在所述第一复位控制信号的控制下将所述第一参考电平信号端的第一参考电平信号写入所述存储子电路的第二端以对所述存储子电路的第二端进行复位，所述复位子电路还被配置为在所述第二复位控制信号的控制下将所述第二 参考电平信号端的第二参考电平信号写入所述发光元件的阳极以对所述发光元件的阳极进行复位。
例如，在本公开一些实施例提供的像素电路中，所述复位子电路包括第一复位晶体管和第二复位晶体管，所述复位子电路的输入端包括所述第一复位晶体管的第一极和所述第二复位晶体管的第一极，所述第一输出端包括所述第一复位晶体管的第二极，所述第二输出端包括所述第二复位晶体管的第二极，所述第一复位晶体管的栅极被配置为接收所述第一复位控制信号，所述第一复位晶体管的第一极被配置为与所述第一参考电平信号端电连接，所述第一复位晶体管的第二极与所述存储子电路的第二端电连接；所述第二复位晶体管的栅极被配置为接收所述第二复位控制信号，所述第二复位晶体管的第一极被配置为与所述第二参考电平信号端电连接，所述第二复位晶体管的第二极与所述发光元件的阳极电连接。
例如，本公开一些实施例提供的像素电路还包括发光控制子电路，所述发光控制子电路被配置为在发光控制信号的控制下实现所述驱动子电路和所述发光元件之间的连接导通或断开。
例如，在本公开一些实施例提供的像素电路中，所述发光控制子电路包括发光控制晶体管，所述发光控制晶体管的栅极被配置为接收所述发光控制信号，所述发光控制晶体管的第一极与第一电平信号端电连接，所述发光控制晶体管的第二极与所述驱动子电路电连接。
例如，在本公开一些实施例提供的像素电路中，所述驱动子电路包括驱动晶体管，所述驱动晶体管的第一极与所述发光控制子电路电连接，所述驱动晶体管的第二极与所述发光元件的阳极电连接，所述驱动子电路的控制端包括所述驱动晶体管的栅极，所述驱动晶体管的栅极与所述存储子电路的第一端，所述发光元件的阴极与第二电平信号端电连接。
例如，在本公开一些实施例提供的像素电路中，所述存储子电路包括存储电容，所述存储子电路的第一端包括所述存储电容的第一端，所述存储子电路的第二端包括所述存储电容的第二端。
本公开至少一些实施例还提供一种显示面板，包括上述任意一项所述的像素电路。
例如，本公开一些实施例提供的显示面板还包括多个像素单元，所述多个像素单元排列为多行多列，每个像素单元内均设置有所述像素电路。
例如，在本公开一些实施例提供的显示面板中，所述多个像素单元的多行像素单元分别与多个栅线组一一对应，所述多个像素单元的多列像素单元分别与多列数据线组一一对应；所述多个栅线组中的每个包括第一栅线和第二栅线，所述第一栅线被配置为提供所述第一数据扫描信号，所述第二栅线被配置为提供所述第二数据扫描信号，在同一行像素单元中，每个所述像素单元的第一数据写入子电路与所述第一栅线电连接以接收所述第一数据扫描信号，每个所述像素单元的第二数据写入子电路与所述第二栅线电连接以接收所述第二数据扫描信号；所述多个数据线组中的每个包括第一数据线和第二数据线，所述第一数据线被配置为提供所述第一数据电压，所述第二数据线被配置为提供所述第二数据电压，在同一列像素单元中，每个所述像素单元的第一数据写入子电路与所述第一数据线电连接以接收所述第一数据电压，每个所述像素单元的第二数据写入子电路与所述第二数据线电连接以接收所述第二数据电压。
例如，在本公开一些实施例提供的显示面板中，在所述第一数据写入子电路的控制端包括第一子控制端和第二子控制端的情况下；所述第一栅线包括第一子栅线和第二子栅线，在同一行像素单元中，每个所述像素单元的第一数据写入子电路的第一子控制端与所述第一子栅线电连接，每个所述像素单元的第一数据写入子电路的第二子控制端与所述第二子栅线电连接。
本公开至少一些实施例还提供一种显示装置，包括上述任一项所述的显示面板。
例如，本公开一些实施例提供的显示装置还包括光敏元件，所述光敏元件用于检测所述显示装置所处的环境的亮度，并在所述亮度高于或等于预设亮度时生成第一触发信号以控制所述显示装置处于第一工作模式，在所述亮度低于所述预设亮度时生成第二触发信号以控制所述显示装置的处于第二工作模式。
例如，在本公开一些实施例提供的显示装置中，所述显示装置在所述第一工作模式下的显示亮度大于所述显示装置在所述第二工作模式下的显示亮度。
例如，本公开一些实施例提供的显示装置还包括数据驱动器，所述数据驱动器被配置为通过第一数据线和第二数据线与所述显示面板中的像素电路电连接，且通过所述第一数据线向所述像素电路提供所述第一数据电压，通过所述第二数据线向所述像素电路提供所述第二数据电压。
例如，本公开一些实施例提供的显示装置还包括栅极驱动器，所述栅极驱动器被配置为向所述显示面板中的像素电路提供所述第一数据扫描信号和所 述第二数据扫描信号。
本公开至少一些实施例还提供一种根据上述任一项所述的显示装置的驱动方法，当所述光敏元件生成所述第一触发信号时，所述显示面板的工作周期包括充电阶段、电压跳变阶段和发光阶段，所述驱动方法包括：在所述充电阶段，控制所述第一数据写入子电路向所述存储子电路的第一端写入所述第一数据电压；在所述电压跳变阶段，控制所述第二数据写入子电路向所述存储子电路的第二端写入所述第二数据电压，以控制所述存储子电路的第一端的电压，其中，在所述充电阶段中所述存储子电路的第一端的电压与在所述电压跳变阶段中所述存储子电路的第一端的电压不相同；在所述发光阶段，所述驱动子电路基于所述存储子电路的第一端的电压驱动所述发光元件发光。
本公开至少一些实施例还提供一种根据上述任一项所述的显示装置的驱动方法，当所述光敏元件生成所述第二触发信号时，所述显示面板的工作周期包括充电阶段和发光阶段，所述驱动方法包括：在所述充电阶段，控制所述第一数据写入子电路向所述存储子电路的第一端写入所述第一数据电压；在所述发光阶段，所述驱动子电路基于所述存储子电路的第一端的电压驱动所述发光元件发光。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A是本公开一些实施例提供的一种像素电路的示意图；
图1B是本公开一些实施例提供的另一种像素电路的示意图；
图2A是本公开一些实施例提供的一种像素电路的电路结构示意图；
图2B是本公开一些实施例提供的另一种像素电路的电路结构示意图；
图3A是本公开一些实施例提供的一种像素电路工作时的一种时序信号图；
图3B是本公开一些实施例提供的一种像素电路工作时的另一种时序信号图；
图3C是本公开一些实施例提供的一种像素电路工作时的又一种时序信号图；
图4A是本公开一些实施例提供的一种发光元件的两端电压与发光亮度之间的关系图；
图4B是本公开一些实施例提供的另一种发光元件的两端电压与发光亮度之间的关系图；
图5为本公开一些实施例提供的一种显示面板的示意图；
图6为本公开一些实施例提供的一种显示装置的示意图；
图7为本公开一些实施例提供的一种显示装置的驱动方法的示意性流程图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
本公开至少一些实施例提供一种像素电路。图1A是本公开一些实施例提供的一种像素电路的示意图，图1B是本公开一些实施例提供的另一种像素电路的示意图；图2A是本公开一些实施例提供的一种像素电路的电路结构示意图；图2B是本公开一些实施例提供的另一种像素电路的电路结构示意图；图3A是本公开一些实施例提供的一种像素电路工作时的一种时序信号图；图3B 是本公开一些实施例提供的一种像素电路工作时的另一种时序信号图；图3C是本公开一些实施例提供的一种像素电路工作时的又一种时序信号图；图4A是本公开一些实施例提供的一种发光元件的两端电压与发光亮度之间的关系图；图4B是本公开一些实施例提供的另一种发光元件的两端电压与发光亮度之间的关系图。
例如，如图1A所示，在一些实施例中，像素电路10包括驱动子电路100、第一数据写入子电路110、第二数据写入子电路120和存储子电路140。像素电路10用于驱动发光元件OLED发光。
例如，第一数据写入子电路110与存储子电路140的第一端电连接。在第一数据扫描信号的控制下，当第一数据写入子电路110导通时，第一数据写入子电路110被配置为向存储子电路140的第一端写入第一数据电压。
第二数据写入子电路120与存储子电路140的第二端电连接。也就是说，第一数据写入子电路110和第二数据写入子电路120分别连接存储子电路140的两端。在第二数据扫描信号的控制下，当第二数据写入子电路120导通时，第二数据写入子电路120被配置为向存储子电路140的第二端写入第二数据电压，以基于第二数据电压控制存储子电路140的第一端的电压。
存储子电路140的第一端还与驱动子电路100的控制端电连接；驱动子电路100被配置在存储子电路140的第一端的电压的控制下驱动发光元件OLED发光。
本公开实施例提供的像素电路可以实现高亮度和低亮度的两种工作模式，同时可以保证高对比度，并且结构简单易于实现。例如，在本公开的实施例提供了一种利用低压Wafer(晶圆)Mos制程实现高压驱动的Micro OLED驱动方案设计，通过在像素电路中增加第二数据写入子电路，采用电压跳变的方式，再配合各个控制信号的数值，实现两种工作模式，在既定的低压Mos制程限制下(例如，0.11um，6V制程)使得Micro OLED器件在wafer特定的耐压范围内可以既满足高亮度同时兼容高对比度，从而可以在低压的TFT制程工艺下，实现高压的发光元件的驱动，实现高亮度，同时保证高对比度。
例如，在另一些实施例中，像素电路10还包括复位子电路130和发光控制子电路150，即如图1B所示，像素电路10包括驱动子电路100、第一数据写入子电路110、第二数据写入子电路120、复位子电路130、存储子电路140和发光控制子电路150。
例如，第一数据写入子电路110的输出端与存储子电路140的第一端电连接，第一数据写入子电路140的输入端和该第一数据写入子电路140的输出端能够在该第一数据写入子电路110的控制端接收到的第一数据扫描信号的控制下导通。
例如，第二数据写入子电路120的输出端与存储子电路140的第二端电连接，第二数据写入子电路120的输入端和该第二数据写入子电路120的输出端能够在该第二数据写入子电路120的控制端接收到的第二数据扫描信号的控制下导通。
例如，复位子电路130被配置为在第一复位控制信号的控制下对存储子电路140的第二端进行复位，在第二复位控制信号的控制下对发光元件OLED的阳极进行复位。
例如，复位子电路130的输入端与第一参考电平信号端Vcom1和第二参考电平信号端Vcom2电连接，复位子电路130的第一输出端与存储子电路140的第二端电连接，复位子电路130的第二输出端与发光元件OLED的阳极电连接。复位子电路130的输入端和复位子电路130的第一输出端能够在该复位子电路130的控制端接收到的第一复位控制信号的控制下导通，复位子电路130的输入端和复位子电路130的第二输出端能够在该复位子电路130的控制端接收到的第二复位控制信号的控制下导通。即复位子电路130被配置为在第一复位控制信号的控制下将第一参考电平信号端Vcom1的第一参考电平信号写入存储子电路140的第二端以对存储子电路140的第二端进行复位，复位子电路130还被配置为在第二复位控制信号的控制下将第二参考电平信号端Vcom2的第二参考电平信号写入发光元件OLED的阳极以对发光元件OLED的阳极进行复位。
例如，存储子电路140的第一端与驱动子电路100的控制端电连接，存储子电路140用于存储通过第一数据写入子电路110写入的第一数据电压和通过第二数据写入子电路120写入的第二数据电压。
例如，发光控制子电路150被配置为在发光控制信号的控制下实现驱动子电路100和发光元件OLED之间的连接导通或断开。发光控制信号包括第一子发光控制信号和第二子发光控制信号。
如图1A和图1B所示，发光元件OLED的阴极与第二电平信号端Vss电连接，发光控制子电路150用于在接收到第一子发光控制信号时允许第一电平 信号端Vdd、驱动子电路100的第一端、驱动子电路100的第二端、发光元件OLED、第二电平信号端Vss之间形成通路，且发光控制子电路150还用于在接收到第二子发光控制信号时将第一电平信号端Vdd、驱动子电路100的第一端、驱动子电路100的第二端、发光二极管OLED、第二电平信号端Vss之间的通路断开。
例如，发光元件OLED可以为发光二极管等。发光二极管可以为有机发光二极管(OLED)或量子点发光二极管(QLED)等。发光元件OLED被配置为在工作时接收发光信号(例如，可以为电流信号)，并发出与该发光信号相对应强度的光。
例如，第一电平信号端Vdd和第二电平信号端Vss之一为高电平信号端，另一个为低电平信号端。在图1A和图1B所示的实施例中，第一电平信号端Vdd为电压源以输出恒定的正电压；而第二电平信号端Vss可以为电压源以输出恒定的负电压，或可以接地等。
例如，在像素电路10的工作过程中，第二电平信号端Vss输出的信号保持不变。
在本公开所提供的像素电路中包括第一数据写入子电路110和第二数据写入子电路120共两个数据写入子电路。
所述像素电路10可以应用于显示面板中，例如AMOLED显示面板等，显示面板的最终显示亮度与画面对比度与发光元件OLED的阳极和阴极的压差V EL相关。发光元件OLED具有两种工作模式，当发光元件OLED的阳极和阴极之间的压差V EL在第一区间之内时，可以实现高亮度的模式一(即第一工作模式)，当发光元件OLED的阳极和阴极之间的压差在第二区间之内时，可以实现高对比度的模式二(即第二工作模式)。
如图4A中所示的是一种具体的发光元件的工作模式，如图4B中所示的是另一种具体的发光元件的工作模式。在一些示例中，如图4A所示，当该发光元件的阳极和阴极之间的压差V EL在4.3V至5.4V之间时，可以实现高对比度的模式二；当该发光二极管的阳极和阴极之间的压差V EL在5.1V至6.1V之间时，可以实现高亮度的模式一，即第一区间为4.3V至5.4V，第二区间为5.1V至6.1V。本公开不限于此，又例如，在另一些示例中，如图4B所示，当该发光元件的阳极和阴极之间的压差V EL在4.5V至7.0V之间时，可以实现高对比度的模式二；当该发光元件的阳极和阴极之间的压差V EL在6.2V至8.5V之间 时，可以实现高亮度的模式一，即第一区间为4.5V至7.0V，第二区间为6.2V至8.5V。
当包括所述像素电路的显示面板所处环境亮度较高，显示面板需要实现高亮度、高对比的显示效果时，向第二数据写入子电路120的控制端提供第二数据扫描信号，并向第二数据写入子电路120的输入端提供第二数据电压，以使存储子电路140的第一端升压，从而可以实现增加发光元件OLED两端的压差，以确保高亮度、高对比度的显示效果。
当包括所述像素电路的显示面板所处环境亮度较低，显示面板需要实现低亮度、高对比的显示效果时，停止通过第二数据写入子电路120向存储子电路140输入第二数据电压，或者通过第二数据写入子电路120向存储子电路140提供第一数据电压，以确保发光元件OLED两端的压差较小，实现低亮度、高对比度的显示效果。
由此可知，在利用本公开所提供的像素电路10实现两种不同的工作模式时，无需设置两个低电平信号端，也无需设置复杂的电压切换电路，且像素电路10易于实现。
需要指出的是，本公开的实施例中采用的晶体管也可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，在一些实施例中，本公开所提供的像素电路10中所用到的驱动晶体管为硅基晶体管，对于硅基晶体管而言，不容易出现阈值电压漂移的问题，因此，本公开所提供的像素电路10中也可以不需要设置阈值补偿子电路。但本公开不限于此，本公开所提供的像素电路10中也可以设置阈值补偿子电路。
例如，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管P1-P3、驱动晶体管DTFT均为P型晶体管(例如，P型MOS晶体管)和晶体管N1-N3均为N型晶体管(例如，N型MOS晶体管)为例详细阐述了本公开的技术方案，然而本公开的实施例的晶体管不限于上述情况，本领域技术人员还可以根据实际需要设置本公开中的 晶体管的类型。
在本公开中，复位子电路130用于对存储子电路140以及发光元件OLED的阳极进行复位，发光控制子电路150用于防止发光元件OLED在发光阶段之前发光。
图2A为图1B所示的像素电路的一种电路结构示意图，下面结合图2A详细描述本公开的像素电路。
例如，如图2A所示，驱动子电路100包括驱动晶体管DTFT，驱动晶体管DTFT的第一极与发光控制子电路150电连接，驱动晶体管DTFT的第二极与发光元件OLED的阳极电连接，驱动子电路100的控制端包括驱动晶体管DTFT的栅极，驱动晶体管DTFT的栅极与存储子电路140的第一端电连接。
例如，发光元件OLED的阴极与第二电平信号端Vss电连接。
例如，第一数据写入子电路110的控制端被配置为电连接第一栅线以接收第一数据扫描信号。在一些实施例中，第一数据写入子电路110的控制端包括第一子控制端和第二子控制端，第一数据扫描信号包括第一子数据扫描信号和第二子数据扫描信号，第一子控制端被配置为接收第一子数据扫描信号，第二子控制端被配置为接收第二子数据扫描信号。
例如，在一些示例中，第一子控制端为N型控制端，第二子控制端为P型控制端。第一子数据扫描信号为N型数据扫描信号，第二子数据扫描信号为P型数据扫描信号。
例如，如图2A所示，第一数据写入子电路110包括N型数据写入晶体管N1和P型数据写入晶体管P1。第一数据写入子电路140的输入端包括N型数据写入晶体管N1的第一极与P型数据写入晶体管P1的第一极，第一数据写入子电路110的输出端包括N型数据写入晶体管N1的第二极与P型数据写入晶体管P1的第二极，第一数据写入子电路110的控制端包括N型数据写入晶体管N1的栅极和P型数据写入晶体管P1的栅极。
例如，N型数据写入晶体管N1的第一极与P型数据写入晶体管P1的第一极均被配置为接收第一数据电压，例如，N型数据写入晶体管N1的第一极与P型数据写入晶体管P1的第一极均电连接至第一数据信号线D1以接收第一数据电压。N型数据写入晶体管N1的第二极与P型数据写入晶体管P1的第二极均与存储子电路140的第一端电连接。第一子控制端包括N型数据写入晶体管N1的栅极，第二子控制端包括P型数据写入晶体管P1的栅极，也就是说，N 型数据写入晶体管N1的栅极被配置为接收第一子数据扫描信号，P型数据写入晶体管P1的栅极被配置为接收第二子数据扫描信号。
例如，第一栅线包括第一子栅线G1和第二子栅线G2，第一子栅线G1被配置为输出第一子数据扫描信号，第二子栅线G2被配置为输出第二子数据扫描信号。从而，如图2A所示，N型数据写入晶体管N1的栅极电连接至第一子栅线G1以接收第一子数据扫描信号，P型数据写入晶体管P1的栅极电连接至第二栅线G2以接收第二子数据扫描信号。
例如，第一数据写入子电路110采用两个不同类型的晶体管，可以增加写入数据电压的电压范围，N型数据写入晶体管N1对应高电平的第一数据电压，P型数据写入晶体管P1对应低电平的第一数据电压。
例如，如图2A所示，第二数据写入子电路120包括第一数据写入晶体管P3。第二数据写入子电路120的输入端包括第一数据写入晶体管P3的第一极，第二数据写入子电路120的输出端包括第一数据写入晶体管P3的第二极，第二数据写入子电路120的控制端包括第一数据写入晶体管P3的栅极。
例如，第一数据写入晶体管P3例如可以为P型晶体管，但本公开不限于此，第一数据写入晶体管P3也可以为N型晶体管。
例如，第一数据写入晶体管P3的栅极被配置为电连接至第二栅线G3以接收第二数据扫描信号，第一数据写入晶体管P3的第一极被配置为电连接至第二数据线D2以接收第二数据电压，第一数据写入晶体管P3的第二极与存储子电路140的第二端电连接。
例如，在第二数据扫描信号处于第一电平时，第一数据写入晶体管P3导通，在第二数据扫描信号处于第二电平时，第一数据写入晶体管P3断开，第一电平和第二电平为彼此相反的电平。例如，当第一数据写入晶体管P3为P型晶体管时，第一电平为低电平，第二电平为高电平；当第一数据写入晶体管P3为N型晶体管时，第一电平为高电平，第二电平为低电平。
例如，如图2A所示，存储子电路140包括存储电容C。存储子电路140的第一端包括存储电容C的第一端，存储子电路140的第二端包括存储电容C的第二端，也就是说，存储电容C的第一端电连接至N型数据写入晶体管N1的第二极和P型数据写入晶体管P1的第二极，存储电容C的第二端电连接至第一数据写入晶体管P3的第二极。
例如，当第一数据写入晶体管P3向存储电容C的第二端写入第二数据电 压时，由于存储电容C的自举效应，存储电容C的第一端的电压发生相应变化，且变化量可以为第二数据电压，从而实现对存储电容C的第一端的电压拉高或拉低。例如，当第二数据电压为正电压时，存储电容C的第一端的电压被拉高；当第二数据电压为负电压时，存储电容C的第一端的电压被拉低。需要说明的是，在第一数据写入晶体管P3向存储电容C的第二端写入第二数据电压之前，存储电容C的第二端的电压可以为0V。
例如，如图2A所示，复位子电路130包括第一复位晶体管N2和第二复位晶体管N3。复位子电路130的输入端包括第一复位晶体管N2的第一极和第二复位晶体管N3的第一极，复位子电路130的第一输出端包括第一复位晶体管N2的第二极，复位子电路130的第二输出端包括第二复位晶体管N3的第二极。
例如，如图2A所示，第一复位晶体管N2的栅极被配置为连接至第一复位控制信号线RS1以接收第一复位控制信号，第一复位晶体管N2的第一极被配置为与第一参考电平信号端Vcom1电连接以接收第一参考电平信号，第一复位晶体管N2的第二极与存储子电路140的第二端电连接，即第一复位晶体管N2的第二极与存储电容C的第二端电连接。当第一复位晶体管N2在第一复位控制信号的控制下导通时，第一参考电平信号端Vcom1的第一参考电平信号经由第一复位晶体管N2被传输至存储电容C的第二端，以实现对存储电容C的第二端进行复位。
例如，如图2A所示，第二复位晶体管N3的栅极被配置为连接至第二复位控制信号线RS2以接收第二复位控制信号，第二复位晶体管N3的第一极被配置为与第二参考电平信号端Vcom2电连接以接收第二参考电平信号，第二复位晶体管N3的第二极与发光元件OLED的阳极电连接。当第二复位晶体管N3在第二复位控制信号的控制下导通时，第二参考电平信号端Vcom2的第二参考电平信号经由第二复位晶体管N3被传输至发光元件OLED的阳极，以实现对发光元件OLED的阳极进行复位。
例如，在一些实施例中，如图2A所示，第一复位控制信号和第二复位控制信号可以为不同的信号，但在另一些实施例中，如图2B所示，第一复位控制信号和第二复位控制信号为同一个信号，从而可以不设置第一复位控制信号线RS1或第二复位控制信号线RS2。也就是说，当仅设置第一复位控制信号线RS1时，第一复位晶体管N2的栅极和第二复位晶体管N3的栅极可以均电连 接至第一复位控制信号线RS1；当仅设置第二复位控制信号线RS2时，第一复位晶体管N2的栅极和第二复位晶体管N3的栅极以均电连接至第二复位控制信号线RS2。
例如，如图2A所示，第一参考电平信号和第二参考电平信号可以不相同，但本公开的实施例不限于此，如图2B所示，在另一些实施例中，第一参考电平信号和第二参考电平信号可以相同。当第一参考电平信号和第二参考电平信号相同时，可以仅设置第一参考电平信号端Vcom1或第二参考电平信号端Vcom2。也就是说，当仅设置第一参考电平信号端Vcom1时，第一复位晶体管N2的第一极和第二复位晶体管N3的第一极可以均电连接至第一参考电平信号端Vcom1；当仅设置第二参考电平信号端Vcom2时，第一复位晶体管N2的第一极和第二复位晶体管N3的第一极可以均电连接至第二参考电平信号端Vcom2。
例如，第一参考电平信号和第二参考电平信号可以均设置为0V。
例如，如图2A所示，发光控制子电路150包括发光控制晶体管P2。发光控制晶体管P2的栅极被配置为接收发光控制信号，发光控制晶体管P2的第一极与第一电平信号端Vdd电连接，发光控制晶体管P2的第二极与驱动子电路100电连接，例如，发光控制晶体管P2的栅极与发光控制信号线EM连接以接收发光控制信号，发光控制晶体管P2的第二极与驱动晶体管DTFT的第一极电连接。
下面结合图2、图3A、图3B和图3C中所提供的信号时序图对本公开的像素电路的工作原理进行详细的描述。当包括所述像素电路的显示面板工作在需要高对比度、高亮度的第一工作模式时，像素电路的一个工作周期包括复位阶段T1、充电阶段T2、跳变阶段T3和发光阶段T4。
需要说明的是，在下面对本公开的描述中，以第一复位控制信号和第二复位控制信号为同一个信号，且第一参考电平信号和第二参考电平信号均设置为0V为例。图3A和3B所示的示例中，驱动晶体管DTFT为N型晶体管，而在图3C所示的示例中，驱动晶体管DTFT为P型晶体管。
例如，如图3A和图3B所示，当驱动晶体管DTFT为N型晶体管时，像素电路的工作原理如下。
在复位阶段T1，通过第一复位控制信号线RS1向复位子电路130的第一控制端提供第一复位控制信号，以将复位子电路130的输入端和该复位子电路 130的第一输出端导通，进而将第一参考电平信号端Vcom1提供的第一参考电平信号写入存储子电路140的第二端，从而实现对存储子电路140的第二端进行复位，以利于后续阶段中第二数据电压的写入。并且，在此复位阶段T1，通过第二复位控制信号线RS2向复位子电路130的第二控制端提供第二复位控制信号，将复位子电路130的输入端与该复位子电路130的第二输出端导通，从而可以将第二参考电平信号端Vcom2提供的第二参考电平信号写入发光元件OLED的阳极，实现对发光元件OLED阳极的复位。
在充电阶段T2，通过第一子栅线G1和第二子栅线G2向第一数据写入子电路110的控制端提供第一子数据扫描信号和第二子数据扫描信号，通过第一数据线D1向第一数据写入子电路110的输入端提供第一数据电压，以将第一数据写入子电路110的输入端与该第一数据写入子电路110的输出端导通，从而将第一数据电压写入存储子电路140的第一端中，并使得驱动晶体管DTFT的栅极电压达到第一电压V1。
例如，在图3A所示的示例中，在充电阶段T2，第一子栅线G1提供的第一子数据扫描信号处于高电平，第二子栅线G2提供的第二子数据扫描信号处于低电平，从而第一数据写入子电路110中的N型数据写入晶体管和P型数据写入晶体管均导通。但本公开的实施例不限于此，在一些示例中，在充电阶段T2，N型数据写入晶体管和P型数据写入晶体管其中之一导通，另一个截止。例如，当第一数据电压为正电压时，N型数据写入晶体管可以导通，P型数据写入晶体管可以截止；当第一数据电压为负电压时，N型数据写入晶体管可以截止，P型数据写入晶体管可以导通。
在电压跳变阶段T3，通过第二栅线G3向第二数据写入子电路120的控制端提供第二数据扫描信号，以使得第二数据写入子电路120的输入端和输出端导通，从而将通过第二数据写入子电路120的输入端写入的第二数据电压存储至存储子电路140的第二端中。在电压跳变阶段T3，由于存储电容C的自举效应，当存储子电路140的第二端(即存储电容C的第二端)的电压由充电阶段T2中的第一参考电平信号，即0V，跳变至电压跳变阶段T3的第二数据电压时，存储子电路140的第一端，即驱动晶体管DTFT的栅极电压(由充电阶段T2中的第一电压V1跳变至电压跳变阶段T3的第二电压V2。由于晶体管的电压阈值为固定阈值(即，晶体管的三个电极中，任意两个电极之间的电压差都不超过上述固定阈值，例如6V)，因此，其余晶体管的控制信号也应随之 跳变，从而保证各个晶体管正常工作。具体地，通过第一子栅线G1向第一数据写入子电路的控制端提供第一子数据扫描信号的电平高于在充电阶段T2中的第一子数据扫描信号的电平，通过第二子栅线G2向第一数据写入子电路的控制端提供第二子数据扫描信号的电平高于在充电阶段T2中的第二子数据扫描信号的电平，从而可以确保第一数据写入子电路的晶体管工作在电压阈值允许的范围内。
例如，如图3A和图3B所示，在复位阶段T1，第一子数据扫描信号的电平为第一数据电平，第二子数据扫描信号的电平为第二数据电平，第一复位控制信号和第二复位控制信号的电平为第一复位电平；在充电阶段T2，第一子数据扫描信号的电平为第三数据电平，第二子数据扫描信号的电平为第四数据电平，第一复位控制信号和第二复位控制信号的电平为第二复位电平；在电压跳变阶段T3，第一子数据扫描信号的电平为第五数据电平，第二子数据扫描信号的电平为第六数据电平，第一复位控制信号和第二复位控制信号的电平为第三复位电平。第一数据电平小于第三数据电平，第三数据电平小于第五数据电平，第二数据电平大于第四数据电平，第六数据电平大于第二数据电平，第一复位电平大于第二复位电平，第一复位电平等于第三复位电平。也就是说，在电压跳变阶段T3，第一子数据扫描信号的电平发生跳变，从第一数据电平跳变为第五数据电平，第二子数据扫描信号的电平发生跳变，从第二数据电平跳变为第六数据电平，第一复位控制信号和第二复位控制信号的电平从第二复位电平跳变为第三复位电平。
在发光阶段T4，由于驱动晶体管DTFT的栅极电压为上述第二电压V2，因此，通过发光控制信号线EM向发光控制子电路150提供发光控制信号，可以使得第一电平信号端Vdd、驱动晶体管DTFT的第一极、驱动晶体管DTFT的第二极、发光二极管OLED以及第二电平信号端Vss形成通路，以驱动发光元件OLED发光。
例如，如图3A和3B所示，在一些示例中，在复位阶段T1和在充电阶段T2，发光控制信号的电平均为第一发光控制电平；在电压跳变阶段T3，发光控制信号的电平为第二发光控制电平；在发光阶段T4，发光控制信号的电平为第三发光控制电平。第一发光控制电平小于第二发光控制电平，第一发光控制电平等于第三发光控制电平，也就是说，在电压跳变阶段T3，发光控制信号的电平发生跳变，从第一发光控制电平跳变为第二发光控制电平；在发光阶 段T4，发光控制信号的电平也发生变化，从第二发光控制电平变为第三发光控制电平。
例如，如图3A所示，在一些示例中，在发光阶段T4，第一子数据扫描信号的电平为第七数据电平，第七数据电平小于第五数据电平，第七数据电平可以等于第三数据电平，也就是说，第一子数据扫描信号的电平发生跳变，从第五数据电平跳变为第三数据电平；第二子数据扫描信号的电平保持为第六数据电平，第一复位控制信号和第二复位控制信号的电平也保持为第三复位电平，即第一复位控制信号的电平和第二子数据扫描信号的电平均没有发生跳变。
又例如，如图3B所示，在另一些示例中，在发光阶段T4，第一子数据扫描信号的电平保持为第五数据电平；第二子数据扫描信号的电平保持为第六数据电平，第一复位控制信号和第二复位控制信号的电平也保持为第三复位电平，即第一复位控制信号和第二复位控制信号的电平、第一子数据扫描信号的电平和第二子数据扫描信号的电平均没有发生跳变。
例如，如图3C所示，当驱动晶体管DTFT为P型晶体管时，像素电路的工作原理与驱动晶体管DTFT为P型晶体管时相类似，不同之处在于各个控制信号的电平不同。
例如，在复位阶段T1，第一子数据扫描信号的电平为第一数据电平，第二子数据扫描信号的电平为第二数据电平，第一复位控制信号和第二复位控制信号的电平为第一复位电平，发光控制信号的电平均为第一发光控制电平；在充电阶段T2，第一子数据扫描信号的电平为第三数据电平，第二子数据扫描信号的电平为第四数据电平，第一复位控制信号和第二复位控制信号的电平为第二复位电平，发光控制信号的电平均为第一发光控制电平；在电压跳变阶段T3，第一子数据扫描信号的电平为第五数据电平，第二子数据扫描信号的电平为第六数据电平，第一复位控制信号和第二复位控制信号的电平为第三复位电平，发光控制信号的电平为第二发光控制电平；在发光阶段T4，第一子数据扫描信号的电平为第五数据电平，第二子数据扫描信号的电平为第六数据电平，第一复位控制信号和第二复位控制信号的电平为第三复位电平，发光控制信号的电平为第三发光控制电平。
例如，第一数据电平小于第三数据电平，第五数据电平小于第一数据电平，第二数据电平大于第四数据电平，第四数据电平大于第六数据电平，第一复位电平大于第二复位电平，第二复位电平大于第三复位电平，第一发光控制电平 大于第二发光控制电平，第二发光控制电平大于第三发光控制电平。也就是说，在电压跳变阶段T3，第一子数据扫描信号的电平发生跳变，从第一数据电平跳变为第五数据电平，第二子数据扫描信号的电平发生跳变，从第二数据电平跳变为第六数据电平，第一复位控制信号和第二复位控制信号的电平发生跳变，从第二复位电平跳变为第三复位电平，发光控制信号的电平发生跳变，从第一发光控制电平跳变为第二发光控制电平。在发光阶段T4，第三发光控制电平小于第二发光控制电平，以保证发光控制晶体管P2在发光阶段T4导通。
例如，在复位阶段T1、充电阶段T2和发光阶段T4，第二数据扫描信号处于第二电平；在电压跳变阶段T3，第二数据扫描信号处于第一电平。在图3A-3C所示的示例中，第二电平为高电平，第一电平为低电平。
根据硅基的驱动晶体管DTFT的栅极电压、驱动晶体管DTFT的阈值电压以及发光元件OLED的阳极和阴极之间的压差VEL之间的关系可以计算出发光元件OLED的阳极和阴极之间的压差V EL。
例如，当驱动晶体管DTFT的栅极电压在1V～5V之间，驱动晶体管DTFT的阈值电压为1V，第二电平信号端Vss提供的电压为-3V时，则发光元件OLED的阴极的电压为-3V，驱动晶体管DTFT的源极电压在0V～4V之间，即发光元件OLED的阳极的电压在0V～4V之间，从而得出发光元件OLED的阳极和阴极之间的压差V EL为3V～7V，通过图4B可知，发光元件OLED工作在可以实现低亮度和高对比度的模式二。
需要指出的是，在显示装置需要高亮度显示时，在电压跳变阶段T3向第二数据写入子电路120的控制端提供第二数据扫描信号，并向第二数据写入子电路120的输入端提供第二数据电压，该第二数据电压可以高于第一数据电压。此时，驱动晶体管DTFT的栅极电压可以在5V～9V之间，从而驱动晶体管DTFT的源极电压在4V～8V之间，即发光元件OLED的阳极的电压在4V～8V之间，从而得出发光元件OLED的阳极和阴极之间的压差V EL为7V～11V，发光元件OLED工作在可以实现高亮度和高对比度的模式一。
在本公开中，对第一数据写入子电路110的具体结构并不做特殊的限制，在一种实施方式中，第一数据写入子电路110的控制端包括N型控制端(即第一子控制端)和P型控制端(即第二子控制端)，相应地，所述第一数据扫描信号包括第一N型数据扫描信号和第一P型数据扫描信号。在充电阶段T2，向第一数据写入子电路110的N型控制端提供第一N型数据扫描信号，并向 第一数据写入子电路110的P型控制端提供第一P型数据扫描信号。
例如，如图2B所示，第一数据写入子电路110包括N型数据写入晶体管N1和P型数据写入晶体管P1，N型数据写入晶体管N1的第一极与P型晶体管P1的第一极电连接，以形成为第一数据写入子电路110的输入端，N型数据写入晶体管N1的第二极与P型数据写入晶体管P1的第二极电连接，以形成为第一数据写入子电路110的输出端。N型数据写入晶体管N1的栅极形成为所述N型控制端，P型数据写入晶体管P1的栅极形成为所述P型控制端。由此可知，N型数据写入晶体管N1和P型数据写入晶体管P1形成传输门。
N型数据写入晶体管N1的第一极和N型数据写入晶体管N1的第二极能够在该N型数据写入晶体管N1的栅极接收到第一N型数据扫描信号时导通，N型数据写入晶体管N1的第一极和N型数据写入晶体管N1的第二极能够在该N型数据写入晶体管N1的栅极接收到第三N型数据扫描信号时断开。第一子数据扫描信号包括第一N型数据扫描信号和第三N型数据扫描信号，且第一N型数据扫描信号为高电平信号，第三N型数据扫描信号为低电平信号。
P型数据写入晶体管P1的第一极和P型数据写入晶体管P1的第二极能够在该P型数据写入晶体管P1的栅极接收到第一P型数据扫描信号时导通，P型数据写入晶体管P1的第一极和P型数据写入晶体管P1的第二极能够在该P型数据写入晶体管P1的栅极接收到第三P型数据扫描信号时断开。第二子数据扫描信号包括第一P型数据扫描信号和第三P型数据扫描信号，且第一P型数据扫描信号为低电平信号，第三P型数据扫描信号为高电平信号。
第一数据写入子电路110形成为包括P型数据写入晶体管和N型数据写入晶体管的传输门的形式，可以提高该第一数据写入子电路110允许输入的数据电压的范围，具体地，N型数据写入晶体管N1可以允许输入电压值较高的数据电压，P型数据写入晶体管P1可以允许输入电压值较低的数据电压。
在本公开中，对复位子电路130的具体结构不做特殊的限制，在图2B中所示的具体实施方式中，复位子电路130包括第一复位晶体管N2和第二复位晶体管N3，且第一复位晶体管N2为N型晶体管。第一复位晶体管N2的栅极和第二复位晶体管N3的栅极均接收第一复位控制信号，即第一复位晶体管N2和第二复位晶体管N3由同一个第一复位控制信号控制。
如图2B所示，第一复位晶体管N2的栅极形成为复位子电路130的控制端，第一复位晶体管N2的第一极形成为复位子电路130的输入端，第一复位 晶体管N2的第二极形成为复位子电路130的第一输出端，第一复位晶体管N2的第一极和第一复位晶体管N2的第二极能够在第一复位晶体管N2的栅极接收到第一子复位控制信号时导通，且第一复位晶体管N2的第一极和第一复位晶体管N2的第二极能够在接收到第二子复位控制信号时断开，第一复位控制信号包括第一子复位控制信号和第二子复位控制信号，且所述第一子复位控制信号和所述第二子复位控制信号相位相反。第一复位晶体管N2的第一极与第一参考电平信号端Vcom1电连接，因此，利用第一复位晶体管N2可以实现对存储子电路130第二端的复位。
第二复位晶体管N3的栅极与第一复位晶体管N2的栅极电连接，第二复位晶体管N3的第一极与第一复位晶体管N2的第一极电连接，第二复位晶体管N3的第二极形成为复位子电路130的第二输出端，第二复位晶体管N3的第一极和第二复位晶体管N3的第二极能够在该第二复位晶体管N3的栅极接收到第一子复位控制信号时导通，并且第二复位晶体管N3的第一极和第二复位晶体管N3的第二极能够在该第二复位晶体管N3的栅极接收到第二子复位控制信号时断开。
第二复位晶体管N3的第一极与第一参考电平信号端Vcom1电连接，因此，利用第二复位晶体管N3可以对发光元件OLED的阳极进行复位。
在本公开中，对第二复位晶体管N3的类型不做特殊限定，例如，在图2B中所示的具体实施方式中，第二复位晶体管N3为N型晶体管。
在本公开中，对第二数据写入子电路120的具体结构并不做特殊的限定，例如，如图2B所示，第二数据写入子电路120包括第一数据写入晶体管P3，该第一数据写入晶体管P3的栅极形成为第二数据写入子电路120的控制端，第一二数据写入晶体管P3的第一极形成为第二数据写入子电路120的输入端，第一数据写入晶体管P3的第二极形成为第二数据写入子电路120的输出端。
第一数据写入晶体管P3的第一极和第一数据写入晶体管P3的第二极能够在该第一数据写入晶体管P3的栅极接收到第三子数据扫描信号时导通，且第一数据写入晶体管P3的第一极和第一数据写入晶体管P3的第二极能够在该第一数据写入晶体管P3的栅极接收到第四子数据扫描信号时导通，例如，第二数据扫描信号包括第三子数据扫描信号和第四子数据扫描信号，且第三子数据扫描信号和第四子数据扫描信号相位相反。
例如，第三子数据扫描信号为第二数据扫描信号处于第一电平时的信号， 第四子数据扫描信号为第二数据扫描信号处于第二电平时的信号。
例如，如图2B所示，第一数据写入晶体管P3为P型晶体管，此时，第三子数据扫描信号为低电平信号，第四子数据扫描信号为高电平信号。当然，本公开并不限于此，例如，也可以将第一数据写入晶体管P3设置为N型晶体管。
在本公开中，对发光控制子电路150的具体结构并不做特殊限制，为了简化发光控制子电路150的结构，例如，发光控制子电路150包括发光控制晶体管P2。
例如，发光控制晶体管P2的栅极形成为发光控制子电路150的控制端，发光控制晶体管P2的第一极与第一电平信号端Vdd电连接，发光控制晶体管P2的第二极与驱动晶体管DTFT的第一极电连接。
发光控制晶体管P2的第一极和发光控制晶体管P2的第二极能够在该发光控制晶体管P2的栅极接收到第一子发光控制信号时导通，且发光控制晶体管P2的第一极和发光控制晶体管P2的第二极能够在该发光控制晶体管P2的栅极接收到第二子发光控制信号时断开。例如，发光控制信号包括第一子发光控制信号与第二子发光控制信号，且所述第一子发光控制信号与所述第二子发光控制信号相位相反。
在本公开中，对发光控制晶体管P2的具体类型也不做特殊的要求，在图2B中所示的具体实施方式中，发光控制晶体管P2为P型晶体管，第一子发光控制信号为低电平信号，第二子发光控制信号为高电平信号。作为另一种实施方式，发光控制晶体管可以为N型晶体管，相应地，第一子发光控制信号为高电平信号，第二子发光控制信号为低电平信号。
在本公开中，对存储子电路140的具体结构也没有特殊的要求，只要能够存储通过第一数据写入子电路110写入的第一数据电压以及通过第二数据写入子电路120写入的第二数据电压，并能在通过第二数据写入子电路120写入的第二数据电压时控制存储子电路140的第一端的电压即可。在图2B中所示的具体实施方式中，存储子电路140包括存储电容C，该存储电容C的第一端形成为存储子电路140的第一端，存储电容C的第二端形成为存储子电路140的第二端。
在图2B中所示的具体实施方式中，第一数据写入子电路110包括N型数据写入晶体管N1和P型数据写入晶体管P1，第二数据写入子电路120包括第一数据写入晶体管P3，复位子电路130包括第一复位晶体管N2和第二复位晶 体管N3，存储子电路140包括存储电容C，发光控制子电路150包括发光控制晶体管P2。例如，在图2B所示的示例中，N型数据写入晶体管N1、第一复位晶体管N2和第二复位晶体管N3均为N型晶体管，P型数据写入晶体管P1、发光控制晶体管P2、第一数据写入晶体管P3均为P型晶体管。
N型数据写入晶体管N1的栅极与第一N型栅线G1电连接，P型数据写入晶体管P1的栅极与第一P型栅线G2电连接，第一复位晶体管N2的栅极与第一复位控制信号线RS1电连接，第二复位晶体管N3的栅极与第一复位控制信号线RS1电连接，第一数据写入晶体管P3的栅极与第二栅线G3电连接，发光控制晶体管P2的栅极与发光控制信号线EM电连接。第一数据写入子电路110的输入端与第一数据线D1电连接，第二数据写入子电路120的输入端与第二数据线D2电连接。
如图3A所示，在复位阶段T1，第一N型栅线G1提供低电平的第三N型数据扫描信号，第一P型栅线G2提供高电平的第三P型数据扫描信号，第一复位控制信号线RS1提供高电平的第一子复位控制信号，发光控制信号线EM提供高电平的第一子发光控制信号，第一数据线D1和第二数据线D2均无信号输入。在此复位阶段T1，不向第二栅线G3提供信号，或者向第二栅线G3提供高电平信号。相应地，在复位阶段T1，N型数据写入晶体管N1、P型数据写入晶体管P1均截止，第一数据写入晶体管P3和发光控制晶体管P2也截止，第一复位晶体管N2和第二复位晶体管N3导通，从而对存储电容C的第二端以及发光元件OLED的阳极进行复位。对存储电容C的第二端复位以及对发光元件OLED的阳极复位可以避免包括所述像素电路的显示装置在显示时出现动态模糊(motion blur)。
在充电阶段T2，向第一N型栅线G1提供高电平的第一N型数据扫描信号，向第一P型栅线G2提供低电平的第一P型数据扫描信号，向第一复位控制信号线RS1提供低电平的第二子复位控制信号，向发光控制信号线EM提供高电平的第一子发光控制信号，向第一数据线D1提供第一数据电压，不向第二数据线D2提供数据电压。在充电阶段T2，向第二栅线G3提供高电平信号。在充电阶段T2，N型数据写入晶体管N1、P型数据写入晶体管P1均导通，第一数据电压被写入存储电容C的第一端中。除此之外，第一数据写入晶体管P3、发光控制晶体管P2、第一复位晶体管N2和第二复位晶体管N3均截止，并且此时驱动晶体管DTFT的栅极电压为第一电压V1，即第一数据电压。
在电压跳变阶段T3，向第二栅线G3提供低电平信号的第四子数据扫描信号，控制第一数据写入晶体管P3导通，从而可以通过第二数据线D2将第二数据电压写入存储电容C的第二端。此时，由于存储电容C的自举效应，存储电容C的第一端，即驱动晶体管DTFT的栅极电压上升为第二电压V2，第二电压V2为第一数据电压和第二数据电压之和。由于所有晶体管均为硅基晶体管，为了确保N型数据写入晶体管N1的任意两极间的电压差在阈值电压范围内、P型数据写入晶体管P1的任意两极之间的电压差在阈值电压范围内，相应地，通过第一N型栅线G1写入的信号的电压以及通过第一P型栅线G2写入的信号的电压都应当高于充电阶段T2中的电压，如图3A中所示。
在发光阶段T4，向第一N型栅线G1提供低电平信号，向第一P型栅线G2提供高电平信号，确保N型数据写入晶体管N1和P型数据写入晶体管P2均处于截止状态。并且，向第二栅线G3提供高电平信号，确保第一数据写入晶体管P3截止。在发光阶段T4，驱动晶体管DTFT的栅极电压保持在第二电压V2，根据源跟随原理可知，驱动晶体管DTFT的源极(即，驱动晶体管DTFT的第二极)电压为V2-Vth，其中，Vth为驱动晶体管DTFT的阈值电压。在本公开中，由于第二电压V2具有较高的电压范围，因此，驱动晶体管DTFT的源极(即，发光元件OLED的阳极)也具有较高的电压范围，从而可以满足实现高对比度和高亮度显示模式的模式一。
上文中所述的是所述像素电路实现高对比度和高亮度模式的模式一的工作原理，下面简要介绍所述像素电路实现高对比度和低亮度显示模式的模式二时的工作原理。
在实现像素电路的模式一时，所述像素电路的工作周期可以只包括复位阶段T1、充电阶段T2和发光阶段T4，而不包括电压跳变阶段T3。当然，本公开并不限于此，所述像素电路的工作周期也可以包括电压跳变阶段T3，不同之处在于，在电压跳变阶段T3，通过第二数据线D2提供0V的电压。因此，在电压跳变阶段T3，第一N型栅线G1的电压保持充电阶段T2的电压，第一P型栅线G2的电压保持充电阶段T2的电压，驱动晶体管DTFT的栅极电压仍然为第一数据电压V1，驱动晶体管DTFT的源极电压为V1-Vth。由于第一电压V1低于第二电压V2，因此，驱动晶体管DTFT的源极电压也低于V2-Vth，从而可以确保发光元件OLED的阳极和阴极之间的压差较小，满足低亮度的模式二。
本公开的至少一些实施例还提供一种显示面板，图5为本公开一些实施例提供的一种显示面板的示意图。
例如，如图5所示，所述显示面板50包括多个像素单元500，每个像素单元500内均设置有像素电路501，例如，所述像素电路501为本公开上述任一实施例提供的像素电路10，每个像素单元500内还包括发光元件502，发光元件502为上面任一实施例描述的发光元件OLED，像素电路501用于驱动发光元件502发光。
例如，所述多个像素单元500排列为多行多列，多个像素单元500的多行像素单元分别与多个栅线组一一对应，多个像素单元500的多列像素单元分别与多列数据线组一一对应。
如图1B、图2A和图5所示，多个栅线组中的每个栅线组包括第一栅线、第二栅线G3，第一栅线被配置为提供第一数据扫描信号，第二栅线G3被配置为提供第二数据扫描信号。每个栅线组还包括第一复位控制信号线RS1、第二复位控制信号线RS2和发光控制信号线EM。在同一行像素单元中，每个所述像素单元500的第一数据写入子电路110的控制端与所述第一栅线电连接以接收第一数据扫描信号，每个所述像素单元500的第二数据写入子电路120的控制端与第二栅线G3电连接以接收第二数据扫描信号，每个所述像素单元500的复位子电路的控制端与第一复位控制信号线RS1、第二复位控制信号线RS2电连接，每个所述像素单元500的发光控制子电路150的控制端与发光控制信号线EM电连接。
所述多个数据线组中的每个数据线组包括第一数据线D1和第二数据线D2，第一数据线D1被配置为提供第一数据电压，第二数据线D2被配置为提供第二数据电压。在同一列像素单元中，每个所述像素单元500的第一数据写入子电路110的输入端与第一数据线D1电连接以接收第一数据电压，每个所述像素单元500的第二数据写入子电路120的输入端与第二数据线D2电连接以接收第二数据电压。
例如，所述第一数据写入子电路110的控制端包括N型控制端(即第一子控制端)和P型控制端(即第二子控制端)，所述第一数据扫描信号包括第一N型数据扫描信号和第一P型数据扫描信号。
并且，所述第一数据写入子电路110包括N型数据写入晶体管N1和P型数据写入晶体管N2，相应地，所述第一栅线包括第一子栅线G1(即第一N型 栅线G1)和第二子栅线G2(即第一P型栅线G2)，在同一行像素单元中，每个所述像素单元的N型控制端与第一N型栅线G1电连接，所述像素单元的P型控制端与第一P型栅线G2电连接。
本公开的至少一些实施例还提供一种显示装置，图6为本公开一些实施例提供的一种显示装置的示意图。
例如，如图6所示，所述显示装置60包括显示面板600和光敏元件603，例如，所述显示面板600为本公开所提供的上述显示面板50，所述光敏元件603用于检测所述显示装置60所处的环境的亮度，并在环境的亮度高于或等于预设亮度时生成第一触发信号以控制显示装置60处于第一工作模式，在所述环境的亮度低于预设亮度时生成第二触发信号以控制显示装置60处于第二工作模式。
例如，显示装置60在第一工作模式下的显示亮度大于显示装置60在第二工作模式下的显示亮度。第一工作模式为上面图4A和图4B中描述的模式一，第二工作模式为上面图4A和图4B中描述的模式二。
例如，如图6所示，显示装置60还包括数据驱动器601。数据驱动器601被配置为通过第一数据线D1和第二数据线D2与显示面板600中的像素电路电连接，且通过第一数据线D1向显示面板600中的像素电路提供第一数据电压，通过第二数据线D2与向显示面板600中像素电路提供第二数据电压。
需要说明的是，当显示装置60处于第一工作模式时，在充电阶段，数据驱动器601通过第一数据线D1向显示面板600中的像素电路提供第一数据电压；在电压跳变阶段，数据驱动器601通过第二数据线D2与向显示面板600中像素电路提供第二数据电压。而当显示装置60处于第二工作模式时，则数据驱动器601可以仅在充电阶段通过第一数据线D1向显示面板600中的像素电路提供第一数据电压。
例如，如图6所示，显示装置60还包括栅极驱动器602。栅极驱动器602被配置为向显示面板600中的像素电路提供第一数据扫描信号和第二数据扫描信号。例如，当显示装置60处于第一工作模式时，在电压跳变阶段，第一数据扫描信号的电平和第二数据扫描信号的电平均发生跳变，图3A-3C示出了第一数据扫描信号和第二数据扫描信号的几种示意性波形。
本公开的至少一些实施例还提供一种显示装置的驱动方法，该驱动方法可以驱动本公开提供的任意一种显示装置。图7为本公开一些实施例提供的一种 显示装置的驱动方法的示意性流程图。
例如，在一些实施例中，当所述光敏元件生成所述第一触发信号时，如图3A-3B所示，所述显示面板的工作周期包括复位阶段T1、充电阶段T2、电压跳变阶段T3和发光阶段T4，如图7所示，驱动方法包括：
S10：在充电阶段，控制第一数据写入子电路向存储子电路的第一端写入第一数据电压；
S11：在电压跳变阶段，控制第二数据写入子电路向存储子电路的第二端写入第二数据电压，以控制存储子电路的第一端的电压，其中，在充电阶段中存储子电路的第一端的电压与在电压跳变阶段中所述存储子电路的第一端的电压不相同；
S12：在发光阶段，驱动子电路基于存储子电路的第一端的电压驱动发光元件发光。
例如，在步骤S11中，当驱动晶体管为N型晶体管时，在充电阶段中存储子电路的第一端的电压小于在电压跳变阶段中存储子电路的第一端的电压；当驱动晶体管为P型晶体管时，在充电阶段中存储子电路的第一端的电压大于在电压跳变阶段中存储子电路的第一端的电压。
例如，驱动方法还包括：在复位阶段，通过复位子电路向存储子电路的第二端写入第一参考电平信号以对存储子电路的第二端进行复位，通过复位子电路向发光元件的阳极写入第一参考电平信号以对发光元件的阳极进行复位。
例如，在一些实施例中，显示装置还可以包括驱动电路，驱动电路被配置为执行上述驱动方法中的各个步骤。例如，驱动电路用于：
在复位阶段T1，向所有第一复位控制信号线和所有第二复位控制信号线提供第一子复位控制信号，向所有第一栅线提供第三N型数据扫描信号和第三P型数据扫描信号，向所有第二栅线提供第四子数据扫描信号，向所有发光控制信号线提供第二子发光控制信号；
在充电阶段T2，向所有第一复位控制信号线和所有第二复位控制信号线提供第二子复位控制信号，按照预定扫描顺序依次向各条第一栅线提供第一N型数据扫描信号和第一P型数据扫描信号，向所有第二栅线提供第四子数据扫描信号，向所有发光控制信号线提供第二子发光控制信号，向第一数据线提供第一数据电压；
在电压跳变阶段T3，向所有第一复位控制信号线和所有第二复位控制信 号线提供第二子复位控制信号，向所有第一栅线提供第五N型数据扫描信号和第五P型数据扫描信号，按照所述预定扫描顺序依次向各条第二栅线提供第三子数据扫描信号，向所有发光控制信号线提供第二子发光控制信号，向第二数据线提供第二数据电压，所述第二数据电压比所述第一数据电压高预设值，例如，第一子数据扫描信号还可以包括第五N型数据扫描信号，第二子数据扫描信号还可以包括第五P型数据扫描信号，如图3A和图3B所示，第五N型数据扫描信号的电压高于第一N型数据扫描信号的电压，也高于第三N型数据扫描信号的电压，第五P型数据扫描信号的电压高于第一P型数据扫描信号的电压，也高于第三P型数据扫描信号的电压；
在发光阶段T4，向所有第一复位控制信号线和所有第二复位控制信号线提供第二子复位控制信号，向所有第一栅线提供第三N型数据扫描信号和第三P型数据扫描信号，向所有第二栅线提供第四子数据扫描信号，向所有发光控制信号线提供第一子发光控制信号。
需要说明的是，在发光阶段T4，驱动电路也可以向所有第一栅线提供第五N型数据扫描信号和第五P型数据扫描信号。
上文中已经对所述像素电路的工作原理和有益效果进行了详细的描述，这里不再赘述。
在本公开中，对所述“预设值”不做特殊限制，例如，对于一种发光二极管而言，实现高对比度(例如，20000:1)和高亮度(＞1500nit)的数据电压范围为5V至9V，而实现高对比度(例如，20000:1)和低亮度(375nit)的数据电压范围为1V至5V。那么，在本公开中，所述预设值则为3V。
需要指出的是，在另一些实施例中，当所述光敏元件生成第二触发信号时，所述显示面板的工作周期包括复位阶段、充电阶段和发光阶段三个阶段。
例如，驱动方法包括：在充电阶段，控制第一数据写入子电路向存储子电路的第一端写入第一数据电压；在发光阶段，驱动子电路基于存储子电路的第一端的电压驱动发光元件发光。
或者，当所述光敏元件生成第二触发信号时，所述显示面板的工作周期也包括复位阶段、充电阶段、电压跳变阶段和发光控制阶段，不同之处在于，充电阶段和电压跳变阶段的信号相同，且在电压跳变阶段，第二数据电压为0V。
例如，在所述第一数据写入子电路的控制端包括N型控制端和P型控制端、所述第一数据写入子电路包括N型数据写入晶体管和P型数据写入晶体管的实 施方式中：
所述第一数据扫描信号包括向所述第一N型栅线提供的第一N型数据扫描信号、向所述第一P型栅线提供的第一P型数据扫描信号、向所述第一N型栅线提供的第三N型数据扫描信号和向所述第一P型栅线提供的第三P型数据扫描信号，所述第一N型数据扫描信号为高电平信号，所述第三N型数据扫描信号为低电平信号，所述第一P型数据扫描信号为低电平信号，所述第三P型数据扫描信号为高电平信号；
所述第一数据扫描信号还可以包括向所述第一N型栅线提供的第五N型数据扫描信号和向所述第一P型栅线提供的第五P型数据扫描信号，所述第五N型数据扫描信号高于所述第一N型数据扫描信号的电压，所述第五P型数据扫描信号的电压高于所述第一P型数据扫描信号的电压。例如，在一些示例中，第五N型数据扫描信号也高于所述第三N型数据扫描信号的电压，所述第五P型数据扫描信号的电压也高于所述第三P型数据扫描信号的电压。
在本公开中，对显示装置60的具体结构不做特殊的限制，例如，所述显示装置60可以是近眼设备(例如，VR眼镜)，从而可以根据周围环境更好地模拟虚拟场景，有利于提高使用者的体验。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (24)

  1. 一种像素电路，包括：驱动子电路、第一数据写入子电路、第二数据写入子电路和存储子电路，其中，
    所述第一数据写入子电路与所述存储子电路的第一端电连接，且被配置为在第一数据扫描信号的控制下导通时向所述存储子电路的第一端写入第一数据电压；
    所述第二数据写入子电路与所述存储子电路的第二端电连接，且被配置为在第二数据扫描信号的控制下导通时向所述存储子电路的第二端写入第二数据电压，以基于所述第二数据电压控制所述存储子电路的第一端的电压；
    所述存储子电路的第一端还与所述驱动子电路的控制端电连接；
    所述驱动子电路被配置在所述存储子电路的第一端的电压的控制下驱动发光元件发光。
  2. 根据权利要求1所述的像素电路，其中，所述第二数据写入子电路包括第一数据写入晶体管，
    所述第一数据写入晶体管的栅极被配置为接收所述第二数据扫描信号，所述第一数据写入晶体管的第一极被配置为接收所述第二数据电压，所述第一数据写入晶体管的第二极与所述存储子电路的第二端电连接。
  3. 根据权利要求2所述的像素电路，其中，在所述第二数据扫描信号处于第一电平时，所述第一数据写入晶体管导通，在所述第二数据扫描信号处于第二电平时，所述第一数据写入晶体管断开，所述第一电平和所述第二电平为彼此相反的电平。
  4. 根据权利要求2或3所述的像素电路，其中，所述第一数据写入晶体管为P型晶体管。
  5. 根据权利要求1-4任意一项所述的像素电路，其中，所述第一数据写入子电路的控制端被配置为接收所述第一数据扫描信号，
    所述第一数据写入子电路的控制端包括第一子控制端和第二子控制端，所述第一数据扫描信号包括第一子数据扫描信号和第二子数据扫描信号，所述第一子控制端被配置为接收所述第一子数据扫描信号，所述第二子控制端被配置为接收所述第二子数据扫描信号。
  6. 根据权利要求5所述的像素电路，其中，所述第一数据写入子电路包 括N型数据写入晶体管和P型数据写入晶体管，所述N型数据写入晶体管的第一极与所述P型数据写入晶体管的第一极均被配置为接收所述第一数据电压，所述N型数据写入晶体管的第二极与所述P型数据写入晶体管的第二极均与所述存储子电路的第一端电连接，所述第一子控制端包括所述N型数据写入晶体管的栅极，所述第二子控制端包括所述P型数据写入晶体管的栅极。
  7. 根据权利要求1-6任意一项所述的像素电路，还包括复位子电路，
    其中，所述复位子电路的第一输出端与所述存储子电路的第二端电连接，所述复位子电路的第二输出端与所述发光元件的阳极电连接，
    所述复位子电路被配置为在第一复位控制信号的控制下对所述存储子电路的第二端进行复位，在第二复位控制信号的控制下对所述发光元件的阳极进行复位。
  8. 根据权利要求7所述的像素电路，其中，所述复位子电路的输入端与第一参考电平信号端和第二参考电平信号端电连接，
    所述复位子电路被配置为在所述第一复位控制信号的控制下将所述第一参考电平信号端的第一参考电平信号写入所述存储子电路的第二端以对所述存储子电路的第二端进行复位，
    所述复位子电路还被配置为在所述第二复位控制信号的控制下将所述第二参考电平信号端的第二参考电平信号写入所述发光元件的阳极以对所述发光元件的阳极进行复位。
  9. 根据权利要求7或8所述的像素电路，其中，所述复位子电路包括第一复位晶体管和第二复位晶体管，
    所述复位子电路的输入端包括所述第一复位晶体管的第一极和所述第二复位晶体管的第一极，所述第一输出端包括所述第一复位晶体管的第二极，所述第二输出端包括所述第二复位晶体管的第二极，
    所述第一复位晶体管的栅极被配置为接收所述第一复位控制信号，所述第一复位晶体管的第一极被配置为与所述第一参考电平信号端电连接，所述第一复位晶体管的第二极与所述存储子电路的第二端电连接；
    所述第二复位晶体管的栅极被配置为接收所述第二复位控制信号，所述第二复位晶体管的第一极被配置为与所述第二参考电平信号端电连接，所述第二复位晶体管的第二极与所述发光元件的阳极电连接。
  10. 根据权利要求1-9任意一项所述的像素电路，还包括发光控制子电路， 其中，
    所述发光控制子电路被配置为在发光控制信号的控制下实现所述驱动子电路和所述发光元件之间的连接导通或断开。
  11. 根据权利要求10所述的像素电路，其中，所述发光控制子电路包括发光控制晶体管，
    所述发光控制晶体管的栅极被配置为接收所述发光控制信号，所述发光控制晶体管的第一极与第一电平信号端电连接，所述发光控制晶体管的第二极与所述驱动子电路电连接。
  12. 根据权利要求10或11所述的像素电路，其中，所述驱动子电路包括驱动晶体管，
    所述驱动晶体管的第一极与所述发光控制子电路电连接，所述驱动晶体管的第二极与所述发光元件的阳极电连接，所述驱动子电路的控制端包括所述驱动晶体管的栅极，所述驱动晶体管的栅极与所述存储子电路的第一端，
    所述发光元件的阴极与第二电平信号端电连接。
  13. 根据权利要求1-12中任意一项所述的像素电路，其中，所述存储子电路包括存储电容，
    所述存储子电路的第一端包括所述存储电容的第一端，所述存储子电路的第二端包括所述存储电容的第二端。
  14. 一种显示面板，包括权利要求1至13中任意一项所述的像素电路。
  15. 根据权利要求14所述的显示面板，还包括多个像素单元，
    其中，所述多个像素单元排列为多行多列，每个像素单元内均设置有所述像素电路。
  16. 根据权利要求15所述的显示面板，其中，所述多个像素单元的多行像素单元分别与多个栅线组一一对应，所述多个像素单元的多列像素单元分别与多列数据线组一一对应；
    所述多个栅线组中的每个包括第一栅线和第二栅线，所述第一栅线被配置为提供所述第一数据扫描信号，所述第二栅线被配置为提供所述第二数据扫描信号，
    在同一行像素单元中，每个所述像素单元的第一数据写入子电路与所述第一栅线电连接以接收所述第一数据扫描信号，每个所述像素单元的第二数据写入子电路与所述第二栅线电连接以接收所述第二数据扫描信号；
    所述多个数据线组中的每个包括第一数据线和第二数据线，所述第一数据线被配置为提供所述第一数据电压，所述第二数据线被配置为提供所述第二数据电压，
    在同一列像素单元中，每个所述像素单元的第一数据写入子电路与所述第一数据线电连接以接收所述第一数据电压，每个所述像素单元的第二数据写入子电路与所述第二数据线电连接以接收所述第二数据电压。
  17. 根据权利要求16所述的显示面板，其中，在所述第一数据写入子电路的控制端包括第一子控制端和第二子控制端的情况下；
    所述第一栅线包括第一子栅线和第二子栅线，在同一行像素单元中，每个所述像素单元的第一数据写入子电路的第一子控制端与所述第一子栅线电连接，每个所述像素单元的第一数据写入子电路的第二子控制端与所述第二子栅线电连接。
  18. 一种显示装置，包括根据权利要求14-16任一项所述的显示面板。
  19. 根据权利要求18所述的显示装置，还包括光敏元件，
    其中，所述光敏元件用于检测所述显示装置所处的环境的亮度，并在所述亮度高于或等于预设亮度时生成第一触发信号以控制所述显示装置处于第一工作模式，在所述亮度低于所述预设亮度时生成第二触发信号以控制所述显示装置的处于第二工作模式。
  20. 根据权利要求19所述的显示装置，其中，所述显示装置在所述第一工作模式下的显示亮度大于所述显示装置在所述第二工作模式下的显示亮度。
  21. 根据权利要求18-20任一项所述的显示装置，还包括数据驱动器，
    其中，所述数据驱动器被配置为通过第一数据线和第二数据线与所述显示面板中的像素电路电连接，且通过所述第一数据线向所述像素电路提供所述第一数据电压，通过所述第二数据线向所述像素电路提供所述第二数据电压。
  22. 根据权利要求18-21任一项所述的显示装置，还包括栅极驱动器，
    其中，所述栅极驱动器被配置为向所述显示面板中的像素电路提供所述第一数据扫描信号和所述第二数据扫描信号。
  23. 一种根据权利要求19或20所述的显示装置的驱动方法，其中，
    当所述光敏元件生成所述第一触发信号时，所述显示面板的工作周期包括充电阶段、电压跳变阶段和发光阶段，
    所述驱动方法包括：
    在所述充电阶段，控制所述第一数据写入子电路向所述存储子电路的第一端写入所述第一数据电压；
    在所述电压跳变阶段，控制所述第二数据写入子电路向所述存储子电路的第二端写入所述第二数据电压，以控制所述存储子电路的第一端的电压，其中，在所述充电阶段中所述存储子电路的第一端的电压与在所述电压跳变阶段中所述存储子电路的第一端的电压不相同；
    在所述发光阶段，所述驱动子电路基于所述存储子电路的第一端的电压驱动所述发光元件发光。
  24. 一种根据权利要求19或20所述的显示装置的驱动方法，其中，
    当所述光敏元件生成所述第二触发信号时，所述显示面板的工作周期包括充电阶段和发光阶段，
    所述驱动方法包括：
    在所述充电阶段，控制所述第一数据写入子电路向所述存储子电路的第一端写入所述第一数据电压；
    在所述发光阶段，所述驱动子电路基于所述存储子电路的第一端的电压驱动所述发光元件发光。
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