TW202109884A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW202109884A
TW202109884A TW109127879A TW109127879A TW202109884A TW 202109884 A TW202109884 A TW 202109884A TW 109127879 A TW109127879 A TW 109127879A TW 109127879 A TW109127879 A TW 109127879A TW 202109884 A TW202109884 A TW 202109884A
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Taiwan
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epitaxial
fin
epitaxial layer
region
layer
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TW109127879A
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林衍廷
宋學昌
李彥儒
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台灣積體電路製造股份有限公司
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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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Abstract

在一實施例中，半導體裝置包括：從基板延伸而出的鰭片；位於鰭片的通道區之上的閘極堆疊；以及位於鰭片中且鄰近於通道區的源極∕汲極區。源極∕汲極區包括接觸鰭片側壁的第一磊晶層與位於第一磊晶層上的第二磊晶層。第一磊晶層包括以摻質摻雜的矽與鍺，且第一磊晶層具有第一濃度的摻質。第二磊晶層包括以上述摻質摻雜的矽與鍺，且第二磊晶層具有第二濃度的摻質，第二濃度大於第一濃度。第一磊晶層與第二磊晶層具有相同的鍺濃度。

Description

半導體裝置
本發明實施例是關於一種半導體裝置及其製造方法，特別是關於一種鰭狀場效電晶體及其製造方法。
半導體裝置用於各式各樣的電子應用中，例如個人電腦、手機、數位相機與其他電子設備。半導體裝置的製造一般是透過於半導體基板上依序沉積絕緣或介電層、導電層以及半導體層的材料，並利用微影圖案化各種材料層以於半導體基板上形成電路組件與元件。
半導體產業藉由不斷地減少最小部件尺寸持續改良各種電子組件（例如，電晶體、二極體、電阻、電容等）的積集密度，而使得更多組件得以整合至一給定面積。然而，隨著最小部件尺寸減少，額外需解決的問題也隨之出現。
本發明實施例提供一種半導體裝置。半導體裝置包括：從基板延伸而出的鰭片；位於鰭片的通道區之上的閘極堆疊；以及位於鰭片中且鄰近於通道區的源極∕汲極區，源極∕汲極區包括：接觸鰭片側壁的第一磊晶層，第一磊晶層包括以摻質摻雜的矽與鍺，且第一磊晶層具有第一濃度的摻質；以及位於第一磊晶層上的第二磊晶層，第二磊晶層包括以上述摻質摻雜的矽與鍺，且第二磊晶層具有第二濃度的上述摻質，第二濃度大於第一濃度，且第一磊晶層與第二磊晶層具有相同的鍺濃度。
本發明實施例亦提供一種半導體裝置的製造方法。半導體裝置的製造方法包括：形成從基板延伸而出的鰭片；於鰭片的通道區之上形成閘極堆疊；在鄰近於通道區的鰭片中形成凹口；利用第一磊晶成長製程，沿著凹口的側壁與底部成長第一磊晶層，第一磊晶成長製程沿著凹口的側壁具有第一成長速率，且第一磊晶成長製程沿著凹口的底部具有第二成長速率，第二成長速率大於第一成長速率；以及利用第二磊晶成長製程，於凹口中的第一磊晶層上成長第二磊晶層，第二磊晶成長製程沿著凹口的側壁具有第三成長速率，且第二磊晶成長製程沿著凹口的底部具有第四成長速率，第三成長速率小於第一成長速率，且第四成長速率大於第二成長速率。
本發明實施例更提供一種半導體裝置的製造方法。半導體裝置的製造方法包括：形成從基板延伸而出的鰭片；於鰭片的通道區之上形成閘極堆疊；在鄰近於通道區的鰭片中形成凹口；利用第一磊晶成長製程，沿著凹口的側壁與底部成長第一磊晶層，第一磊晶成長製程是在第一溫度與第一壓力之下進行；以及利用第二磊晶成長製程，於凹口中的第一磊晶層上成長第二磊晶層，第二磊晶成長製程是在第二溫度與第二壓力之下進行，第一溫度小於第二溫度，且第一壓力大於第二壓力。
以下揭露提供了許多的實施例或範例，用於實施所提供的標的物之不同元件。各元件和其配置的具體範例描述如下，以簡化本發明實施例之說明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，敘述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接觸的實施例，也可能包含額外的元件形成在第一和第二元件之間，使得它們不直接接觸的實施例。此外，本發明實施例可能在各種範例中重複參考數值以及∕或字母。如此重複是為了簡明和清楚之目的，而非用以表示所討論的不同實施例及∕或配置之間的關係。
再者，其中可能用到與空間相對用詞，例如「在……下方」、「在……之下」、「下方的」、「在……之上」、「上方的」等類似用詞，是為了便於描述圖式中一個（些）部件或特徵與另一個（些）部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時（旋轉90度或其他方位），其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
根據一些實施例，具有多層磊晶層（epitaxial layer）的磊晶源極∕汲極區成長於半導體鰭片（fin）中。最底層磊晶層與剩餘的膜層相比，是在較低溫度及較高壓力之下成長於半導體鰭片的側壁上。最底層磊晶層可因此以較為順應的（conformal）輪廓而成長，使得在磊晶源極∕汲極區沒有受損的風險之下，可增加最底層磊晶層的鍺濃度。以較高的鍺濃度在半導體鰭片的側壁形成磊晶源極∕汲極區可增加所製得裝置（例如，電晶體）的性能。
第1圖是根據一些實施例，繪示出簡化的鰭狀場效電晶體（fin field-effect transistor, FinFET）之一範例的三維示意圖。為了使圖示清楚，省略了鰭狀場效電晶體的一些其他部件（以下討論）。所示鰭狀場效電晶體可以如一個電晶體或多個電晶體運作的方式而電性連接或耦接，多個電晶體如兩個電晶體。
鰭狀場效電晶體包括從基板50延伸而出的鰭片52。淺溝槽隔離（shallow trench isolation, STI）區56設置於基板50之上，且鰭片52從鄰近的淺溝槽隔離區56之間突出於淺溝槽隔離區56之上。雖然淺溝槽隔離區56被描述∕繪示為與基板50分離，在此使用的用語「基板」可單純指的是半導體基板或可指的是包括隔離區的半導體基板。此外，雖然鰭片52被繪示為基板50單一且連續的材料，鰭片52以及∕或基板50可包括單一材料或複數個材料。在此背景下，鰭片52指的是在鄰近的淺溝槽隔離區56之間延伸的部分。
閘極介電質106沿著鰭片52的側壁且位於鰭片52的頂表面之上，且閘極電極108位於閘極介電質106之上。源極∕汲極區80設置於鰭片52相對於閘極介電質106與閘極電極108之兩側。閘極間隔物（spacer）78隔離了源極∕汲極區80與閘極介電質106及閘極電極108。層間介電質（inter-layer dielectric, ILD）102設置於源極∕汲極區80與淺溝槽隔離區56之上。在形成多個電晶體的實施例中，各個電晶體可共用源極∕汲極區80。在由多個鰭片52所形成的一個電晶體的實施例中，鄰近的源極∕汲極區80可電性連接，例如利用磊晶成長連結（coalescing）源極∕汲極區80，或利用相同的源極∕汲極接觸件（contact）耦接源極∕汲極區80。
第1圖更繪示出數個參考剖面。剖面A-A係沿著閘極電極108的縱軸方向，且垂直於鰭狀場效電晶體的源極∕汲極區80之間的電流方向。剖面B-B垂直於剖面A-A且係沿著鰭片52的縱軸方向，且係沿著如鰭狀場效電晶體的源極∕汲極區80之間的電流方向。剖面C-C平行於剖面A-A且延伸穿過鰭狀場效電晶體的源極∕汲極區80。為了清楚起見，後續圖式將參照這些參考剖面。
在此討論的一些實施例是在利用閘極後製（gate-last）製程形成鰭狀場效電晶體的背景之下所討論。在其他實施例中，可使用閘極先製（gate-first）製程。此外，一些實施例也將用於如平面場效電晶體的平面裝置納入考量。
第2至15B圖是根據一些實施例，繪示出製造鰭狀場效電晶體的中間階段的各個示意圖。第2與3圖為三維示意圖。第4A、5A、11A、12A、13A、14A與15A是沿著第1圖中的參考剖面A-A所繪示的剖面圖，但未繪示多個鰭片∕鰭狀場效電晶體。第4B、5B、6、7、8、9、11B、12B、13B、14B、14C與15B是沿著第1圖中的參考剖面B-B所繪示的剖面圖，但未繪示多個鰭片∕鰭狀場效電晶體。
第2圖中，提供基板50。基板50可為半導體基板，例如塊狀（bulk）半導體、絕緣體上覆半導體（semiconductor-on-insulator, SOI）基板或類似基板，其可為摻雜（例如，利用p型或n型摻質（dopant）摻雜）或未摻雜的。基板50可為晶圓，例如矽晶圓。一般而言，絕緣體上覆半導體基板為形成於絕緣層上的一層半導體材料。例如，絕緣層可為埋入氧化（buried oxide, BOX）層或氧化矽等。絕緣層係提供於基板上，一般為矽或玻璃基板。也可使用其他基板，例如多層（multi-layered）或梯度（gradient）基板。在一些實施例中，基板50的半導體材料可包括矽；鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦以及∕或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP以及∕或GaInAsP；或前述之組合。例如，形成p型裝置時，基板50可為如矽鍺（Six Ge1-x ，其中x可介於0至1之間的範圍）的應變（strained）材料，其具有介於約0%至約40%之間的範圍的鍺濃度，而形成具有p型完全應變通道（p-type fully strained channel, PFSC）區的鰭狀場效電晶體。
基板50具有區域50N與區域50P。區域50N可用於形成如n型金屬氧化物半導體（metal-oxide-semiconductor, MOS）電晶體的n型裝置，n型金屬氧化物半導體電晶體如n型鰭狀場效電晶體。區域50P可用於形成如p型金屬氧化物半導體電晶體的p型裝置，p型金屬氧化物半導體電晶體如p型鰭狀場效電晶體。區域50N可與區域50P物理隔離，且任何數量的裝置部件（例如，其他主動元件、摻雜區、隔離結構等）可設置於區域50N與區域50P之間。
形成鰭片52從基板50延伸而出。鰭片52為半導體帶（strip）。在一些實施例中，可透過在基板50中蝕刻出溝槽而於基板50中形成鰭片52。蝕刻可為任何可接受的蝕刻製程，例如反應離子蝕刻（reactive ion etch, RIE）、中子束蝕刻（neutral beam etch, NBE）等或前述之組合。蝕刻可為非等向性的（anisotropic）。形成鰭片52之後，鰭片52具有寬度W1 ，且在相同的區域50N∕50P中的鰭片52以節距（pitch）P1 分離。寬度W1 可介於約3nm至約30nm之間的範圍。節距P1 可介於約20nm至約100nm之間的範圍。
可利用任何合適的方法圖案化鰭片。例如，可利用一或多種光學微影（photolithography）製程圖案化鰭片，光學微影製程包括雙重圖案化或多重圖案化製程。一般而言，雙重圖案化或多重圖案化製程結合光學微影與自對準（self-aligned）製程，產生具有如節距小於使用單一、直接的光學微影製程可獲得的節距之圖案。例如，在一實施例中，犧牲層形成於基板之上並利用光學微影製程圖案化。利用自對準製程在圖案化的犧牲層一旁形成間隔物。接著移除犧牲層，且剩餘的間隔物接著可用以圖案化鰭片。
淺溝槽隔離區56形成於基板50之上以及鄰近的鰭片52之間。作為形成淺溝槽隔離區56的一範例，絕緣材料形成於中間（intermediate）結構之上。絕緣材料可為如氧化矽的氧化物、氮化物等或前述之組合，且可利用高密度電漿化學氣相沉積（high density plasma chemical vapor deposition, HDP-CVD）、流動式化學氣相沉積（flowable CVD, FCVD，例如於遠程（remote）電漿系統中利用化學氣相沉積所沉積（CVD-based）的材料，並進行後固化（post curing）使其轉換成如氧化物的另一材料）等或前述之組合所形成。可使用由任何可接受的製程所形成的其他絕緣材料。在所示實施中，絕緣材料為利用流動式化學氣相沉積所形成的氧化矽。一旦形成絕緣材料後，可進行退火（anneal）製程。在一實施例中，形成絕緣材料使得過量的絕緣材料覆蓋鰭片52。一些實施例可使用多個膜層。例如，在一些實施例中，可先沿著基板50與鰭片52的表面形成襯層（未繪示）。接著，可於襯層之上形成如以上所討論的填充材料。對絕緣材料進行移除製程以移除鰭片52之上過多的絕緣材料。在一些實施例中，可使用平坦化製程如化學機械研磨（chemical mechanical polish, CMP）、回蝕刻（etch-back）製程等或前述之組合。平坦化製程露出了鰭片52，使得完成平坦化製程後，鰭片52與絕緣材料的頂表面齊平。接著，凹蝕絕緣材料，使絕緣材料的剩餘部分形成淺溝槽隔離區56。凹蝕絕緣材料使得區域50N與區域50P中鰭片52的上部分從鄰近的淺溝槽隔離區56間突出。凹蝕之後，鰭片52的露出部分延伸高度H1 於淺溝槽隔離區56的頂表面之上。高度H1 可大於約40nm，例如介於約50nm至約80nm之間的範圍。鰭片52的露出部分包括製得的鰭狀場效電晶體的通道區。
再者，淺溝槽隔離區56的頂表面可具有所示的平坦表面、凸（convex）表面、凹（concave）表面（如碟狀（dishing））或前述之組合。可利用適當的蝕刻方式形成淺溝槽隔離區56的頂表面，使其為平坦狀、凸狀以及∕或凹狀。可利用可接受的蝕刻製程凹蝕淺溝槽隔離區56，例如對絕緣材料具有選擇性的蝕刻製程（例如，相較於鰭片52的材料，以較快的速率蝕刻絕緣材料的材料）。例如，可使用合適的蝕刻製程進行化學氧化物移除的步驟，蝕刻製程使用如稀釋氫氟酸（diluted hydrofluoric, dHF）。
上述的製程僅是鰭片52可如何形成的一範例。在一些實施例中，可利用磊晶成長製程形成鰭片52。例如，介電層可形成於基板50的頂表面之上，且可蝕刻溝槽穿過介電層，以露出下方的基板50。可於溝槽中磊晶成長同質磊晶（homoepitaxial）結構，且可凹蝕介電層，使得同質磊晶結構從介電層突出而形成鰭片52。此外，在一些實施例中，異質磊晶（heteroepitaxial）結構可用於鰭片52。例如，在一同平坦化淺溝槽隔離區56的絕緣材料與鰭片52之後，可凹蝕鰭片52，且與鰭片52不同的材料可磊晶成長於凹蝕的鰭片52之上。在此些範例中，鰭片52包括凹蝕的材料以及設置於凹蝕的材料之上的磊晶成長材料。在更一實施例中，介電層可形成於基板50的頂表面之上，且可蝕刻溝槽穿過介電層。接著，可使用與基板50不同的材料於溝槽中磊晶成長異質磊晶結構，且可凹蝕介電層，使得異質磊晶結構從介電層突出而形成鰭片52。在磊晶成長同質磊晶或異質磊晶結構的一些實施例中，成長期間可於原位（in-situ）摻雜磊晶成長的材料，如此可不需要前佈植（implantation）與後續佈植步驟，儘管可一同使用原位與佈植摻雜。
再者，於區域50N（例如，n型金屬氧化物半導體區）中磊晶成長與區域50P（例如，p型金屬氧化物半導體區）不同的材料可能是有利的。在各種實施例中，可使用矽鍺（Six Ge1-x ，其中x可介於0至1之間的範圍）、碳化矽、純或實質上為純鍺、III-V族化合物半導體、II-VI族化合物半導體等形成鰭片52的上部分。例如，形成III-V族化合物半導體可使用的材料包括InAs、AlAs、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlP、GaP等，但並非以此為限。
再者，適當的井區（well，未繪示）可形成於鰭片52以及∕或基板50中。在一些實施例中，P井可形成於區域50N中，且N井可形成於區域50P中。在一些實施例中，P井或N井形成於區域50N與區域50P兩者中。
在不同井區型態的實施例中，可利用光阻或其他遮罩（未繪示）進行區域50N與區域50P的不同佈植步驟。例如，光阻可形成於區域50N中的鰭片52與淺溝槽隔離區56之上。圖案化光阻以露出基板50的區域50P，區域50P如p型金屬氧化物半導體區。可利用旋轉塗佈（spin-on）技術形成光阻，且可利用可接受的光學微影技術圖案化光阻。光阻一旦圖案化後，於區域50P中進行n型雜質（impurity）的摻雜，且光阻可作為遮罩以實質上防止n型雜質佈植至區域50N中，區域50N如n型金屬氧化物半導體區。n型雜質可為磷、砷、銻等，於區域中佈植至小於或等於1018 cm-3 的濃度，如約1017 cm-3 至約1018 cm-3 間。佈植後，利用如可接受的灰化（ashing）製程移除光阻。
佈植區域50P後，於區域50P中的鰭片52與淺溝槽隔離區56之上形成光阻。圖案化光阻以露出基板50的區域50N，區域50N如n型金屬氧化物半導體區。可利用旋轉塗佈技術形成光阻，且可利用可接受的光學微影技術圖案化光阻。光阻一旦圖案化後，於區域50N可進行p型雜質的摻雜，且光阻可作為遮罩以實質上防止p型雜質佈植至區域50P中，區域50P如p型金屬氧化物半導體區。p型雜質可為硼、BF2 或銦等，於區域中佈植至小於或等於1018 cm-3 的濃度，如約1017 cm-3 至約1018 cm-3 間。佈植後，可利用如可接受的灰化製程移除光阻。
佈植區域50N與50P之後，可進行退火以活化所佈植的p型以及∕或n型雜質。在一些實施例中，成長期間可於原位摻雜磊晶鰭片的成長材料，如此可不需要佈植步驟，儘管可一同使用原位與佈植摻雜。
第3圖中，虛置（dummy）閘極介電質70形成於鰭片52上，且虛置閘極72形成於虛置閘極介電質70之上。虛置閘極介電質70與虛置閘極72可共同稱為「虛置閘極堆疊」，每個虛置閘極堆疊包括虛置閘極介電質70與虛置閘極72。虛置閘極堆疊沿著鰭片52的側壁延伸。雖然僅繪示出一個虛置閘極堆疊，應能理解同時有多個虛置閘極堆疊形成，且每個鰭片52可具有多個虛置閘極堆疊形成於其上。
作為形成虛置閘極介電質70與虛置閘極72的一範例，虛置介電層形成於鰭片52上。虛置介電層可為如氧化矽、氮化矽等或前述之組合，且可根據可接受的技術沉積或熱成長虛置介電層。虛置閘極層形成於虛置介電層之上，且遮罩層形成於虛置閘極層之上。虛置閘極層可沉積於虛置介電層之上，且可利用如化學機械研磨的方式平坦化虛置閘極層。遮罩層可沉積於虛置閘極層之上。虛置閘極層可為導電或非導電材料，且可選自以下所組成之群組，包括：非晶矽（amorphous silicon）、多晶矽（polycrstalline-silicon, polysilicon）、多晶矽鍺、金屬氮化物、金屬矽化物、金屬氧化物與金屬。可利用物理氣相沉積（physical vapor deposition, PVD）、化學氣相沉積、濺射（sputter）沉積或本發明所屬技術領域中已知用於沉積導電材料的其他技術沉積虛置閘極層。虛置閘極層可由相對於隔離區具有高蝕刻選擇性的其他材料所形成。遮罩層可包括如氮化矽、氮氧化矽等。在此範例中，形成橫跨區域50N與區域50P的單一虛置閘極層與單一遮罩層。應注意的是，僅是為了說明的目的，虛置介電層被繪示為只有覆蓋鰭片52。在一些實施例中，可沉積虛置介電層使其覆蓋淺溝槽隔離區56，且在虛置閘極層與淺溝槽隔離區56之間延伸。接著，利用可接受的光學微影與蝕刻技術圖案化遮罩層以形成遮罩74。接著，利用可接受的蝕刻技術將遮罩74的圖案轉移至虛置閘極層，以形成虛置閘極72。遮罩74的圖案更轉移至虛置介電層，以形成虛置閘極介電質70。遮罩74的圖案可用以物理性隔離每個虛置閘極72與鄰近的虛置閘極。虛置閘極72也可具有縱向方向，其實質上垂直於個別的磊晶鰭片52的縱向方向。
第4A與4B圖中，閘極密封間隔物（seal spacer）76形成於虛置閘極72、遮罩74以及∕或鰭片52露出的表面上。熱氧化（thermal oxidation）或沉積之後進行非等向性蝕刻可形成閘極密封間隔物76。
形成閘極密封間隔物76之後，可進行輕摻雜源極∕汲極（lightly doped source/drain, LDD）區（未明確繪示）的佈植。在不同裝置型態的實施例中，與所討論的佈植相似，如光阻的遮罩可形成於區域50N之上而露出區域50P，且可佈植適當型態（例如， p型）的雜質至區域50P中露出的鰭片52之中。接著，可移除遮罩。之後，如光阻的遮罩可形成於區域50P之上而露出區域50N，且可佈植適當型態（例如， n型）的雜質至區域50N中露出的鰭片52之中。接著，可移除遮罩。n型雜質可為先前討論的任何n型雜質，且p型雜質可為先前討論的任何p型雜質。輕摻雜源極∕汲極區可具有約1015 cm-3 至約1016 cm-3 間的雜質濃度。可使用退火活化佈植的雜質。
再者，閘極間隔物78可形成於沿著虛置閘極72與遮罩74之側壁的閘極密封間隔物76上。可順應地沉積絕緣材料並接著非等向性地蝕刻絕緣材料而形成閘極間隔物78。閘極間隔物78的絕緣材料可為氮化矽、碳氮化矽等或前述之組合。在一些實施例中（未繪示），閘極間隔物78由多層絕緣材料所形成，且包括多個膜層。例如，閘極間隔物78可包括多層氮化矽，或可包括一層氧化矽設置於兩層氮化矽之間。閘極間隔物78可伴隨閘極密封間隔物76而形成，或可在閘極密封間隔物76之後形成。在一些實施例中，順應地形成閘極密封間隔物76的第一間隔物層，於第一間隔物層上順應地形成閘極間隔物78的第二間隔物層，一同圖案化此二間隔物層以同時圖案化閘極密封間隔物76與閘極間隔物78。形成閘極密封間隔物76與閘極間隔物78兩者是可選的。在一些實施例中，形成且圖案化單一間隔物層以形成單一層間隔物。
第5A與5B圖中，磊晶源極∕汲極區80形成於鰭片52中，以於鰭片52個別的通道區58中施加應力（stress）而改善性能。磊晶源極∕汲極區80形成於鰭片52中，使得每個虛置閘極72設置於個別鄰近成對的磊晶源極∕汲極區80之間。在一些實施例中，磊晶源極∕汲極區80可延伸至鰭片52位於淺溝槽隔離區56的頂表面之下的部分。在一些實施例中，閘極間隔物78用於以一適當的橫向距離隔離磊晶源極∕汲極區80與虛置閘極72，使磊晶源極∕汲極區80不會短路製得的鰭狀場效電晶體後續所形成的閘極。如以下所進一步討論，磊晶源極∕汲極區80為包括複數層摻雜半導體層的多層磊晶區。磊晶源極∕汲極區80係形成為彼此分離，使鰭片52的通道區58具有長度L1 。在一些實施例中，通道區58的長度L1 可介於約10nm至約100nm之間的範圍。再者，如以下所討論，磊晶源極∕汲極區80從鰭片52的表面抬升，使得磊晶源極∕汲極區80的最頂層表面於鰭片52的最頂表面之上延伸高度H2 。高度H2 可大於約3nm，例如介於約3nm至約8nm之間的範圍。
第6至9圖是形成磊晶源極∕汲極區80的中間階段的剖面圖。如以上所指明，每個鰭片52可具有多個虛置閘極72形成於其上。雖然繪示出一磊晶源極∕汲極區80形成於兩個虛置閘極72之間，但應能理解有多個磊晶源極∕汲極區80同時形成。
所說明的製程可用以於區域50N或區域50P中形成磊晶源極∕汲極區80。可透過遮蔽如p型金屬氧化物半導體區的區域50P且進行所說明的步驟，而於如n型金屬氧化物半導體區的區域50N中形成磊晶源極∕汲極區80。區域50N中的磊晶源極∕汲極區80可包括任何可接受的材料，例如適合用於n型鰭狀場效電晶體的材料。例如，若鰭片52為矽，區域50N中的磊晶源極∕汲極區80可包括於通道區58中施加伸張應變（tensile strain）的材料，例如矽、SiC、SiCP或SiP等。接著，可移除遮罩。可透過遮蔽如n型金屬氧化物半導體區的區域50N且重複所說明的步驟，而於如p型金屬氧化物半導體區的區域50P中形成磊晶源極∕汲極區80。磊晶源極∕汲極區80可包括任何可接受的材料，例如適合用於p型鰭狀場效電晶體的材料。磊晶源極∕汲極區80可包括任何可接受的材料，例如適合用於p型鰭狀場效電晶體的材料。例如，若鰭片52為矽，區域50P中的磊晶源極∕汲極區80可包括於通道區58中施加壓縮應變（compressive strain）的材料，如SiGe、SiGeB、Ge或GeSn等。如以下所進一步討論，在成長時利用n型及∕或p型雜質於原位摻雜磊晶源極∕汲極區80，因此形成了源極∕汲極區。源極∕汲極區的n型及∕或p型雜質可為先前所討論的任何雜質。
第6圖中，凹口（recess）82形成於鰭片52的源極∕汲極區中以及鄰近的閘極間隔物78之間，且形成於鰭片52的末端。可利用可接受的光學微影與蝕刻技術形成凹口82。凹口82係形成至寬度W2 ，寬度W2 與鄰近的閘極間隔物78之間的距離相同。在一些實施例中，寬度W2 介於約10nm至約100nm之間的範圍。凹口82係形成至深度D1 。在一些實施例中，深度D1 大於約40nm。凹口82可部分地延伸至鰭片52之中或完全地延伸穿過鰭片52。
第7圖中，進行第一磊晶成長製程84以於凹口82形成磊晶源極∕汲極區80的第一磊晶層80A。如以下所討論，第一磊晶成長製程84的成長輪廓（profile）係使得凹口82側壁上的成長速率與凹口82底部上的成長速率有些微不同，例如有小於50%的差異。
於第一磊晶成長製程84時，將凹口82曝露至許多前驅物（precursor），前驅物包括半導體材料前驅物、摻質前驅物與蝕刻前驅物。可將凹口82同時曝露至所有前驅物，或可以重複的循環曝露至前驅物。例如，可在循環的第一部份將凹口82曝露至半導體材料前驅物與摻質前驅物，且在循環的第二部分將凹口82曝露至蝕刻前驅物。第一磊晶層80A可具有低摻雜濃度，而增加對鰭片52材料的黏著力。在磊晶源極∕汲極區80包括矽鍺的實施例中，例如形成p型源極∕汲極區時，以低p型摻雜（例如，硼）濃度與高鍺濃度形成第一磊晶層80A。例如，第一磊晶層80A的p型摻雜（例如，硼）濃度可大於2x1020 cm-3 ，例如介於約2x1020 cm-3 至約3x1020 cm-3 之間的範圍，且第一磊晶層80A的鍺濃度可介於約45原子百分比（.%）至約55原子百分比之間的範圍。可透過選擇成長的前驅物及其流速來控制第一磊晶層80A的摻雜與鍺濃度。
第一磊晶成長製程84的半導體材料前驅物包括沉積所欲半導體材料的前驅物。範例半導體材料前驅物包括甲矽烷（SiH4 ）、甲鍺烷（GeH4 ）、二氯矽烷（H2 SiCl2 ）、乙矽烷（Si2 H6 ）、三氯矽烷（HSiCl3 ）等。例如，在磊晶源極∕汲極區80由矽所形成的一實施例中，例如形成n型源極∕汲極區時，半導體材料前驅物包括甲矽烷。同樣地，在磊晶源極∕汲極區80由矽鍺所形成的一實施例中，例如形成p型源極∕汲極區時，半導體材料前驅物包括甲矽烷與甲鍺烷。如以下所進一步討論，第一磊晶成長製程84是在低溫之下進行。第一磊晶成長製程84使用甲矽烷作為其中一種半導體材料前驅物，因為甲矽烷可用於在低溫之下的沉積。
摻質前驅物包括所欲的導電型態的任何前驅物，而所欲的導電型態將半導體材料前驅物納入考量。例如，在磊晶源極∕汲極區80為SiCP的一實施例中，例如形成n型源極∕汲極區時，摻質前驅物可包括如磷化氫（PH3 ）的磷前驅物以及如烴（Cx Hy ）的碳前驅物。同樣地，在磊晶源極∕汲極區80為SiGeB的一實施例中，例如形成p型源極∕汲極區時，摻質前驅物可包括如乙硼烷（B2 H6 ）的硼前驅物。
蝕刻前驅物在第一磊晶成長製程84時控制了成長。詳細而論，蝕刻前驅物控制成長選擇性，使得第一磊晶層80A在所欲位置成長（例如，於鰭片52的凹口82中），且不會在非所欲位置成長（例如，於淺溝槽隔離區56上）。在一些實施例中，蝕刻前驅物包括鹽酸（HCl）。
進行第一磊晶成長製程84直到第一磊晶層80A達到所欲的厚度。可透過控制第一磊晶成長製程84時的溫度與壓力，而決定第一磊晶成長製程84的成長輪廓。詳細而論，第一磊晶成長製程84是在低溫與高壓之下進行。例如，第一磊晶成長製程84的溫度可小於約600℃，例如介於約450℃至約600℃之間的範圍，且第一磊晶成長製程84的壓力可大於約50Torr，例如介於約50Torr至約100Torr之間的範圍。在低成長溫度之下，原子具有較低的遷移能力（migration capability），使原子在不同的結晶方向之間具有較低的選擇性。因此，在低溫之下，沿著＜100＞方向與＜110＞方向的成長速率的差異會減少，使得第一磊晶成長製程84的成長輪廓較為順應的。因此，雖然第一磊晶成長製程84沿著凹口82側壁的成長速率小於沿著凹口82底部的成長速率，成長速率由於第一磊晶成長製程84時的低溫與高壓而有著些微差異。例如，沿著凹口82側壁與沿著凹口82底部的成長速率的比值可介於約0.9至約1.0。
第一磊晶層80A沿著凹口82的側邊具有厚度T1 ，且沿著凹口82的底部具有厚度T2 。由於第一磊晶成長製程84的成長速率具有差異，厚度T1 與T2 不同，側壁厚度T1 小於底部厚度T2 。例如，底部厚度T2 可小於約15nm，例如介於約5nm至約11nm之間的範圍，且側壁厚度T1 可介於約4.5nm至約11nm之間的範圍，例如小於約10nm。側壁厚度T1 與底部厚度T2 間的差異小是歸因於第一磊晶成長製程84的成長輪廓。例如，側壁厚度T1 與底部厚度T2 的比值可介於約0.9至約1.0之間的範圍。如以上所指明，第一磊晶層80A具有高鍺濃度，例如介於約45原子百分比至約55原子百分比之間的範圍。高鍺濃度的SiGeB磊晶成長製程易具有由下而上的（bottom-up）成長輪廓，但由下而上成長第一磊晶層80A將會造成對鰭片52較弱的黏著力。第一磊晶成長製程84的成長輪廓使第一磊晶層80A形成具有高鍺濃度，而同時仍充分地黏著至鰭片52。第一磊晶層80A的高鍺濃度增加施加於通道區58的應力，因而增加載子（carrier）遷移且減少製得的鰭狀場效電晶體的通道區58中的阻值。第一磊晶層80A的高鍺濃度也減少磊晶源極∕汲極區80中的阻值，因為鍺的能帶間隙（band gap）低於矽的能帶間隙。減少通道區58以及∕或磊晶源極∕汲極區80的阻值可增加製得的鰭狀場效電晶體的性能。
第8圖中，進行第二磊晶成長製程86以於凹口82中形成磊晶源極∕汲極區80的第二磊晶層80B。第二磊晶層80B填充了凹口82，且可過度填充凹口82。如以下所討論，第二磊晶成長製程86具有由下而上的成長輪廓，使第二磊晶層80B從凹口82的底部成長且不會從凹口82的側壁成長。換言之，第二磊晶成長製程86時的垂直成長速率（例如，沿著＜100＞方向）大於第一磊晶成長製程84時的垂直成長速率。同樣地，第二磊晶成長製程86時的橫向成長速率（例如，沿著＜110＞方向）小於第一磊晶成長製程84時的橫向成長速率。
第二磊晶成長製程86時，凹口82曝露至許多前驅物，前驅物包括半導體材料前驅物、摻質前驅物與蝕刻前驅物。可將凹口82同時曝露至所有前驅物，或可以重複的循環曝露至前驅物。例如，可在循環的第一部份將凹口82曝露至半導體材料前驅物與摻質前驅物，且在循環的第二部分將凹口82曝露至蝕刻前驅物。第二磊晶層80B與第一磊晶層80A相比具有較高的摻雜濃度，進而為製得的鰭狀場效電晶體提供充足的多數載子。在磊晶源極∕汲極區80包括矽鍺的實施例中，例如形成p型源極∕汲極區時，以高p型摻雜（例如，硼）濃度與高鍺濃度形成第二磊晶層80B。例如，第二磊晶層80B的p型摻雜（例如，硼）濃度可介於約7x1020 cm-3 至約1x1021 cm-3 之間的範圍，且第二磊晶層80B的鍺濃度可介於約45原子百分比至約55原子百分比之間的範圍。值得注意地，第二磊晶層80B的鍺濃度與第一磊晶層80A的鍺濃度大約相同。第二磊晶層80B的鍺濃度可與第一磊晶層80A的鍺濃度不同，但第一磊晶層80A與第二磊晶層80B的鍺濃度可介於相同範圍（例如，約45原子百分比至約55原子百分比之間）。高鍺濃度可使第一磊晶層80A作為障壁（barrier），於第二磊晶成長製程86時有助於減少摻質（例如，硼）從第二磊晶層80B遷移至通道區58。可因此減少汲極引發能帶降低（drain-induced barrier lowering, DIBL），進而增加製得的鰭狀場效電晶體的性能。再者，第二磊晶層80B的摻雜濃度可具有梯度變化，從第二磊晶層80B的最頂層表面至第二磊晶層80B的最底層表面的延伸方面減少。可透過選擇成長的前驅物及其流速來控制第二磊晶層80B的摻雜與鍺濃度。
第二磊晶成長製程86的半導體材料前驅物包括用於沉積所欲半導體材料的前驅物。第二磊晶成長製程86的半導體材料前驅物可與第一磊晶成長製程84的半導體材料前驅物相同（或可不同）。在一些實施例中，第二磊晶成長製程86的至少一種半導體材料前驅物與第一磊晶成長製程84的半導體材料前驅物不同。例如，在磊晶源極∕汲極區80由矽鍺所形成的一實施例中，例如形成p型源極∕汲極區時，半導體材料前驅物包括二氯矽烷與甲鍺烷。如以下所進一步討論，第二磊晶成長製程86是在高溫之下進行。第二磊晶成長製程86使用二氯矽烷作為其中一種半導體材料前驅物，因為二氯矽烷可用於在高溫之下沉積。
摻質前驅物與第一磊晶成長製程84的摻質前驅物相同。如以上所指明，第二磊晶層80B的摻雜濃度大於第一磊晶層80A的摻雜濃度。如此一來，第二磊晶成長製程86時摻質前驅物的流速可大於第一磊晶成長製程84時摻質前驅物的流速。例如，第一磊晶成長製程84時摻質前驅物的流速可介於約60sccm至約120sccm，且第二磊晶成長製程86時摻質前驅物的流速可介於約150sccm至約300sccm。
蝕刻前驅物與第一磊晶成長製程84的蝕刻前驅物相同。如以上所指明，蝕刻前驅物控制成長選擇性，使第一磊晶層80A於所欲位置（例如，於鰭片52的凹口82中）成長，且不會於非所欲位置（例如，於淺溝槽隔離區56上）成長。因為第二磊晶成長製程86時的垂直成長速率大於第一磊晶成長製程84時的垂直成長速率，可能需要進行額外的蝕刻來控制成長選擇性。如此一來，第二磊晶成長製程86時蝕刻前驅物的流速可大於第一磊晶成長製程84時蝕刻前驅物的流速。
第二磊晶成長製程86具有由下而上的成長輪廓，且進行第二磊晶成長製程86直到第二磊晶層80B具有所欲的厚度。可透過控制第二磊晶成長製程86時的溫度與壓力，而決定第二磊晶成長製程86的成長輪廓。詳細而論，第二磊晶成長製程86是在高溫與低壓之下進行。例如，第二磊晶成長製程86的溫度可大於約600℃，例如介於約600℃至約650℃之間的範圍，且第二磊晶成長製程86的壓力可小於約50Torr，例如介於約10Torr至約20Torr之間的範圍。在高成長溫度之下，原子具有較高的遷移能力，使原子在不同的結晶方向之間具有較高的選擇性。因此，在高溫之下，沿著＜100＞方向與＜110＞方向的成長速率的差異會增加，使得第二磊晶成長製程86的成長輪廓較具選擇性。因此，第二磊晶成長製程86沿著凹口82側壁的成長速率小於沿著凹口82底部的成長速率，且兩成長速率有著較大差異。例如，沿著凹口82側壁與沿著凹口82底部的成長速率的比值可介於約0.1至約0.3。
第9圖中，可進行第三磊晶成長製程88以形成第三磊晶層80C。第三磊晶成長製程88是可選且可省略的。第三磊晶層80C為最後的膜層，且可於後續矽化（silicidation）製程時移除或消耗第三磊晶層80C。
第三磊晶成長製程88時，磊晶源極∕汲極區80曝露至許多前驅物，前驅物包括半導體材料前驅物、摻質前驅物與蝕刻前驅物。可將凹口82同時曝露至所有前驅物，或可以重複的循環曝露至前驅物。例如，可在循環的第一部份將凹口82曝露至半導體材料前驅物與摻質前驅物，且在循環的第二部分將凹口82曝露至蝕刻前驅物。第三磊晶層80C的摻雜濃度小於第一磊晶層80A與第二磊晶層80B的摻雜濃度，因而可增加第三磊晶層80C的成長選擇性。第三磊晶層80C在後續製程時為保護第二磊晶層80B的犧牲（sacrificial）層，且可在後續形成源極∕汲極接觸件時移除第三磊晶層80C（以下針對第15A與15B圖進一步討論）。在磊晶源極∕汲極區80包括矽鍺的實施例中，例如形成p型源極∕汲極區時，以低p型摻雜（例如，硼）濃度與低鍺濃度形成第三磊晶層80C。例如，第三磊晶層80C的摻雜（例如，硼）濃度可介於約9x1019 cm-3 至約2x1020 cm-3 之間的範圍，且第三磊晶層80C的鍺濃度可介於約20原子百分比至約22原子百分比之間的範圍。值得注意地，第三磊晶層80C的鍺濃度小於第一磊晶層80A與第二磊晶層80B的鍺濃度。
第三磊晶成長製程88的前驅物可與第二磊晶成長製程86的前驅物相同，但可具有不同的流速。例如，當磊晶源極∕汲極區80為SiCP時，例如形成n型源極∕汲極區時，相較於第二磊晶成長製程86時，於第三磊晶成長製程88時可藉由流送較少的磷化氫與較少的烴來減少第三磊晶層80C的摻雜濃度。同樣地，當磊晶源極∕汲極區80為SiGeB時，例如形成p型源極∕汲極區時，相較於第二磊晶成長製程86時，於第三磊晶成長製程88時可藉由流送較少的甲鍺烷與較少的乙硼烷來減少第三磊晶層80C的鍺濃度。
第三磊晶成長製程88也具有由下而上的成長輪廓，且進行第三磊晶成長製程88直到第三磊晶層80C具有所欲的厚度。例如，第三磊晶層80C可具有介於約0.5nm至約10nm之間範圍的厚度T3 。可透過控制第三磊晶成長製程88時的溫度與壓力，而決定第三磊晶成長製程88的成長輪廓。詳細而論，第三磊晶成長製程88是在高溫與低壓之下進行。例如，第三磊晶成長製程88的溫度可大於約600℃，例如介於約600℃至約620℃之間的範圍，且第三磊晶成長製程88的壓力可小於約50Torr，例如介於約20Torr至約30Torr之間的範圍。第三磊晶成長製程88的溫度可小於第二磊晶成長製程86的溫度，且第三磊晶成長製程88的溫度可大於第一磊晶成長製程84的溫度。第三磊晶成長製程88的壓力可大於第二磊晶成長製程86的壓力，且第三磊晶成長製程88的壓力可小於第一磊晶成長製程84的壓力。
第10圖繪示出形成磊晶源極∕汲極區80之後的其中一個磊晶源極∕汲極區80。第10圖係沿著第1圖中的參考剖面B-B與C-C繪示出磊晶源極∕汲極區80，且第10圖一同繪示出兩剖面以達到方便說明的目的。在此實施例中，磊晶源極∕汲極區80具有從個別的鰭片52表面抬升且平坦的上表面。在一些實施例中，磊晶源極∕汲極區80可具有凸狀的上表面。磊晶源極∕汲極區80具有全寬度W3 。全寬度W3 可介於約40nm至約80nm之間的範圍。
鄰近的磊晶源極∕汲極區80可相互合併而使製得的磊晶源極∕汲極區80橫跨至多個鰭片52（例如，所示範例中的一對鰭片52），上述鰭片52為相同鰭狀場效電晶體的一部份。當鄰近的磊晶源極∕汲極區80相互合併時，氣隙（air gap）90形成於磊晶源極∕汲極區80下方，且位於鰭狀場效電晶體的鄰近成對的鰭片52之間。氣隙90可具有介於約0nm至約50nm之間的範圍的高度H3 。氣隙90在鄰近的磊晶源極∕汲極區80相互合併處也可具有內角θ1 。氣隙90的內角θ1 可介於約10度至約150度之間的範圍。隔離區56在鄰近成對的鰭片52之間可具有凹狀的上表面，因而增加了氣隙90的體積。氣隙90在淺溝槽隔離區56的鄰近部分之間具有寬度W4 。寬度W4 可介於約0nm至約50nm之間的範圍。
鰭片52的源極∕汲極區的蝕刻製程可具有一些製程變化。詳細而論，對於同一鰭狀場效電晶體，鄰近成對的鰭片52可緊密地成群在一起，使鰭片52的外側壁與內側壁相比可以較高的速率被蝕刻。淺溝槽隔離區56沿著鰭片52內側壁的部分可具有高度H4 ，高度H4 大於約25nm，例如介於約30nm至約50nm之間的範圍，且淺溝槽隔離區56沿著鰭片52外側壁的部分可具有高度H5 ，高度H5 大於約20nm，例如介於約25nm至約45nm之間的範圍。
第10圖也繪示出第一磊晶層80A進一步的態樣。除了具有沿著凹口82側邊的厚度T1 以及沿著凹口82底部的厚度T2 ，第一磊晶層80A也具有沿著鰭片52側壁的橫向厚度T4 。橫向厚度T4 可小於約6nm，例如介於約2nm至約4nm之間的範圍。橫向厚度T4 小於側壁厚度T1 與底部厚度T2 。
第11A與11B圖中，第一層間介電質102沉積於中間結構之上。第一層間介電質102可由介電材料所形成，且可利用任何合適的方法如化學氣相沉積、電漿增強化學氣相沉積（plasma-enhanced CVD, PECVD）或流動式化學氣相沉積形成第一層間介電質102。介電材料可包括磷矽酸鹽玻璃（phospho-silicate glass, PSG）、硼矽酸鹽玻璃（boro-silicate glass, BSG）、硼摻雜磷矽酸鹽玻璃（boro-doped phospho-silicate glass, BPSG）或未摻雜矽酸鹽玻璃（undoped silicate glass, USG）等。可使用利用任何可接受的製程所形成的其它介電材料。在一些實施例中，接觸蝕刻停止層（contact etch stop layer, CESL）100設置於第一層間介電質102與磊晶源極∕汲極區80、遮罩74以及閘極間隔物78之間。接觸蝕刻停止層100可包括介電材料，例如氮化矽、氧化矽、氮氧化矽等，所述的介電材料與上覆的第一層間介電質102的材料相比具有不同的蝕刻速率。
第12A與12B圖中，可進行如化學機械研磨的平坦化製程，以使第一層間介電質102的頂表面與虛置閘極72或遮罩74的頂表面齊平。平坦化製程也可移除虛置閘極72上的遮罩74，以及閘極密封間隔物76與閘極間隔物78沿著遮罩74的側壁之部分。平坦化製程後，虛置閘極72、閘極密封間隔物76、閘極間隔物78與第一層間介電質102的頂表面位於相同水平。因此，虛置閘極72的頂表面通過第一層間介電質102而露出。在一些實施例中，可保留遮罩74，在此情況下，平坦化製程使第一層間介電質102的頂表面與遮罩74的頂表面齊平。
第13A與13B圖中，於蝕刻步驟中移除虛置閘極72以及遮罩74（若存在）而形成凹口104。也可移除虛置閘極介電層70於凹口104中的部分。在一些實施例中，僅移除虛置閘極72並保留虛置閘極介電質70，且虛置閘極介電質70透過凹口104露出。在一些實施例中，從位於晶粒（die）第一區（例如，核心邏輯區（core logic region））中的凹口104移除虛置閘極介電層70，且在位於晶粒第二區（例如，輸入∕輸出區（input∕output region））的凹口104中保留虛置閘極介電層70。在一些實施例中，利用非等向性乾式蝕刻製程移除虛置閘極72。例如，蝕刻製程可包括乾式蝕刻製程，其使用選擇性蝕刻虛置閘極72的反應氣體，而不蝕刻第一層間介電質102或閘極間隔物78。每個凹口104露出個別的鰭片52的通道區58。每個通道區58設置於鄰近成對的磊晶源極∕汲極區80之間。移除且蝕刻虛置閘極72時，虛置閘極介電層70可作為蝕刻停止層。移除虛置閘極72後，接著可視需要地移除虛置閘極介電層70。
第14A與14B圖中，形成閘極介電質106與閘極電極108為取代閘極。第14C繪示出第14B圖的區域10的細部示意圖。閘極介電質106順應地沉積於凹口104中，例如位於鰭片52的頂表面與側壁上以及閘極密封間隔物76∕閘極間隔物78的側壁上。閘極介電質106也可形成於第一層間介電質102的頂表面上。根據一些實施例，閘極介電質106包括氧化矽、氮化矽或前述的多層。在一些實施例中，閘極介電質106包括高介電常數介電材料，且在這些實施例中，閘極介電質106可具有大於約7.0的介電常數值，且可包括金屬氧化物或Hf、Al、Zr、La、Mg、Ba、Ti、Pb與前述之組合的矽化物。閘極介電質106的形成方法可包括分子束沉積（molecular-beam deposition, MBD）、原子層沉積（atomic layer deposition, ALD）或電漿增強化學氣相沉積等。在部分的虛置閘極介電層70保留於凹口104中的實施例中，閘極介電質106包括虛置閘極介電層70的材料（例如，SiO2 ）。
閘極電極108分別沉積於閘極介電質106之上，並填充凹口104的剩餘部分。閘極電極108可包括含金屬材料如TiN、TiO、TaN、TaC、Co、Ru、Al、W、前述之組合或前述之多層。例如，儘管第14B圖中僅繪示出單一層閘極電極108，閘極電極108可包括任何數量的襯層（liner layer）108A、任何數量的功函數調諧層（work function tuning layer）108B與填充材料108C，如第14C圖所示。填充閘極電極108後，可進行如化學機械研磨的平坦化製程移除閘極介電質106與閘極電極108的材料過多的部分，過多的部分位於第一層間介電質102的頂表面之上。閘極電極108與閘極介電質106的材料剩餘的部分因此形成了製得的鰭狀場效電晶體的取代閘極。閘極電極108與閘極介電質106可一同稱為「閘極堆疊」或「金屬閘極堆疊」，每個金屬閘極堆疊包括閘極介電質106與閘極電極108。金屬閘極堆疊可沿著鰭片52的通道區58的側壁延伸。
可同時形成區域50N與區域50P中的閘極介電質106，使每個區域中的閘極介電質106由相同材料所形成，且可同時形成閘極電極108，使每個區域中的閘極電極108由相同材料所形成。在一些實施例中，可利用不同的製程形成每個區域中的閘極介電質106，使閘極介電質106可為不同的材料，以及∕或可利用不同的製程形成每個區域中的閘極電極108，使閘極電極108可為不同的材料。使用不同的製程時，可使用各種遮蔽步驟遮蔽且露出適當的區域。
第二層間介電質112沉積於第一層間介電質102之上。在一些實施例中，第二層間介電質112是流動式化學氣相沉積方法所形成的可流動薄膜。在一些實施例中，第二層間介電質112是由介電材料所形成，介電材料如磷矽酸鹽玻璃、硼矽酸鹽玻璃、硼摻雜磷矽酸鹽玻璃、未摻雜矽酸鹽玻璃等，且可利用任何合適的方法如化學氣相沉積與電漿增強化學氣相沉積來沉積第二層間介電質112。根據一些實施例，形成第二層間介電質112之前，凹蝕金屬閘極堆疊，使凹口直接位於金屬閘極堆疊之上以及閘極間隔物78的相對部分之間。包括一或多層介電材料的閘極遮罩110填充於凹口中，介電材料如氮化矽、氮氧化矽等，接著利用平坦化製程移除介電材料延伸於第一層間介電質102之上過多的部分。後續形成的閘極接觸件將穿過閘極遮罩110，以接觸凹蝕的閘極電極108的頂表面。
在第15A與15B圖中，根據一些實施例，閘極接觸件114與源極∕汲極接觸件116形成穿過第二層間介電質112與第一層間介電質102。源極∕汲極接觸件116的開口形成穿過第一層間介電質102與第二層間介電質112，且閘極接觸件114的開口形成穿過第二層間介電質112與閘極遮罩110。可利用可接受的光學微影與蝕刻技術形成開口。在形成開口時，移除第三磊晶層80C（參照第10圖），因此露出了第二磊晶層80B。
矽化物118可形成於磊晶源極∕汲極區80上。在一些實施例中，形成源極∕汲極接觸件116之前，導電材料沉積於磊晶源極∕汲極區80（例如，於源極∕汲極接觸件116的開口中）上。導電材料可為鈦、鈷、鎳等，且可為與源極∕汲極接觸件116不同的導電材料。退火導電材料以形成矽化物118。矽化物118物理性與電性耦接至磊晶源極∕汲極區80。
接著，如擴散阻障層（diffusion barrier layer）的襯層、黏著層（adhesion layer）等以及導電材料形成於開口中以及矽化物118上。襯層包括鈦、氮化鈦、鉭或氮化鉭等。導電材料可為銅、銅合金、銀、金、鎢、鈷、鋁或鎳等。可進行如化學機械研磨的平坦化製程從第二層間介電質112的表面移除過多的材料。剩餘的襯層與導電材料於開口中形成了源極∕汲極接觸件116與閘極接觸件114。源極∕汲極接觸件116物理性與電性耦接至矽化物118，且閘極接觸件114物理性與電性耦接至閘極電極108。可於不同製程中形成源極∕汲極接觸件116與閘極接觸件114，或可於相同製程中形成源極∕汲極接觸件116與閘極接觸件114。儘管繪示為形成於相同剖面中，應能理解的是每個源極∕汲極接觸件116與閘極接觸件114可形成於不同剖面中，因而避免接觸件短路。
實施例可達到許多優點。在低溫與高壓之下進行第一磊晶成長製程84，使得第一磊晶層80A形成具有較為順應的成長輪廓。可因此形成具有較高鍺濃度的第一磊晶層80A，而在磊晶磊晶源極∕汲極區80中沒有產生缺陷的風險。形成第一磊晶層80A至高鍺濃度增加了施加於通道區58的應力，因而增加載子遷移且減少通道區58中的阻值。第一磊晶層80A中的高鍺濃度也減少磊晶源極∕汲極區80中的阻值。減少通道區58以及∕或磊晶源極∕汲極區80中的阻值可增加製得的鰭狀場效電晶體的性能。最後，第一磊晶層80A中的高鍺濃度也減少摻質從第二磊晶層80B遷移至通道區58，因此減少了減少汲極引發能帶降低，進而增加製得的鰭狀場效電晶體的性能。
在一實施例中，半導體裝置包括：從基板延伸而出的鰭片；位於鰭片的通道區之上的閘極堆疊；以及位於鰭片中且鄰近於通道區的源極∕汲極區，源極∕汲極區包括：接觸鰭片側壁的第一磊晶層，第一磊晶層包括以摻質摻雜的矽與鍺，且第一磊晶層具有第一濃度的摻質；以及位於第一磊晶層上的第二磊晶層，第二磊晶層包括以上述摻質摻雜的矽與鍺，且第二磊晶層具有第二濃度的上述摻質，第二濃度大於第一濃度，且第一磊晶層與第二磊晶層具有相同的鍺濃度。
在半導體裝置的一些實施例中，第一磊晶層具有沿著第二磊晶層的側壁延伸的第一部分，以及沿著第二磊晶層的底部延伸的第二部分，第一部分具有第一厚度，第二部分具有第二厚度，且第一厚度與第二厚度的比值介於0.9至1.0之間。在半導體裝置的一些實施例中，鍺濃度介於45原子百分比至55原子百分比之間。在半導體裝置的一些實施例中，摻質的第一濃度介於2x1020 cm-3 至3x1020 cm-3 之間。在半導體裝置的一些實施例中，摻質的第二濃度介於7x1020 cm-3 至1x1021 cm-3 之間。在半導體裝置的一些實施例中，摻質的第二濃度從第二磊晶層的最頂層表面至第二磊晶層的最底層表面的延伸方向減少。
在一實施例中，半導體裝置的製造方法包括：形成從基板延伸而出的鰭片；於鰭片的通道區之上形成閘極堆疊；在鄰近於通道區的鰭片中形成凹口；利用第一磊晶成長製程，沿著凹口的側壁與底部成長第一磊晶層，第一磊晶成長製程沿著凹口的側壁具有第一成長速率，且第一磊晶成長製程沿著凹口的底部具有第二成長速率，第二成長速率大於第一成長速率；以及利用第二磊晶成長製程，於凹口中的第一磊晶層上成長第二磊晶層，第二磊晶成長製程沿著凹口的側壁具有第三成長速率，且第二磊晶成長製程沿著凹口的底部具有第四成長速率，第三成長速率小於第一成長速率，且第四成長速率大於第二成長速率。
在半導體裝置的製造方法的一些實施例中，第一磊晶成長製程是在第一溫度與第一壓力之下進行，且第二磊晶成長製程是在第二溫度與第二壓力之下進行，第一溫度小於第二溫度，且第一壓力大於第二壓力。在半導體裝置的製造方法的一些實施例中，第一磊晶成長製程是利用多個第一半導體材料前驅物與摻質前驅物進行，且第二磊晶成長製程是利用多個第二半導體材料前驅物與上述摻質前驅物進行，第二半導體材料前驅物的至少一子集與第一半導體材料前驅物不同。在半導體裝置的製造方法的一些實施例中，摻質前驅物為乙硼烷，第一半導體材料前驅物為甲矽烷與甲鍺烷，且第二半導體材料前驅物為二氯矽烷與甲鍺烷。在半導體裝置的製造方法的一些實施例中，與第一磊晶成長製程時相比，於第二磊晶成長製程時以較高的流速配送乙硼烷，且於第二磊晶成長製程時以較高的流速配送甲鍺烷。
在一實施例中，半導體裝置的製造方法包括：形成從基板延伸而出的鰭片；於鰭片的通道區之上形成閘極堆疊；在鄰近於通道區的鰭片中形成凹口；利用第一磊晶成長製程，沿著凹口的側壁與底部成長第一磊晶層，第一磊晶成長製程是在第一溫度與第一壓力之下進行；以及利用第二磊晶成長製程，於凹口中的第一磊晶層上成長第二磊晶層，第二磊晶成長製程是在第二溫度與第二壓力之下進行，第一溫度小於第二溫度，且第一壓力大於第二壓力。
在半導體裝置的製造方法的一些實施例中，第一溫度介於450℃至600℃之間。在半導體裝置的製造方法的一些實施例中，第二溫度介於600℃至650℃之間。在半導體裝置的製造方法的一些實施例中，第一壓力介於30Torr至100Torr之間。在半導體裝置的製造方法的一些實施例中，第二壓力介於10Torr至20Torr之間。在半導體裝置的製造方法的一些實施例中，第一磊晶層為具有第一鍺濃度與第一硼濃度的摻硼矽鍺，且第二磊晶層為具有第一鍺濃度與第二硼濃度的摻硼矽鍺，第二硼濃度大於第一硼濃度。在一些實施例中，半導體裝置的製造方法更包括利用第三磊晶成長製程，於第二磊晶層上成長第三磊晶層，第三磊晶層是在第三溫度與第三壓力之下進行，第一溫度小於第三溫度，且第一壓力大於第三壓力。在半導體裝置的製造方法的一些實施例中，第三磊晶層為具有第二鍺濃度與第三硼濃度的摻硼矽鍺，第三硼濃度小於第一硼濃度與第二硼濃度，且第二鍺濃度小於第一鍺濃度。在半導體裝置的製造方法的一些實施例中，第一磊晶成長製程沿著凹口的側壁具有第一成長速率，且第一磊晶成長製程沿著凹口的底部具有第二成長速率，第二成長速率大於第一成長速率，且其中第二磊晶成長製程沿著凹口的側壁具有第三成長速率，且第二磊晶成長製程沿著凹口的底部具有第四成長速率，第三成長速率小於第一成長速率，且第四成長速率大於第二成長速率。
以上概述數個實施例之部件，以便在本發明所屬技術領域中具有通常知識者可更易理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解，他們能以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解到，此類等效的製程和結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神和範圍之下，做各式各樣的改變、取代和替換。
10,50N,50P:區域 50:基板 52:鰭片 56:淺溝槽隔離區 58:通道區 70:虛置閘極介電層 72:虛置閘極 74:遮罩 76:閘極密封間隔物 78:閘極間隔物 80:磊晶源極∕汲極區 80A:第一磊晶層 80B:第二磊晶層 80C:第三磊晶層 82,104:凹口 84:第一磊晶成長製程 86:第二磊晶成長製程 88:第三磊晶成長製程 90:氣隙 100:接觸蝕刻停止層 102:第一層間介電層 106:閘極介電質 108:閘極電極 108A:襯層 108B:功函數調諧層 108C:填充材料 110:閘極遮罩 112:第二層間介電質 114:閘極接觸件 116:源極∕汲極接觸件 118:矽化物 A-A,B-B,C-C:剖面 D1 :深度 H1 ,H2 ,H3 ,H4 ,H5 :高度 L1 :長度 P1 :節距 T1 ,T2 ,T3 ,T4 :厚度 W1 ,W2 ,W3 ,W4 :寬度 θ1 :內角
以下將配合所附圖式詳述本發明實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製且僅用以說明例示。事實上，可任意地放大或縮小元件的尺寸，以清楚地表現出本發明實施例的特徵。 第1圖是根據一些實施例，繪示出鰭狀場效電晶體一範例的三維示意圖。 第2、3、4A、4B、5A、5B、6、7、8、9、10、11A、11B、12A、12B、13A、13B、14A、14B、14C、15A與15B是根據一些實施例，繪示出在製造鰭狀場效電晶體的中間階段的剖面圖。
52:鰭片
58:通道區
70:虛置閘極介電層
72:虛置閘極
74:遮罩
76:閘極密封間隔物
78:閘極間隔物
80A:第一磊晶層
80B:第二磊晶層
82:凹口
86:第二磊晶成長製程

Claims (1)

  1. 一種半導體裝置，包括： 一鰭片，從一基板延伸而出； 一閘極堆疊，位於該鰭片的一通道區之上；以及 一源極∕汲極區，位於該鰭片中且鄰近於該通道區，該源極∕汲極區包括： 一第一磊晶層，接觸該鰭片的側壁，該第一磊晶層包括以一摻質（dopant）摻雜的矽與鍺，且該第一磊晶層具有一第一濃度的該摻質；以及 一第二磊晶層，位於該第一磊晶層上，該第二磊晶層包括以該摻質摻雜的矽與鍺，且該第二磊晶層具有一第二濃度的該摻質，該第二濃度大於該第一濃度，且該第一磊晶層與該第二磊晶層具有一相同的鍺濃度。
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