TW202105658A - 晶片結構及其製造方法 - Google Patents

晶片結構及其製造方法 Download PDF

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TW202105658A
TW202105658A TW109125329A TW109125329A TW202105658A TW 202105658 A TW202105658 A TW 202105658A TW 109125329 A TW109125329 A TW 109125329A TW 109125329 A TW109125329 A TW 109125329A TW 202105658 A TW202105658 A TW 202105658A
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substrate
wafer structure
layer
inclined side
sidewall
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TWI727870B (zh
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賴俊諺
陳家湘
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精材科技股份有限公司
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Abstract

一種晶片結構包含第一基板、第二基板、導電通道與重佈線層。第一基板具有第一傾斜側壁。第二基板位於第一基板的下表面上，且具有上部與下部。下部凸出上部。上部位於第一基板與下部之間。上部具有第二傾斜側壁，且第一傾斜側壁與第二傾斜側壁的斜率大致相同。導電通道位於下部中。重佈線層從第一基板的上表面依序沿第一傾斜側壁與第二傾斜側壁延伸至第二基板之下部的上表面，且電性連接導電通道。

Description

晶片結構及其製造方法
本案是有關於一種晶片結構與一種晶片結構的製造方法。
晶片結構可具有堆疊的晶片，且此晶片結構的上表面與下表面可能需與其他裝置電性連接，因此在晶片結構的上表面與下表面可先形成裸露導電墊的通孔，接著便可分別在晶片結構的上表面與下表面形成電性連接導電墊的重佈線層，以於後續製程電性連接其他裝置。前述晶片結構的上表面為上層晶片的上表面，下表面為下層晶片的下表面。此外，上層晶片的導電墊位於上層晶片的下表面，下層晶片的導電墊位於下層晶片的上表面，可在接合製程中電性連接不同晶片的導電墊。
然而，通孔的深寬比(Aspect ratio)與晶片的厚度有關。當選用的晶片厚時，通孔的深寬比大(例如大於2)，重佈線層在轉折處容易斷線。如此一來，晶片結構其包含的晶片厚度將會有所侷限，不利於設計。此外，通孔的深寬比大，雖然可採用雷射鑽孔的方式形成，但也容易對導電墊造成損傷。
本發明之一技術態樣為一種晶片結構。
根據本發明一實施方式，一種晶片結構包含第一基板、第二基板、導電通道與重佈線層。第一基板具有第一傾斜側壁。第二基板位於第一基板的下表面上，且具有上部與下部。下部凸出上部。上部位於第一基板與下部之間。上部具有第二傾斜側壁，且第一傾斜側壁與第二傾斜側壁的斜率大致相同。導電通道位於下部中。重佈線層從第一基板的上表面依序沿第一傾斜側壁與第二傾斜側壁延伸至第二基板之下部的上表面，且電性連接導電通道。
在本發明一實施方式中，上述晶片結構更包含接合層。接合層位於第一基板與第二基板之間，且接合層的側面接觸重佈線層。
在本發明一實施方式中，上述第一基板、第二基板與接合層定義出空腔。
在本發明一實施方式中，上述接合層具有傾斜側面。晶片結構更包含絕緣層。絕緣層位於導電通道與第二基板之間、第二基板的下表面上、重佈線層與第一基板之間、第一基板的上表面上、第一傾斜側壁上、接合層的傾斜側面上及第二傾斜側壁上。
在本發明一實施方式中，上述接合層具有傾斜側面。晶片結構更包含表面保護層。表面保護層位於第一基板的上表面上、重佈線層上、第一傾斜側壁上、接合層的傾斜側面上、第二傾斜側壁上及第二基板的下部上。
在本發明一實施方式中，上述第一基板具有導電墊，且導電墊的側壁接觸重佈線層。
在本發明一實施方式中，上述晶片結構更包含接合層。接合層位於第一基板與第二基板之間，且第一基板的導電墊位於接合層上。
在本發明一實施方式中，上述第二基板具有導電墊，且導電墊的側壁接觸重佈線層。
在本發明一實施方式中，上述晶片結構更包含接合層。接合層位於第一基板與第二基板之間，且接合層位於第二基板的導電墊上。
在本發明一實施方式中，上述第一基板與第二基板各具有導電墊，晶片結構更包含接合層。接合層位於兩導電墊與重佈線層之間。
在本發明一實施方式中，上述重佈線層為階梯狀。
在本發明一實施方式中，上述重佈線層具有兩水平部與傾斜部，傾斜部的兩端分別鄰接兩水平部。
在本發明一實施方式中，上述重佈線層的兩水平部分別位於第一基板的上表面與下部的上表面，傾斜部位於第一傾斜側壁與第二傾斜側壁上。
在本發明一實施方式中，上述在下部的上表面上的水平部接觸導電通道的上表面。
本發明之一技術態樣為一種晶片結構的製造方法。
根據本發明一實施方式，一種晶片結構的製造方法包含在第一基板上接合第二基板；形成開口於第二基板中；形成導電通道於第二基板的開口中；形成溝槽於第一基板與第二基板中，使導電通道從溝槽裸露，第一基板具有第一傾斜側壁，第二基板具有第二傾斜側壁，且第一傾斜側壁與第二傾斜側壁的斜率大致相同；以及形成重佈線層，其從第一基板的上表面依序沿第一傾斜側壁與第二傾斜側壁延伸至第二基板之下部的上表面，且電性連接導電通道。
在本發明一實施方式中，上述導電通道是以電鍍或化學鍍的方式形成。
在本發明一實施方式中，上述晶片結構的製造方法更包含形成導電通道後，接合第二基板於載體。
在本發明一實施方式中，上述晶片結構的製造方法更包含形成重佈線層後，從第二基板移除載體。
在本發明一實施方式中，上述溝槽是以刀具切割第一基板與第二基板的方式形成。
在本發明一實施方式中，上述晶片結構的製造方法更包含形成該重佈線層後，沿溝槽切割第二基板，其中依照第二基板切割的厚度，第二基板的側壁形狀為直立狀或階梯狀。
在本發明上述實施方式中，由於第一基板與第二基板接合後，可於第一基板與第二基板中形成溝槽，因此第二基板的下部中的導電通道可從溝槽裸露，且溝槽的形成可一併產生第一基板的第一傾斜側壁與第二基板的第二傾斜側壁。如此一來，後續形成的重佈線層可從第一基板的上表面依序沿第一傾斜側壁與第二傾斜側壁延伸至第二基板之下部的上表面，進而電性連接導電通道。本揭露的晶片結構的導電通道只位在第二基板的下部中，深寬比可有效降低。此外，由於重佈線層是在第一傾斜側壁與第二傾斜側壁上延伸，因此第一基板的厚度與第二基板的厚度不影響深寬比，對於設計上來說有所助益。
以下將以圖式揭露本發明之複數個實施方式，為明確說明，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
第1圖繪示根據本發明一實施方式之晶片結構100的剖面圖。晶片結構100包含第一基板110、第二基板120、導電通道130與重佈線層140。第一基板110具有相對的下表面111與上表面112，且具有鄰接下表面111與上表面112的第一傾斜側壁113。第二基板120位於第一基板110的下表面111上，且具有上部124與下部125。第二基板120的下部125凸出上部124，且下部125的寬度大於上部124。第二基板120的上部124位於第一基板110與第二基板120的下部125之間。第二基板120的上部124具有第二傾斜側壁123，且第一傾斜側壁113與第二傾斜側壁123的斜率大致相同。
導電通道130位於第二基板120的下部125中。重佈線層140從第一基板110的上表面112依序沿第一傾斜側壁113與第二傾斜側壁123延伸至第二基板120之下部125的上表面128，且電性連接導電通道130。
在本實施方式中，第一基板110與第二基板120的材質可以包含矽，可具有感測裝置或內部線路。導電通道130的材質可以包含銅，可採用電鍍或化學鍍(包含種子層濺鍍及線路設計所需黃光製程)的方式形成。重佈線層140的材質可以包含鋁或銅，可採用濺鍍方式形成。此外，重佈線層140還可包含在第一基板110之上表面112上的焊墊部146。晶片結構100還可包含在第二基板120之下表面121上的焊墊部132。焊墊部132與焊墊部146可用來設置導電結構(如錫球)或電性連接其他電子裝置(如電路板、晶片等)，因此晶片結構100具有雙面電性連接之功效。
由於晶片結構100的重佈線層140可從第一基板110的上表面112依序沿第一傾斜側壁113與第二傾斜側壁123延伸至第二基板120之下部125的上表面128，進而電性連接導電通道130，因此重佈線層140不受傳統通孔的寬深比影響。本揭露的晶片結構100的導電通道130只位在第二基板120的下部125中，其深寬比可有效降低。此外，由於重佈線層140是在第一傾斜側壁113與第二傾斜側壁123上延伸，因此第一基板110的厚度與第二基板120的厚度不影響深寬比，對於設計上來說有所助益。舉例來說，設計者可選用較厚的第一基板110的與第二基板120而能避免重佈線層140斷線。
在本實施方式中，重佈線層140為階梯狀。具體而言，重佈線層140具有兩水平部142a、142b與傾斜部144，傾斜部144的兩端分別鄰接兩水平部142a、142b。傾斜部144與水平部142a之間夾鈍角θ1，且傾斜部144與水平部142b之間夾鈍角θ2。相似地，第一基板110之上表面112與第一傾斜側壁113之間夾鈍角θ1，且第二基板120之第二傾斜側壁123與下部125的上表面128之間夾鈍角θ2。
重佈線層140的兩水平部142a、142b分別位於第一基板110的上表面112與下部125的上表面128，傾斜部144位於第一傾斜側壁113與第二傾斜側壁123上。在第二基板120之下部125的上表面128上的水平部142b接觸導電通道130的上表面。經由上述設計，重佈線層140與導電通道130可將訊號從晶片結構100的上側傳輸到下側，或從晶片結構100的下側傳輸到上側，且重佈線層140不易斷裂。
在本實施方式中，晶片結構100更包含接合層150。接合層150位於第一基板110的下表面111與第二基板120的上表面122之間，且接合層150的側面接觸重佈線層140。
應瞭解到，已敘述過的元件連接關係、材料與功效將不再重複贅述，合先敘明。在以下敘述中，將說明其他形式的晶片結構。
第2圖繪示根據本發明另一實施方式之晶片結構100a的剖面圖。晶片結構100a包含第一基板110、第二基板120、導電通道130、重佈線層140與接合層150a。與第1圖實施方式不同的地方在於，第一基板110、第二基板120與接合層150a定義出空腔C，且第一基板110具有導電墊116，第二基板120具有導電墊126。導電墊116的側壁117與導電墊126的側壁127接觸重佈線層140。此外，第一基板110的導電墊116位於接合層150a上，且接合層150a位於第二基板120的導電墊126上。如此一來，接合層150a位於兩導電墊116、126與重佈線層140之間。
在本實施方式中，由於第一基板110的導電墊116與第二基板120的導電墊126可利用重佈線層140電性連接，因此可選用無導電材料的接合層150a，不僅可降低成本，對於材料的選用更具彈性。
在以下敘述中，將詳細說明第1圖之晶片結構100的製造方法。
第3圖繪示根據本發明一實施方式之第二基板120接合於第一基板110後的剖面圖。第4圖繪示第3圖之第二基板120形成導電通道130後的剖面圖。同時參閱第3圖與第4圖，首先，可利用接合層150於第一基板110上接合第二基板120，使接合層150位於第一基板110與第二基板120之間。接著，可形成開口O於第二基板120中。在形成開口O後，可採電鍍的方式於第二基板120的開口O中形成導電通道130，並在第二基板120上形成焊墊部132，如第4圖所示。
第5圖繪示第4圖之第二基板120接合於載體210後的剖面圖。同時參閱第4圖與第5圖，待導電通道130形成後，可將第4圖的結構翻轉180度，並利用暫時接合層205(Temporary bonding layer)將第二基板120接合於載體210。載體210可於後續切割製程提供支撐力。暫時接合層205可利用照光、浸泡、或高溫方式使其黏性消失，但並不以上述方式為限。在其他實施方式中，若第一基板110與第二基板120有足夠厚度，接合載體210的步驟可以省略。
第6圖繪示第5圖之第一基板110與第二基板120中形成溝槽T後的剖面圖。待接合載體210後，可於第一基板110與第二基板120中形成溝槽T，使導電通道130從溝槽T裸露。溝槽T形成後，第一基板110具有第一傾斜側壁113，第二基板120具有第二傾斜側壁123，且第一傾斜側壁113與第二傾斜側壁123的斜率大致相同。在本實施方式中，溝槽T是以刀具切割第一基板110與第二基板120的方式形成。在其他實施方式中，溝槽T也可採蝕刻方式形成。
第7圖繪示第6圖之第一基板110與第二基板120上形成重佈線層140後的剖面圖。接著，可形成具有水平部142a、142b與傾斜部144的重佈線層140，其從第一基板110的上表面112依序沿第一傾斜側壁113與第二傾斜側壁123延伸至第二基板120之下部125的上表面128，使得重佈線層140可電性連接導電通道130。導電通道130只位在第二基板120的下部125，深寬比可有效降低。此外，由於重佈線層140是在第一傾斜側壁113與第二傾斜側壁123上延伸，因此第一基板110的厚度與第二基板120的厚度不影響深寬比，對於設計上來說有所助益。
第8圖繪示第7圖之第二基板120切割後的剖面圖。同時參閱第7圖與第8圖，待形成重佈線層140後，可從第二基板120的下表面121移除載體210及暫時接合層205。接著，可沿溝槽T(也就是沿線L)切割第二基板120，而得到多個晶片結構100。此外，可依照第二基板120所需切割的厚度，使第二基板120的側壁形狀為直立狀(如第8圖所示)或階梯狀(如下部125也具有傾斜側壁123的結構)。晶片結構100的詳細結構可參閱第1圖，不重覆贅述。
第9圖繪示根據本發明一實施方式之晶片結構100b的剖面圖。晶片結構100b包含第一基板110、第二基板120、導電通道130與重佈線層140。與第1圖實施方式不同的地方在於晶片結構100b更包含絕緣層160與表面保護層170。絕緣層160位於導電通道130與第二基板120之間、第二基板120的下表面121上、重佈線層140與第一基板110之間、第一基板110的上表面112上、第一傾斜側壁113上、接合層150的傾斜側面上及第二傾斜側壁123上。此外，表面保護層170位於第一基板110的上表面112上、重佈線層140上、第一傾斜側壁113上、接合層150的傾斜側面上、第二傾斜側壁123上及第二基板120的下部125上。在本實施方式中，表面保護層170覆蓋絕緣層160。
絕緣層160存在與否依照第一基板110與第二基板120之材質導電與否決定，如第1圖之晶片結構100不需絕緣層160。表面保護層170是否存在與後續封裝方式不同及導線(如重佈線層140)保護需求有關，如第1圖之晶片結構100不需表面保護層170。
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100,100a,100b:晶片結構 110:第一基板 111:下表面 112:上表面 113:第一傾斜側壁 116:導電墊 117:側壁 120:第二基板 121:下表面 122:上表面 123:第二傾斜側壁 124:上部 125:下部 126:導電墊 127:側壁 128:上表面 130:導電通道 132:焊墊部 140:重佈線層 142a,142b:水平部 144:傾斜部 146:焊墊部 150,150a:接合層 160:絕緣層 170:表面保護層 205:暫時接合層 210:載體 C:空腔 L:線 O:開口 T:溝槽 θ1,θ2:鈍角
第1圖繪示根據本發明一實施方式之晶片結構的剖面圖。 第2圖繪示根據本發明另一實施方式之晶片結構的剖面圖。 第3圖繪示根據本發明一實施方式之第二基板接合於第一基板後的剖面圖。 第4圖繪示第3圖之第二基板形成導電通道後的剖面圖。 第5圖繪示第4圖之第二基板接合於載體後的剖面圖。 第6圖繪示第5圖之第一基板與第二基板中形成溝槽後的剖面圖。 第7圖繪示第6圖之第一基板與第二基板上形成重佈線層後的剖面圖。 第8圖繪示第7圖之第二基板切割後的剖面圖。 第9圖繪示根據本發明一實施方式之晶片結構的剖面圖。
100:晶片結構
110:第一基板
111:下表面
112:上表面
113:第一傾斜側壁
120:第二基板
121:下表面
122:上表面
123:第二傾斜側壁
124:上部
125:下部
128:上表面
130:導電通道
132:導體
140:重佈線層
142a,142b:水平部
144:傾斜部
146:導體
150:接合層
O:開口
θ 1,θ 2:鈍角

Claims (20)

  1. 一種晶片結構，包含： 一第一基板，具有一第一傾斜側壁； 一第二基板，位於該第一基板的一下表面上，且具有一上部與一下部，其中該下部凸出該上部，該上部位於該第一基板與該下部之間，該上部具有一第二傾斜側壁，且該第一傾斜側壁與該第二傾斜側壁的斜率大致相同； 一導電通道，位於該下部中；以及 一重佈線層，從該第一基板的一上表面依序沿該第一傾斜側壁與該第二傾斜側壁延伸至該第二基板之該下部的一上表面，且電性連接該導電通道。
  2. 如請求項1所述的晶片結構，更包含： 一接合層，位於該第一基板與該第二基板之間，且該接合層的側面接觸該重佈線層。
  3. 如請求項2所述的晶片結構，其中該第一基板、該第二基板與該接合層定義出一空腔。
  4. 如請求項2所述的晶片結構，該接合層具有一傾斜側面，該晶片結構更包含： 一絕緣層，位於該導電通道與該第二基板之間、該第二基板的下表面上、該重佈線層與該第一基板之間、該第一基板的該上表面上、該第一傾斜側壁上、該接合層的該傾斜側面上及該第二傾斜側壁上。
  5. 如請求項2所述的晶片結構，該接合層具有一傾斜側面，該晶片結構更包含： 一表面保護層，位於該第一基板的該上表面上、該重佈線層上、該第一傾斜側壁上、該接合層的該傾斜側面上、該第二傾斜側壁上及該第二基板的該下部上。
  6. 如請求項1所述的晶片結構，其中該第一基板具有一導電墊，且該導電墊的側壁接觸該重佈線層。
  7. 如請求項6所述的晶片結構，更包含： 一接合層，位於該第一基板與該第二基板之間，且該第一基板的該導電墊位於該接合層上。
  8. 如請求項1所述的晶片結構，其中該第二基板具有一導電墊，且該導電墊的側壁接觸該重佈線層。
  9. 如請求項8所述的晶片結構，更包含： 一接合層，位於該第一基板與該第二基板之間，且該接合層位於該第二基板的該導電墊上。
  10. 如請求項1所述的晶片結構，其中該第一基板與該第二基板各具有一導電墊，該晶片結構更包含： 一接合層，位於該兩導電墊與該重佈線層之間。
  11. 如請求項1所述的晶片結構，其中該重佈線層為階梯狀。
  12. 如請求項1所述的晶片結構，其中該重佈線層具有兩水平部與一傾斜部，該傾斜部的兩端分別鄰接該兩水平部。
  13. 如請求項12所述的晶片結構，其中該重佈線層的該兩水平部分別位於該第一基板的該上表面與該下部的該上表面，該傾斜部位於該第一傾斜側壁與該第二傾斜側壁上。
  14. 如請求項12所述的晶片結構，其中在該下部的該上表面上的該水平部接觸該導電通道的上表面。
  15. 一種晶片結構的製造方法，包含： 在一第一基板上接合一第二基板； 形成一開口於該第二基板中； 形成一導電通道於該第二基板的該開口中； 形成一溝槽於該第一基板與該第二基板中，使該導電通道從該溝槽裸露，該第一基板具有一第一傾斜側壁，該第二基板具有一第二傾斜側壁，且該第一傾斜側壁與該第二傾斜側壁的斜率大致相同；以及 形成一重佈線層，其從該第一基板的一上表面依序沿該第一傾斜側壁與該第二傾斜側壁延伸至該第二基板之該下部的一上表面，且電性連接該導電通道。
  16. 如請求項15所述的晶片結構的製造方法，其中該導電通道是以電鍍或化學鍍的方式形成。
  17. 如請求項15所述的晶片結構的製造方法，更包含： 形成該導電通道後，接合該第二基板於一載體。
  18. 如請求項17所述的晶片結構的製造方法，更包含： 形成該重佈線層後，從該第二基板移除該載體。
  19. 如請求項15所述的晶片結構的製造方法，其中該溝槽是以刀具切割該第一基板與該第二基板的方式形成。
  20. 如請求項15所述的晶片結構的製造方法，更包含： 形成該重佈線層後，沿該溝槽切割該第二基板，其中依照該第二基板切割的厚度，該第二基板的側壁形狀為直立狀或階梯狀。
TW109125329A 2019-07-29 2020-07-27 晶片結構及其製造方法 TWI727870B (zh)

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