TW202044510A - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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TW202044510A
TW202044510A TW108126531A TW108126531A TW202044510A TW 202044510 A TW202044510 A TW 202044510A TW 108126531 A TW108126531 A TW 108126531A TW 108126531 A TW108126531 A TW 108126531A TW 202044510 A TW202044510 A TW 202044510A
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semiconductor die
layer
semiconductor
heat dissipation
dissipation structure
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TW108126531A
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English (en)
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TWI711134B (zh
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黃崑永
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力成科技股份有限公司
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Publication of TW202044510A publication Critical patent/TW202044510A/zh

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Abstract

本發明提供半導體封裝及其製造方法。半導體封裝包括半導體晶粒、包封體、重佈線層、聚合物圖案層以及散熱結構。半導體晶粒具有位於其主動側的導電接墊，且被包封體側向包封。重佈線層設置於半導體晶粒的主動側且延伸於包封體的前表面。重佈線層電性連接至多個導電接墊。聚合物圖案層設置於包封體的背離前表面的背面，且環繞半導體晶粒。散熱結構接觸於半導體晶粒的背離主動側的背側，且延伸至聚合物圖案層上。

Description

半導體封裝及其製造方法
本發明是有關於一種半導體封裝及其製造方法，且特別是有關於一種扇出(fan-out)型半導體封裝及其製造方法。
扇出型半導體封裝是將半導體晶粒的接點藉由重佈線層而重新分配至更大面積的一種封裝製程。換言之，扇出型半導體封裝可以更高的積集度(integration level)與更多的外部接點來封裝半導體元件。然而，在製造過程中，扇出型半導體封裝經常承受相當大的應力，並且這種應力可能導致翹曲(warpage)之問題。
本發明提供一種半導體封裝及其製造方法，使半導體封裝不易受到翹曲問題的影響。
根據本發明的一些實施例，本發明的半導體封裝包括半導體晶粒、包封體、重佈線層、聚合物圖案層以及散熱結構。半導體晶粒具有位於半導體晶粒的主動側的多個導電接墊。包封體側向包封半導體晶粒。重佈線層設置於半導體晶粒的主動側且延伸於包封體的前表面。重佈線層電性連接至多個導電接墊。聚合物圖案層設置於包封體的背離前表面的背面，且環繞半導體晶粒。散熱結構接觸於半導體晶粒的背離主動側的背側，且延伸至聚合物圖案層上。
在本發明的一些實施例中，聚合物圖案層與半導體晶粒之間具有非零間距。
在本發明的一些實施例中，聚合物圖案層的側壁實質上共面於半導體晶粒的側壁。
在本發明的一些實施例中，聚合物圖案層覆蓋半導體晶粒的周邊部分。
在本發明的一些實施例中，散熱結構直接接觸於半導體晶粒的背側。
在本發明的一些實施例中，散熱結構包括晶種層以及導電層。晶種層共形地形成於聚合物圖案層與半導體晶粒的背側上。導電層形成於晶種層上。
在本發明的一些實施例中，導電層的交疊於半導體晶粒的一部分具有第一厚度，導電層的覆蓋聚合物圖案層的另一部分具有第二厚度，且第一厚度大於第二厚度。
在本發明的一些實施例中，半導體封裝更包括設置於散熱結構上的散熱件。
在本發明的一些實施例中，半導體晶粒更具有多個導電柱，分別地設置於重佈線層與多個導電接墊的一者之間。
在本發明的一些實施例中，半導體晶粒更具有多個焊接點，分別地設置於重佈線層與多個導電柱的一者之間。
在本發明的一些實施例中，重佈線層的附接於半導體晶粒的表面具有凹陷，且半導體晶粒位於所述凹陷中。
在本發明的一些實施例中，半導體封裝更包括底部填充材料，側向環繞多個導電柱與多個焊接點。
在本發明的一些實施例中，半導體封裝更包括多個電性連接件，設置於重佈線層的背離半導體晶粒的表面，且電性連接至重佈線層。
根據本發明的一些實施例，半導體封裝的製造方法包括：提供半導體晶粒，其中半導體晶粒具有位於半導體晶粒的主動側的多個導電接墊；以包封體側向包封半導體晶粒。於半導體晶粒的主動側形成重佈線層，其中重佈線層覆蓋多個導電接墊且延伸於包封體的前表面；於包封體的背離前表面的背面形成聚合物圖案層，其中聚合物圖案層具有開口，暴露出半導體晶粒的背離主動側背側的開口；於半導體晶粒的背側，其中散熱結構接觸於半導體晶粒，且延伸覆蓋於聚合物圖案層上。
在本發明的一些實施例中，形成重佈線結構的步驟在形成聚合物圖案層的步驟與形成散熱結構的步驟之前。
在本發明的一些實施例中，半導體封裝的製造方法更包括：在以包封體側向包封半導體晶粒之前，將半導體晶粒的背側附接於第一載體；在形成重佈線層之後且於形成散熱結構之前，將第二載體附接於重佈線層並將第一載體從半導體晶粒與包封體分離；在形成散熱結構之後，將第二載體從重佈線層分離。
在本發明的一些實施例中，形成重佈線層的步驟在形成聚合物圖案層的步驟與形成散熱結構的步驟之後。
在本發明的一些實施例中，半導體封裝的製造方法更包括：在以包封體側向包封半導體晶粒之前，將半導體晶粒的主動側附接於第一載體；在形成散熱結構之後且於形成重佈線層之前，將第二載體附接於散熱結構並將第一載體從半導體晶粒與包封體分離；以及在形成重佈線層之後，將第二載體從散熱結構分離。
根據本發明的一些實施例，半導體封裝的製造方法包括：於載體上形成重佈線層；將半導體晶粒附接於重佈線層上，其中半導體晶粒具有在半導體晶粒的主動側的多個導電柱，且多個導電柱附接且電性連接至重佈線層；以包封體側向包封半導體晶粒；於包封體的背離重佈線層的背面上形成聚合物圖案層，其中聚合物圖案層具有開口，暴露出半導體晶粒的背離主動側的背側；於半導體晶粒的背側上形成散熱結構，其中散熱結構接觸於半導體晶粒，且延伸於聚合物圖案層上；以及移除載體。
在本發明的一些實施例中，半導體封裝的製造方法更包括：在附接半導體晶粒之前，於重佈線層的表面形成凹陷，其中經附接的半導體晶粒位於凹陷內；以及在附接半導體晶粒之後，形成側向環繞多個導電柱的底部填充材料。
基於上述，本發明實施例的半導體封裝包括被包封體側向包封的至少一半導體晶粒。重佈線層設置於半導體晶粒的主動側與包封體的前表面，而聚合物圖案層形成於包封體的背面。因此，包封體位於重佈線層與聚合物圖案層之間。包封體的熱膨脹係數（CTE）可以大於或小於聚合物圖案層與重佈線層中的介電層的熱膨脹係數。從而，由包封體與聚合物圖案層之間的熱膨脹係數失配所產生的應力以及由包封體和介電層之間的熱膨脹係數失配所產生的應力可至少部分地相互抵消。於是，可以減少半導體封裝中的總應力，使得半導體封裝不易有翹曲的問題。此外，聚合物圖案層形成在包封體的環繞半導體晶粒的一部分上，且可視為具有交疊於半導體晶粒的開口。如此一來，上覆於聚合物圖案的散熱結構可以直接接觸半導體晶粒。因此，半導體晶粒產生的熱量可以有效地經由散熱結構而逸散。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1是依照本發明一些實施例繪示的半導體封裝的製造流程圖。圖2A至圖2J根據本發明一些實施例繪示在半導體封裝的製造過程期間的各階段的結構的剖視示意圖。
請參照圖1與圖2A，執行步驟S100，以提供半導體晶粒100。半導體晶粒100可為自裝置晶圓(device wafer)單體化而得到的半導體晶粒。在一些實施例中，半導體晶粒100可以是邏輯積體電路(integrated circuit，IC)晶粒、記憶積體電路晶粒(舉例來說，動態隨機存取記憶體(dynamic random access memory，DRAM)晶粒、系統晶片(system-on-chip，SOC)晶粒、類比積體電路晶粒、專用積體電路(application-specific integrated circuit，ASIC)晶粒等。半導體晶粒100包括半導體基底102。半導體基底102可以是半導體晶圓絕緣層上覆半導體(semiconductor-on-insulator，SOI)晶圓的一部分。在半導體基底102內及/或半導體基底102上方形成有多個電子元件（未繪示）。電子元件包括主動裝置與被動裝置。舉例而言，主動裝置可以包括電晶體、二極體、其類似者或其組合，而被動裝置可以包括電阻器、電容器、其類似者或其組合。另外，半導體基底102上可設置有內連線層（未繪示）。內連線層用於連接形成在半導體基底102內及/或半導體基底102上方的電子元件。內連線層上可依序地形成有多個導電接墊104（例如是鋁接墊）與鈍化層106（例如是氧化矽層、氮化矽層或其類似者）。鈍化層106具有多個開口，分別地暴露出一導電接墊104。在一些實施例中，多個導電柱108（例如是銅柱）分別設置於導電接墊104的暴露部分上。半導體晶粒100的導電柱108所在的一側稱為主動側AS1，而半導體晶粒100的背離主動側AS1的另一側則稱為背側BS1。
請參照圖1與圖2B，執行步驟S102，以將多個半導體晶粒100附接於第一載體CA1-1上。經附接的半導體晶粒100可彼此側向地分離。雖然在圖2B僅描繪出兩個經附接的半導體晶粒100，但本領域中具有通常知識者可將單一半導體晶粒100或三個以上的半導體晶粒100附接於第一載體CA1-1上，本發明不限於此。此外，也可以將一或多個被動裝置（未繪示）附接於第一載體CA1-1上。在一些實施例中，半導體晶粒100的背側BS1附接於第一載體CA1-1，而半導體晶粒100的主動側AS1背離第一載體CA1-1。舉例而言，第一載體CA1-1為玻璃載體。在一些實施例中，於第一載體CA1-1的將被半導體晶粒100附接的表面上預先形成附著層110。在一些實施例中，附著層110為單一材料層，例如是光熱轉換（light to heat conversion，LTHC）離型層、熱離型層或雷射離型層（laser release layer）。在其他實施例中，附著層110可為多層結構，包括在第一載體CA1-1上依序形成的離型層和晶粒貼合膜（未繪示）。
請參照圖1與圖2C，執行步驟S104，以包封體112側向包封半導體晶粒100。在一些實施例中，包封材料（未繪示）起初包封且覆蓋半導體晶粒100，接著對包封材料執行平坦化製程，以暴露出半導體晶粒100的導電柱108並形成包封體112。在特定實施例中，在平坦化製程期間，可部分地去除導電柱108的頂部。另外，在執行平坦化製程之後，導電柱108的頂部表面可實質上共面於包封體112的前表面112a。另一方面，包封體112的背離前表面112a的背面112b可共面於半導體基底102的背面。半導體基底102的背面位於半導體晶粒100的背側BS1。在一些實施例中，包封體112的材料可包括環氧樹脂(epoxy resin)、聚醯亞胺(polyimide)、矽氧樹脂(silicone)、其類似者或者其組合，且平坦化製程可為化學機械拋光（chemical-mechanical polishing）製程、蝕刻製程或研磨製程。
請參照圖1、圖2C與圖2D，執行步驟S106，以在半導體晶粒100的主動側AS1與包封體112的前表面112a上形成重佈線層114。重佈線層114覆蓋半導體晶粒100的導電柱108的頂部表面，且延伸於包封體112的前表面112a上。在一些實施例中，重佈線層114包括多層介電層116的堆疊，且包括形成於此介電層116堆疊中的重佈線單元118。重佈線單元118電性連接至半導體晶粒100的導電柱108，且分布範圍向上擴展到包括半導體晶粒100與包封體112的重組晶圓的面積。至少一重佈線單元118可電性連接於側向相鄰的半導體晶粒100的導電柱108之間，且作為晶粒對晶粒(die-to-die)的內連線。多個重佈線單元118可分別包括導電跡線、導電通孔或其組合。導電跡線沿著實質上平行於介電層116的延伸方向的一個或多個方向延伸，而導電通孔貫穿至少一介電層116並電性連接至一導電跡線。在一些實施例中，介電層116的材料包括聚合物材料，而重佈線單元118的材料包括金屬或金屬合金。舉例而言，聚合物材料包括聚醯亞胺、聚苯並唑（polybenzoxazole，PBO）、苯環丁烯（benzocyclobutene，BCB）、其類似者或其組合，且金屬/金屬合金包括銅、鎳、鈦、其類似者或其組合。在替代實施例中，介電層116是無機絕緣層，並且由例如氧化矽、氮化矽或其類似者構成。
在一些實施例中，於形成重佈線層114之後，移除最頂部介電層116的一些部分，以形成多個開口。此些開口暴露出重佈線層114的一些重佈線單元118。隨後，可分別在暴露出的重佈線單元118上形成焊球接墊（ball pad）129。在一些實施例中，焊球接墊129更可延伸至開口外。焊球接墊129的材料可包括鉻、銅、鈦、鎢、鎳、鋁、金、其類似者或其組合。
請參照圖1與圖2E，執行步驟S108，以將第二載體CA1-2附接於重佈線層114與焊球接墊129，且將第一載體CA1-1從包封體112與半導體晶粒100分離。在一些實施例中，第二載體CA1-2將附接於重佈線層114與焊球接墊129的表面上預先形成有附著層120。舉例而言，附著層120可以是光熱轉換離型層、熱離型層或雷射離型層。另一方面，在預先形成於第一載體CA1-1上的附著層110是光熱轉換離型層、熱離型層或雷射離型層的實施例中，附著層110在暴露於光、熱或雷射時失去其附著性，使得第一載體CA1-1從半導體晶粒100與包封體112分離。在分離第一載體CA1-1之後，暴露出半導體晶粒100的背側BS1與包封體112的背面112b。
請參照圖1、圖2E以及圖2F，執行步驟S110，以翻轉圖2E所示的結構，並在包封體112的背面112b上形成聚合物圖案層122。聚合物圖案層122覆蓋包封體112的環繞半導體晶粒100的一部分。另一方面，半導體晶粒100的背側BS1與包封體112的位於半導體晶粒100之間的部分仍然維持暴露出來的狀態。換句話說，半導體晶粒100與包封體112的位於半導體晶粒100之間的部分被上方的聚合物圖案層122環繞，且目前處於暴露出的狀態。聚合物圖案層122可被視為具有交疊於半導體晶粒100以及包封體112的位於半導體晶粒100之間的部分的開口W1。在一些實施例中，如圖2F所示，聚合物圖案層122並未交疊於半導體晶粒100，且開口W1的邊界與最接近半導體晶粒100之間具有非零間距SP1。聚合物圖案層122的材料可相異於包封體112的材料，且可與重佈線層114的介電層116（如圖2D所示）的材料相同。舉例而言，聚合物圖案層122可由聚醯亞胺、聚苯並唑、苯環丁烯、環氧樹脂、其類似者或其組合構成。另外，聚合物圖案122的形成方法可包括首先在重組晶圓的背離重佈線層114的背側上形成毯覆的聚合物層（未顯出），接著圖案化此毯覆的聚合物層以形成聚合物圖案層122。聚合物圖案層122具有暴露出半導體晶粒100與包封體112的位於半導體晶粒100之間的部分的開口W1。在一些實施例中，聚合物圖案層122經形成為網孔圖案（mesh pattern），且具有多個開口W1。多個開口W1分別暴露出重組晶圓中的一或多個半導體晶粒100。在替代實施例中，聚合物圖案層122經形成為環形圖案，且環繞重組晶圓中的所有半導體晶粒100。
請參照圖1、圖2F以及圖2G，執行步驟S112，以在當前結構上形成散熱結構124。散熱結構124可視為填入聚合物圖案層122的開口W1，且散熱結構124更沿著聚合物圖案層122的側壁與頂部表面延伸至聚合物圖案層122上。如此一來，散熱結構124覆蓋半導體晶粒100與包封體112的位於半導體晶粒100之間的部分，並在側向上以及在垂直方向上接觸於聚合物圖案層122。在一些實施例中，散熱結構124直接接觸半導體晶粒100的背側BS1與包封體112的位於半導體晶粒100之間的部分。在聚合物圖案層122與半導體晶粒100之間具有非零間距的實施例中，散熱結構124更覆蓋包封體112的環繞半導體晶粒100的一部分。在一些實施例中，散熱結構124包括晶種層126與形成於晶種層126上的導電層128。散熱結構124的形成方法包括藉由例如是物理氣相沉積（physical vapor deposition，PVD）製程而將晶種層126共形地形成在如圖2F所示的封裝結構上，以使晶種層126覆蓋聚合物圖案層122、半導體晶粒100的背側BS1以及包封體112的位於半導體晶粒100之間的部分。接著，藉由例如是鍍覆製程在晶種層126上形成導電層128。在一些實施例中，導電層128填充聚合物圖案層122的開口W1，且更延伸到聚合物圖案層122上。此外，可藉由非共形方式來形成導電層128，以使導電層128的交疊於半導體晶粒100的部分之第一厚度T1可以大於導電層128的覆蓋聚合物圖案層122的另一部分之第二厚度T2。作為替代地，可藉由共形的方式形成導電層128，且導電層128可具有實質上均一的厚度。晶種層126的材料可以包括銅、鈦、其類似者或其組合，而導電層128的材料可包括銅。
請參照圖1、圖2G、圖2H與圖2I，執行步驟S114，以分離第二載體CA1-2，且於重佈線層114的背離半導體晶粒100的一側上形成多個電性連接件130。在分離第二載體CA1-2之前，如圖2G所示的封裝結構可經翻轉，且可使散熱結構124附接於膠帶或另一載體（未繪示）。在形成於第二載體CA1-2上的附著層120是光熱轉換離型層、熱離型層或雷射離型層的實施例中，附著層120在暴露於光、熱或雷射時失去其附著性，而使第二載體CA1-2自重佈線層114分離。請參照圖2H，在分離第二載體CA1-2之後，暴露出重佈線層114的背離包封體112的表面（亦即如圖2H所示的最頂層介電層116的表面）以及焊球接墊129。在分離第二載體CA1-2之後，可對當前封裝結構執行單體化製程。每個單體化封裝結構可包含被包封體112側向包封的一或多個半導體晶粒100（舉例來說，如圖2H所示的兩個半導體晶粒100）。在每個單體化封裝結構中的半導體晶粒100被聚合物圖案層122環繞，且接觸於散熱結構124。舉例而言，單體化製程包括切割製程、鋸切製程或雷射燒蝕製程。隨後，如圖2I所示，可在多個焊球接墊129上形成電性連接件130。在形成有焊球接墊129的實施例中，焊球接墊129位於電性連接件130與重佈線層114之間。在一些實施例中，電性連接件130可包括微凸塊(micro-bumps)、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、球柵陣列封裝（ball grid array，BGA）球、焊球或其類似者。
請參照圖1與圖2J，執行步驟S116，將散熱件132附接於散熱結構124上。在一些實施例中，在附接散熱件132之前，分離附接於散熱結構124的膠帶或載體（未繪示），且可於散熱結構124的即將附接於散熱件132的表面上形成熱介面材料（thermal interfacial material，TIM）層134。如圖2J所示，在一些實施例中，散熱件132具有基部132a以及由基部132a突出的多個突出部132b。突出部132b可是鰭狀結構或柱狀結構。在替代實施例中，散熱件132是金屬板，且不具有突出部分。散熱件132的材料可包括銅、鋁或其他金屬，且熱介面材料層134的材料可包括包含如金屬或金屬氧化物顆粒的導電材料的聚合物材料（舉例來說，導熱油脂或導熱膠帶）。
根據上述實施例，單體化步驟在分離第二載體CA1-2的步驟之後，而在形成電性連接件130的步驟之前。然而，在替代實施例中，形成電性連接件的步驟130可在分離第二載體CA1-2的步驟與單體化步驟之前。本領域中具有通常知識者可調整這些步驟的順序，本發明不限於此。
至止，已形成半導體封裝10。半導體封裝10中的半導體晶粒100被包封體112側向地包封。重佈線層114設置於半導體晶粒100的主動側AS1與包封體112的前表面112a，而聚合物圖案層122形成於包封體112的背面112b。換言之，包封體112設置於重佈線層114與聚合物圖案層122之間。包封體112的熱膨脹係數（coefficient of thermal expansion，CTE）可以大於或小於聚合物圖案層122與重佈線層114中的介電層116的熱膨脹係數。因此，包封體112與介電層116之間的熱膨脹係數失配（mismatch）所造成的應力可以至少部分地被包封體112與聚合物圖案層122之間的熱膨脹係數失配所造成的應力抵消。因此，可以減少半導體封裝10中的總應力，使得半導體封裝10不易有翹曲的問題。舉例而言，包封體112由具有填料（filler）的環氧模塑化合物（epoxy molding compound，EMC）構成，並且具有5ppm/℃至20ppm/℃的熱膨脹係數。另一方面，聚合物圖案層122與重佈線層114的介電層116由聚醯亞胺構成，並且具有50ppm/℃至60ppm/℃的熱膨脹係數。此外，聚合物圖案層122形成於包封體112的環繞半導體晶粒100的部分上，且可以被視為具有交疊於半導體晶粒100以及包封體112的位於半導體晶粒100之間的部分之開口W1（如圖2F所示）。如此一來，上覆於聚合物圖案層122的散熱結構124可接觸於半導體晶粒100的背側BS1與包封體112的位於半導體晶100之間的部分。因此，由半導體晶粒100產生的熱量可有效地經由散熱結構124而逸散。
圖3是依照本發明一些實施例繪示的半導體封裝的剖視示意圖。
請參照圖2J與圖3，圖3中所示的半導體封裝10a類似於圖2J所示的半導體封裝10。以下僅描述兩者之間的差異，而相同或相似的部分則不再贅述。如圖3所示，在一些實施例中，聚合物圖案層122更延伸到半導體晶粒100的背側BS1上。在這些實施例中，聚合物圖案層122覆蓋半導體晶粒100的一些周邊部分，而半導體晶粒100的此些周邊部分不與散熱結構124直接接觸。藉由增加聚合物圖案層122的面積，包封體112與重佈線層114的介電層116之間的熱膨脹係數失配所產生的應力可更大程度地被包封體112與聚合物圖案層122之間的熱膨脹係數失配所產生的應力所抵消。因此，可進一步減少半導體封裝10a中的總應力。
在替代實施例（未繪示）中，聚合物圖案層122的開口W1的邊界實質上與相鄰半導體晶粒100的側壁共面。在這些替代實施例中，聚合物圖案層122的被散熱結構124填充之開口W1延伸至半導體晶粒100的分佈區域之邊界。
圖4是依照本發明一些實施例繪示的半導體封裝的製造流程圖。圖5A至圖5I是圖4所示的半導體封裝的製造過程期間的各階段的結構的剖視示意圖。參照圖4與圖5A至圖5I所描述的實施例類似於參照圖1與圖2A至圖2J所描述的實施例。以下僅描述兩者之間的差異，而相同或相似的部分則不再贅述。另外，相似的標號被指定為類似的組件。
請參照圖4與圖5A，執行步驟S200，以提供半導體晶粒200。半導體晶粒200類似於圖2A中所示的半導體晶粒100，除了半導體晶粒200在主動側AS2可不具有導電柱（舉例來說，圖2A中所示的導電柱108）。如圖5A所示，設置於半導體基底202上的導電接墊204暴露於形成在導電接墊204上的鈍化層206的開口中，且並未被導電柱覆蓋。另一方面，半導體晶粒200的背離主動側AS2的一側稱為背側BS2。
請參照圖4、圖5A與圖5B，執行步驟S202，以將半導體晶粒200附接於第一載體CA2-1上。半導體晶粒200的主動側AS2附接於第一載體CA2-1，而半導體晶粒200的背側BS2背離第一載體CA2-1。在一些實施例中，在第一載體CA2-1的即將附接於半導體晶粒200的表面上預先形成附著層210。附著層210例如為光熱轉換層、熱離型層或雷射離型層。在這些實施例中，經附接的半導體晶粒200的導電接墊204與鈍化層206接觸附著層210。應當注意的是，即使在圖5B中僅描繪了單一半導體晶粒200，實際上可將多個半導體晶粒200附接於第一載體CA2-1上，且這些經附接的半導體晶粒200可彼此側向分離。此外，更可將一或多個被動裝置（未繪示）附接於第一載體CA2-1上。
請參照圖4與圖5C，執行步驟S204，而以包封體212側向包封經附接的半導體晶粒200。包封體212暴露出半導體晶粒200的背側BS2。在一些實施例中，包封體212的背面212b實質上共面於半導體基底202的背面。半導體基底202的背面位於半導體晶粒200的背側BS2處。另一方面，包封體212的前表面212a接觸於附著層210或第一載體CA2-1。應當注意的是，即使圖5C所描繪的包封體212僅側向包封單一半導體晶粒200，包封體212實際上可側向地包封多個半導體晶粒200。
請參照圖4與圖5D，執行步驟S206，以在包封體212的背面212b上形成聚合物圖案層222。聚合物圖案層222覆蓋包封體212的環繞半導體晶粒200的部分。聚合物圖案層122可視為具有交疊於半導體晶粒200的開口W2。在一些實施例中，聚合物圖案層222並未覆蓋半導體晶粒200，且聚合物圖案層222的開口W2之邊界與半導體晶粒200之間具有非零間距SP2。在替代實施例中，聚合物圖案層222更延伸到半導體晶粒200的背側BS2上，且覆蓋半導體晶粒200的周邊部分。在其他實施例中，聚合物圖案層222的開口W2之邊界實質上共面於半導體晶粒200的側壁。
之後，執行步驟S208，以在當前結構上形成散熱結構224。散熱結構224可視為填充於聚合物圖案層222的開口W2中，且散熱結構224更沿聚合物圖案層222的側壁與頂部表面延伸到聚合物圖案層222上。因此，散熱結構224覆蓋半導體晶粒200的背側BS2與聚合物圖案層222被散熱結構224覆蓋，且散熱結構224在側向上與垂直方向上接觸於聚合物圖案層222。在一些實施例中，散熱結構224與半導體晶粒200直接接觸，且由半導體晶粒200產生的熱量可經由散熱結構224而逸散。此外，在一些實施例中，散熱結構224包括晶種層226與導電層228。散熱結構224的形成方法可包括在半導體晶粒200與聚合物圖案層222上共形地形成晶種層228，且在晶種層226上形成導電層228。在一些實施例中，導電層228可具有實質上平坦的頂部表面。在這些實施例中，導電層228的填充於開口W2中的部分之厚度大於導電層228的位於開口W2外的另一部分之厚度。
請參照圖4與圖5E，執行步驟S210，以將第二載體CA2-2附接於散熱結構224上，且將第一載體CA2-1從包封體212與半導體晶粒200分離。在一些實施例中，預先在第二載體CA2-2的即將附接於散熱結構224的表面上預先形成例如是光電轉換離型層、熱離型層或雷射離型層的附著層220。另一方面，在形成於第一載體CA2-1上的附著層210是光熱轉換離型層、熱離型層或雷射離型層的實施例中，附著層210在暴露於光、熱或雷射時失去其附著性，而使第一載體CA2-1自半導體晶粒200和包封體212分離。在分離第一載體CA2-1之後，暴露出半導體晶粒200的主動側AS2與包封體212的前表面212a。
請參照圖4、圖5E與圖5F，執行步驟S212，以在半導體晶粒200的主動側AS2與包封體212的前表面212a上形成重佈層線214。在形成重佈線層214之前，如圖5E所示的結構可經翻轉，使得半導體晶粒200的主動側AS2與包封體212的前表面212a在目前的階段面向上方。在一些實施例中，重佈線層214包括多層介電層216的堆疊，且包括形成在介電層216堆疊中的重佈線單元218。重佈線單元218電性連接至半導體晶粒200的導電接墊206，且分布範圍向上擴展到包括半導體晶粒200與包封體212的重組晶圓的面積。
在一些實施例中，於形成重佈線層214之後，移除最頂部介電層216的一些部分，以形成多個開口。此些開口暴露出重佈線層114的一些重佈線單元218。隨後，可分別在暴露出的重佈線單元218上形成焊球接墊229。在一些實施例中，焊球接墊229更可延伸至開口外。
請參照圖4、圖5G與圖5H，執行步驟S214，以分離第二載體CA2-2，且於重佈線層214的背離半導體晶粒200的表面上形成電性連接件230。在分離第二載體CA2與形成電性連接件230之前，如圖5F所示的結構可經翻轉，且重佈線層214可附接於膠帶或另一個載體（未繪示）。在形成於第二載體CA2-2上的附著層220是光電轉換離型層、熱離型層或雷射離型層的實施例中，附著層220在暴露於光、熱或雷射時失去其附著性，以使第二載體CA2-2自散熱結構224分離。在分離第二載體CA2-2之後，可對當前封裝結構執行單體化製程。每個單體化封裝結構可包含被包封體212側向包封的一或多個半導體晶粒200（舉例來說，如圖5G所示的一個半導體晶粒200）。每個單體化封裝結構中的半導體晶粒200被上覆的聚合物圖案層222環繞，且接觸於散熱結構224。接著，請參照圖5H，分離附接於重佈線層214與焊球接墊229的膠帶或載體（未繪示）。，且在多個焊球接墊229上形成電性連接件230。在此些形成有焊球接墊229的實施例中，焊球接墊229位於電性連接件230與重佈線層214之間。
根據上述實施例，單體化步驟在分離第二載體CA2-2的步驟之後，而在形成電性連接件230的步驟之前。然而，在替代實施例中，形成電性連接件230的步驟可在分離第二載體CA2-2步驟與單體化步驟之前。本領域中具有通常知識者可以調整這些步驟的順序，本發明不限於此。
請參照圖4與圖5I，執行步驟S216，以將散熱件232附接於散熱結構224上。在一些實施例中，在附接散熱件232之前，可在散熱結構224的即將附接於散熱件232的表面上形成熱介面材料層234。
至此，已形成半導體封裝20。半導體封裝20的結構類似於圖2J中所示的半導體封裝10的結構，除了半導體封裝20的半導體晶粒200可不具有導電柱。關於半導體封裝20的製造過程，半導體晶粒200的主動側AS2附接於第一載體CA2-1（如圖5B所示），且形成聚合物圖案層222與散熱結構224（如圖5D所示）的步驟在形成重佈線層214的步驟之前（如圖5F所示）。另一方面，在半導體封裝10的製造過程期間，半導體晶粒100的背側BS1附接於第一載體CA1-1（如圖2B所示），且在形成聚合物圖案層122與散熱結構124的步驟（如圖2F與圖2G所示）在形成重佈線層114的步驟（如圖2D所示）之後。
圖6是依照本發明一些實施例繪示的半導體封裝的製造流程圖。圖7A至圖7G是圖6所示的半導體封裝的製造過程期間的各階段的結構的剖視示意圖。參照圖6與圖7A至圖7G所描述的實施例類似於參照圖1與圖2A至圖2J所描述的實施例。以下將描述兩者之間的差異，而相同或相似的部份則不再贅述。另外，相似的標號被指定為類似的組件。
請參照圖6與圖7A，執行步驟S300，以提供半導體晶粒300。半導體晶粒300類似於圖2A中所示的半導體晶粒100，除了半導體晶粒300在其主動側AS3處更具有焊接點SJ。如圖7A所示，導電接墊304與鈍化層306依序設置於半導體基底302上，且鈍化層306具有分別暴露出導電接墊304的開口。導電柱308分別設置於導電墊304的暴露部分上，且焊接點SJ分別設置於導電柱308上。在一些實施例中，焊接點SJ的材料包括錫、銀、銅或其合金。另一方面，半導體晶粒300的背離主動側AS3的一側被稱為背側BS3。
請參照圖6與圖7B，執行步驟S302，以提供第一載體CA3-1，且在第一載體CA3-1上形成重佈線層314。在一些實施例中，預先於第一載體CA3-1的即將形成有重佈線層314表面上形成例如是光熱轉換層、熱離型層或雷射離型層的附著層310。另外，在一些實施例中，重佈層線314包括多層介電層316的堆疊與形成於介電層316堆疊中的重佈線單元318。可移除最頂部的介電層316的一些部分，以形成暴露出一些最頂部的重佈線單元318的多個開口。如此一來，重佈線單元318的這些暴露部分將可以電性連接至於後續步驟中（如圖7C所示）附接於重佈線層314上的半導體晶粒300（與未繪示的被動裝置）。另外，最頂部介電層316中的這些開口可以被視為重佈線層314的頂部表面的凹陷。
請參照6圖、圖7A與圖7C，執行步驟S304，以將多個半導體晶粒300附接於重佈線層314上。即使圖7C僅繪示出兩個半導體晶粒300被附接於重佈線層314上，單一半導體晶粒300或多於三個的半導體晶粒300可被附接於重佈線層314上。此外，也可將一或多個被動裝置附接於重佈線層314上。經附接的半導體晶粒300（與被動裝置）可電性連接至重佈線單元318的先前暴露於開口中的部分。半導體晶粒300的主動側AS3經由焊接點SJ而與重佈線層314接觸，而半導體晶粒300的背側BS3背離重佈線層314。在一些實施例中，以底部填充材料UF填充半導體基底302與重佈線層314之間的間隙。在這些實施例中，底部填充材料UF側向地環繞導電柱308與焊接點SJ。底部填充材料UF的材料可包括液態環氧樹脂、可變形凝膠、矽橡膠或其類似者。在一些實施例中，底部填充材料UF可為含有填充材料（舉例來說，氧化物、氮化物、碳化物或其類似者）的聚合物層。
請參照圖6與圖7D中，執行步驟S306，而以包封體312側向包封半導體晶粒300。包封體312暴露出半導體晶粒300的背側BS3。在一些實施例中，包封體312的背面312b實質上共面於半導體基底203的背面。半導體基底203的所述背面位於半導體晶粒300的背側BS3處。另一方面，包封體312的前表面312a接觸於重佈線層314。
請參照圖6與圖7E，執行步驟S308，以在包封體312的背面312b上形成聚合物圖案層322。聚合物圖案層322覆蓋包封體312的環繞每個半導體晶粒300的部分。聚合物圖案層322可視為具有多個開口W3。多個開口W3分別交疊於一半導體晶粒300。在一些實施例中，聚合物圖案層322並未覆蓋半導體晶粒300，且每個開口W3的邊界與此開口W3中的半導體晶粒300之間具有非零間距SP3。在替代實施例中，聚合物圖案層322更延伸到半導體晶粒300的背側BS3上，且覆蓋半導體晶粒300的周邊部分。在其他實施例中，每個開口W3的邊界實質上共面於位在其中的半導體晶粒300的側壁。
隨後，執行步驟S310，以在當前結構上形成散熱結構324。散熱結構324可視為填充聚合物圖案層322的開口W3，且散熱結構324更延伸到聚合物圖案層322上。如此一來，散熱結構324覆蓋半導體晶粒300的背側BS3與聚合物圖案層322，且散熱結構324在側向上與垂直方向上接觸於聚合物圖案層322。在一些實施例中，散熱結構324直接接觸於半導體晶粒300，以使半導體晶粒300產生的熱量有效地經由散熱結構324而逸散。此外，在一些實施例中，散熱結構324包括晶種層326與導電層328。晶種層326共形地形成於半導體晶粒300與聚合物圖案層322上，且導電層328形成於晶種層326上。在一些實施例中，導電層328可具有實質上平坦的頂部表面。在這些實施例中，導電層328的填充在開口W3中的一部分之厚度大於導電層328的位於開口W3外的另一部分之厚度。
請參照圖6、圖7E與圖7F，執行步驟S312，以分離第一載體CA3-1，且於重佈線層314的暴露表面上形成多個電性連接件130。在第一載體CA3-1上所形成的附著層310是光熱轉換離型層、熱離型層或雷射離型層的實施例中，附著層310在暴露於光、熱或雷射時失去其附著性，以使第一載體CA3-1自重佈線層314分離。如此一來，可暴露出重佈線層314（例如是暴露出重佈線層314的如圖7F所示的最底部之絕緣層316與重佈線單元318）。在分離第一載體CA3-1之後，可對當前封裝結構執行單體化製程。每個單體化封裝結構可包含被包封體312側向包封的一或多個半導體晶粒300（舉例來說，如圖7F所示的一個半導體晶粒300）。在單體化封裝結構中的每個半導體晶粒300被上覆的聚合物圖案層322環繞，且接觸於散熱結構324。隨後，可在暴露出的重佈線單元318之表面上設置電性連接件330。
根據上述實施例，單體化步驟在分離第一載體CA3-1的步驟之後，並在形成電性連接件330的步驟之前。然而，在替代實施例中，形成電性連接件330的步驟可在分離第一載體CA3-1的步驟與單體化步驟之前。本領域中具有通常知識者可以調整這些步驟的順序，本發明不限於此。
請參照圖6與圖7G，執行步驟S314，並將散熱件332附接於散熱結構224上。在一些實施例中，在附接散熱件332之前，可在散熱結構324的即將附接於散熱件332的表面上形成熱介面材料層334。
至此，已形成半導體封裝30。半導體封裝30類似於圖2J所示的半導體封裝10，除了半導體封裝30的半導體晶粒300更可包括焊接點SJ與底部填充材料UF。此外，重佈線層314的最頂部介電層316具有用於容納附接於重佈線層314上的半導體晶粒300的開口。關於半導體封裝30的製造過程，於第一載體CA3-1上形成重佈線層314的步驟（如圖7B所示）在將半導體晶粒300的主動側AS3附接於第一載體CA3-1上的步驟（如圖7C所示）之前，且省略了附接與分離第二載體的步驟（例如是圖2E所示的第二載體CA1-2或圖5E所示的第二載體CA2-2）。因此，可進一步降低半導體封裝30的製造成本。
圖8是依照本發明一些實施例繪示的半導體封裝30a的剖視示意圖。圖8所示的半導體封裝30a相似於圖7G所示的半導體封裝30，惟圖8所示的半導體封裝30a更包括設置於電性連接件330與重佈線層314之間的焊球接墊329。
綜上所述，本發明實施例的半導體封裝包括被包封體側向包封的至少一半導體晶粒。重佈線層設置於半導體晶粒的主動側與包封體的前表面，而聚合物圖案層形成於包封體的背面。因此，包封體位於重佈線層與聚合物圖案層之間。包封體的熱膨脹係數（CTE）可以大於或小於聚合物圖案層與重佈線層中的介電層的熱膨脹係數。從而，由包封體與聚合物圖案層之間的熱膨脹係數失配所產生的應力以及由包封體和介電層之間的熱膨脹係數失配所產生的應力可至少部分地相互抵消。於是，可以減少半導體封裝中的總應力，使得半導體封裝不易有翹曲的問題。此外，聚合物圖案層形成在包封體的環繞半導體晶粒的一部分上，且可視為具有交疊於半導體晶粒的開口。如此一來，上覆於聚合物圖案的散熱結構可以直接接觸半導體晶粒。因此，半導體晶粒產生的熱量可以有效地經由散熱結構而逸散。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
S100、S102、S104、S106、S108、S110、S112、S114、S116、S200、S202、S204、S206、S208、S210、S212、S214、S216、S300、S302、S304、S306、S308、S310、S312、S314:步驟 10、10a、20、30、30a:半導體封裝 100、200、300:半導體晶粒 102、202、302:半導體基底 104、204、304:導電接墊 106、206、306:鈍化層 108、308:導電柱 110、120、210、220、310:附著層 112、212、312:包封體 112a、212a、312a:前表面 112b、212b、312b:背面 114、214、314:重佈線層 116、216、316:介電層 118、218、318:重佈線單元 122、222、322:聚合物圖案層 124、224、324:散熱結構 126、226、326:晶種層 128、228、328:導電層 129、229、329:焊球接墊 130、230、330:電性連接件 132、232、332:散熱件 132a:基部 132b:突出部 134、234、334:熱介面材料層 AS1、AS2、AS3:主動側 BS1、BS2、BS3:背側 CA1-1、CA2-1、CA3-1:第一載體 CA1-2、CA2-2:第二載體 SJ:焊接點 SP1、SP2、SP3:非零間距 T1:第一厚度 T2:第二厚度 UF:底部填充材料 W1、W2、W3:開口
接下來的圖式被包括以提供對本發明的進一步理解，並且併入與構成說明書的一部分。圖式繪示出本發明的示範實施例，且與說明書一起用於解釋本發明的原理。 圖1是依照本發明一些實施例繪示的半導體封裝的製造流程圖。 圖2A至圖2J是圖1所示的半導體封裝的製造過程期間的各階段的結構的剖視示意圖。 圖3是依照本發明一些實施例繪示的半導體封裝的剖視示意圖。 圖4是依照本發明一些實施例繪示的半導體封裝的製造流程圖。 圖5A至圖5I是圖4所示的半導體封裝的製造過程期間的各階段的結構的剖視示意圖。 圖6是依照本發明一些實施例繪示的半導體封裝的製造流程圖。 圖7A至圖7G是圖6所示的半導體封裝的製造過程期間的各階段的結構的剖視示意圖。 圖8是依照本發明一些實施例繪示的半導體封裝的剖視示意圖。
100:半導體晶粒
112:包封體
114:重佈線層
116:介電層
118:重佈線單元
122:聚合物圖案層
124:散熱結構
126:晶種層
128:導電層
129:焊球接墊
130:電性連接件

Claims (20)

  1. 一種半導體封裝，包括： 半導體晶粒，具有位於所述半導體晶粒的主動側的多個導電接墊； 包封體，側向包封所述半導體晶粒； 重佈線層，設置於所述半導體晶粒的所述主動側，且延伸於所述包封體的前表面，其中所述重佈線層電性連接至所述多個導電接墊； 聚合物圖案層，設置於所述包封體的背離所述前表面的背面，且環繞所述半導體晶粒；以及 散熱結構，接觸於所述半導體晶粒的背離所述主動側的背側，且延伸至所述聚合物圖案層上。
  2. 如申請專利範圍第1項所述的半導體封裝，其中非零間距所述聚合物圖案層與所述半導體晶粒之間具有非零間距。
  3. 如申請專利範圍第1項所述的半導體封裝，其中所述聚合物圖案層的側壁實質上共面於所述半導體晶粒的側壁。
  4. 如申請專利範圍第1項所述的半導體封裝，其中所述聚合物圖案層覆蓋所述半導體晶粒的周邊部分。
  5. 如申請專利範圍第1項所述的半導體封裝，其中所述散熱結構直接接觸於所述半導體晶粒的所述背側。
  6. 如申請專利範圍第1項所述的半導體封裝，其中所述散熱結構包括： 晶種層，共形地形成於所述聚合物圖案層與所述半導體晶粒的所述背側上；以及 導電層，形成於所述晶種層上。
  7. 如申請專利範圍第6項所述的半導體封裝，其中所述導電層的交疊於所述半導體晶粒的一部分具有第一厚度，所述導電層的覆蓋所述聚合物圖案層的另一部分具有第二厚度，且所述第一厚度大於所述第二厚度。
  8. 如申請專利範圍第1項所述的半導體封裝，更包括散熱件，設置於所述散熱結構上。
  9. 如申請專利範圍第1項所述的半導體封裝，其中所述半導體晶粒更具有多個導電柱，分別地設置於所述重佈線層與所述多個導電接墊的一者之間。
  10. 如申請專利範圍第9項所述的半導體封裝，其中所述半導體晶粒更具有多個焊接點，分別地設置於所述重佈線層與所述多個導電柱的一者之間。
  11. 如申請專利範圍第10項所述的半導體封裝，其中所述重佈線層的附接於所述半導體晶粒附接的表面具有凹陷，且所述半導體晶粒位於所述凹陷中。
  12. 如申請專利範圍第10項所述的半導體封裝，更包括底部填充材料，側向環繞所述多個導電柱與所述多個焊接點。
  13. 如申請專利範圍第1項所述的半導體封裝，更包括多個電性連接件，設置於所述重佈線層的背離所述半導體晶粒的表面，且電性連接至所述重佈線層。
  14. 一種半導體封裝的製造方法，包括： 提供半導體晶粒，其中所述半導體晶粒具有位於所述半導體晶粒的主動側的多個導電接墊； 以包封體側向包封所述半導體晶粒； 於所述半導體晶粒的所述主動側形成重佈線層，其中所述重佈線層覆蓋所述多個導電接墊且延伸於所述包封體的前表面； 於所述包封體的背離所述前表面的背面形成聚合物圖案層，其中所述聚合物圖案層具有開口，所述開口暴露出所述半導體晶粒的背離所述主動側的背側；以及 於所述半導體晶粒的所述背側形成散熱結構，其中所述散熱結構接觸於所述半導體晶粒，且延伸於所述聚合物圖案層上。
  15. 如申請專利範圍第14項所述的半導體封裝的製造方法，其中形成所述重佈線結構的步驟在形成所述聚合物圖案層的步驟與形成所述散熱結構的步驟之前。
  16. 如申請專利範圍第15項所述的半導體封裝的製造方法，更包括： 在以所述包封體側向包封所述半導體晶粒之前，將所述半導體晶粒的所述背側附接於第一載體； 在形成所述重佈線層之後且於形成所述散熱結構之前，將第二載體附接於所述重佈線層並將所述第一載體從所述半導體晶粒與所述包封體分離；以及 在形成所述散熱結構之後，將所述第二載體從所述重佈線層分離。
  17. 如申請專利範圍第14項所述的半導體封裝的製造方法，其中形成所述重佈線層的步驟在形成所述聚合物圖案層的步驟與形成所述散熱結構的步驟之後。
  18. 如申請專利範圍第17項所述的半導體封裝的製造方法，更包括： 在以所述包封體側向包封所述半導體晶粒之前，將所述半導體晶粒的所述主動側附接於所述第一載體； 在形成所述散熱結構之後且於形成所述重佈線層之前，將所述第二載體附接於所述散熱結構並將所述第一載體從所述半導體晶粒與所述包封體分離；以及 在形成所述重佈線層之後，將所述第二載體從所述散熱結構分離。
  19. 一種半導體封裝的製造方法，包括： 於載體上形成重佈線層； 將半導體晶粒附接於所述重佈線層上，其中所述半導體晶粒具有在所述半導體晶粒的主動側的多個導電柱，且所述多個導電柱附接且電性連接至所述重佈線層； 以包封體側向包封所述半導體晶粒； 於所述包封體的背離所述重佈線層的背面上形成聚合物圖案層，其中所述聚合物圖案層具有開口，所述暴露出所述半導體晶粒的背離所述主動側的背側； 於所述半導體晶粒的所述背側上形成散熱結構，其中所述散熱結構接觸於所述半導體晶粒，且延伸於所述聚合物圖案層上；以及 移除所述載體。
  20. 如申請專利範圍第19項所述的半導體封裝的製造方法，更包括： 在附接所述半導體晶粒之前，於所述重佈線層的表面形成凹陷，其中經附接的所述半導體晶粒位於所述凹陷內；以及 在附接所述半導體晶粒之後，形成側向環繞所述多個導電柱的底部填充材料。
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