TWI839068B - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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TWI839068B
TWI839068B TW112100995A TW112100995A TWI839068B TW I839068 B TWI839068 B TW I839068B TW 112100995 A TW112100995 A TW 112100995A TW 112100995 A TW112100995 A TW 112100995A TW I839068 B TWI839068 B TW I839068B
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Taiwan
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adhesive
substrate
package
interposer
package assembly
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TW112100995A
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English (en)
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廖一寰
謝秉穎
陳志豪
王卜
鄭禮輝
施應慶
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台灣積體電路製造股份有限公司
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Abstract

提供一種包含兩種不同黏合劑的半導體封裝及一種形成 方法。所述半導體封裝可包括：封裝組件，具有接合至基底的半導體晶粒；第一黏合劑，位於基底之上；熱量轉移層，位於封裝組件上；以及蓋，藉由第二黏合劑而貼合至基底。第一黏合劑可包圍封裝組件及熱量轉移層。蓋可包括頂部部分及底部部分，頂部部分位於熱量轉移層及第一黏合劑上，底部部分貼合至基底且包圍第一黏合劑。第二黏合劑的材料可不同於第一黏合劑的材料。

Description

半導體封裝及其製造方法
本發明的實施例是有關於半導體封裝及其製造方法。
積體電路的形成包括在半導體晶圓上形成積體電路裝置，且然後將半導體晶圓鋸切成裝置晶粒。可將裝置晶粒接合至封裝組件(例如中介層、封裝基底、印刷電路板或類似組件)。為了保護裝置晶粒及將裝置晶粒接合至封裝組件的接合結構，可使用包封體(例如模製化合物、底部填充膠或類似材料)來包封裝置晶粒。
本發明實施例的一種半導體封裝，包括封裝組件，包括半導體晶粒；基底，接合至所述封裝組件的第一側；第一黏合劑，位於所述基底之上，其中所述第一黏合劑在俯視圖中包圍所述封裝組件；熱量轉移層，位於所述封裝組件的第二側上，其中所述第一黏合劑在所述俯視圖中包圍所述熱量轉移層；以及蓋，包括：頂部部分，位於所述熱量轉移層及所述第一黏合劑上；以及底部部分，藉由第二黏合劑而貼合至所述基底，其中所述第二黏合劑的材 料不同於所述第一黏合劑的材料，且其中所述底部部分在所述俯視圖中包圍所述第一黏合劑。
本發明實施例的一種半導體封裝，包括中介層；封裝組件，接合至所述中介層的第一側，所述封裝組件包括半導體晶粒；包封體，位於所述中介層的所述第一側上，其中所述包封體在俯視圖中包圍所述封裝組件；基底，接合至所述中介層的第二側；底部填充膠，位於所述中介層與所述基底之間；第一黏合劑，位於所述基底之上，其中所述第一黏合劑在所述俯視圖中包圍所述中介層；金屬層，位於所述封裝組件之上，其中所述金屬層在所述底部填充膠上延伸；以及蓋結構，其中所述蓋結構的第一底部表面接合至所述金屬層且貼合至所述第一黏合劑，其中所述金屬層由所述蓋結構及所述第一黏合劑限定，其中所述蓋結構的第二底部表面藉由第二黏合劑而貼合至所述基底，且其中所述第一黏合劑具有與所述第二黏合劑不同的剛性。
本發明實施例的一種製造半導體封裝的方法包括：將封裝組件接合至基底，所述封裝組件包括：中介層，其中所述基底接合至所述中介層的第一側；半導體晶粒，接合至所述中介層的第二側；以及包封體，位於所述中介層的所述第二側上且包圍所述半導體晶粒，其中所述封裝組件上設置有與所述半導體晶粒接觸的第一金屬層；在所述封裝組件與所述基底之間形成底部填充膠；將金屬材料放置於所述第一金屬層上；在所述基底之上分配第一黏合劑及第二黏合劑，其中所述第一黏合劑的材料不同於所述第二黏 合劑的材料，且其中所述第一黏合劑在俯視圖中封閉所述封裝組件；以及將蓋結構放置於所述基底之上，其中所述第一黏合劑與所述蓋結構的第一底部表面接觸，且其中所述第二黏合劑與所述蓋結構的第二底部表面以及所述基底接觸。
20、66:載體
22、68:釋放膜
24、28、34、38:絕緣層
26、32、36:重佈線線(RDL)
30、40:開口
42、70、98:凸塊下金屬(UBM)
44、72、80:電性連接件
45外部連接件
46:中介層
50、50A、50B:封裝組件
56、102:底部填充膠
60:包封體
63、112:金屬層
63A:第一子層
63B:第二子層
63C:第三子層
63D:第四子層
64:晶圓結構
64’:封裝結構
74:膠帶
76:框架
78:切割道
79:表面安裝裝置(SMD)
82:基底
84:芯體材料
86:穿孔
88:填充材料
90:重佈線結構
94:介電層
96:金屬化圖案
100:阻焊劑
104:熱介面材料(TIM)
106:第一黏合劑
108:第二黏合劑
110:蓋
110A:頂部部分
110B:底部部分
110C:芯體
110D:塗層
114、116、118、119:區
120、122、124:半導體封裝
200:製程流程
202、204、206、208、210、212、214、216、218、220、222、224、226、228、230、232、234、236:製程
302:半導體基底
304:裝置
306:層間介電質(ILD)
308:導電插塞
310:內連線結構
312:接墊
314:鈍化膜
316:晶粒連接件
318:模製化合物
A-A’:參考橫截面
D1、D2、D3:距離
H1、H2:高度
T1、T2:厚度
W1、W2、W3:寬度
結合附圖閱讀以下詳細說明，會最佳地理解本揭露的各態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為使論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖9、圖10A、圖10B、圖11至圖17、圖18A、圖18B、圖18C、圖18D、圖19A、圖19B、圖20A及圖20B示出根據一些實施例在形成包含兩種不同黏合劑的半導體封裝中的中間階段的剖視圖及俯視圖。
圖21示出根據一些實施例的用於形成包含兩種不同黏合劑的半導體封裝的製程流程。
圖22A及圖22B示出根據一些實施例的各種半導體晶粒的剖視圖。
以下揭露內容提供用於實施本發明的不同特徵的諸多不同實施例或實例。以下闡述組件及佈置的具體實例以簡化本揭露。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其 中第一特徵與第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵進而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外，本揭露可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「位於...之下(underlying)」、「位於...下方(below)」、「下部的(lower)」、「上覆於...之上(overlying)」、「上部的(upper)」及類似用語等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
提供一種具有兩種不同黏合劑的半導體封裝及其形成方法。根據一些實施例，將封裝結構接合至基底，所述封裝結構包括多個半導體晶粒、中介層及包封體。在封裝結構上設置與多個半導體晶粒接觸的金屬層。將蓋貼合至基底並設置於金屬層之上。在金屬層與蓋之間設置熱量轉移層，並將熱量轉移層接合至金屬層及蓋。在蓋與基底之間設置包圍封裝結構的具有高剛性(stiffness)的第一黏合劑。第一黏合劑可為蓋提供支撐，此可減輕蓋的翹曲(warping)並改善熱量轉移層與蓋之間的接合以及熱量轉移層與 金屬層之間的接合。第一黏合劑亦與蓋形成對熱量轉移層進行限定的密封件(seal)。在對熱量轉移層進行迴焊(reflowing)期間，在密封件中產生高壓力，此可減少熱量轉移層中的空隙(void)的數量及大小。因此，自半導體晶粒經由金屬層及熱量轉移層而到達蓋的熱量轉移得到改善。具有低剛性的第二黏合劑被用於將蓋貼合至基底。第二黏合劑可減輕蓋的熱膨脹係數(coefficient of thermal expansion，CTE)與基底的熱膨脹係數之間的不匹配(mismatch)，此可防止或減少封裝結構出現裂紋(cracking)，藉此改善半導體封裝的長期可靠性。
圖1至圖6示出如圖6中所示的中介層46(例如，增層式中介層(build-up interposer))的形成的剖視圖。參照圖1，在載體20上形成釋放膜22。相應的製程被示出為如圖21中所示的製程流程200中的製程202。載體20可為玻璃載體、有機載體或類似載體。載體20可具有圓形的俯視形狀，且可具有矽晶圓的大小。釋放膜22可由可與載體20一起自將在後續步驟中形成的上覆結構移除的聚合物系材料(例如光熱轉換(light-to-heat-conversion，LTHC)材料)形成。在一些實施例中，釋放膜22包含環氧樹脂系熱釋放材料。可將釋放膜22塗佈至載體20上。
在釋放膜22上形成絕緣層24。相應的製程被示出為如圖21中所示的製程流程200中的製程204。在一些實施例中，絕緣層24包含有機材料(例如，聚苯並噁唑(polybenzoxazole，PBO)、聚醯亞胺、苯並環丁烯(benzocyclobutene，BCB)或類似材料) 或無機介電材料(例如，氧化矽、氮化矽、碳化矽、氮氧化矽、碳氧化矽、碳氮氧化矽、未經摻雜矽酸鹽玻璃(Un-doped Silicate Glass，USG)或類似材料)。
在絕緣層24之上形成多條重佈線線(redistribution line，RDL)26。相應的製程被示出為如圖21中所示的製程流程200中的製程206。RDL 26的形成可包括：在絕緣層24之上形成晶種層(未示出)；在晶種層之上形成經圖案化罩幕(未示出)，例如光阻或者一或多個介電材料層；以及在被暴露出的晶種層上鍍覆導電材料。移除經圖案化罩幕以及晶種層的被經圖案化罩幕覆蓋的部分。在其中光阻被用作經圖案化罩幕的實施例中，藉由例如使用氧電漿或類似材料的可接受的灰化製程(ashing process)或剝除製程(stripping process)來移除經圖案化罩幕。在其中所述一或多個介電材料層被用作經圖案化罩幕的實施例中，藉由可接受的剝除製程(例如濕法蝕刻(wet etching)或乾法蝕刻(dry etching))來移除經圖案化罩幕。剩餘的導電材料與下伏的晶種層可被統稱為RDL 26(如圖1中所示)。晶種層與所鍍覆的導電材料可由相同的材料或不同的材料形成。晶種層可為單一金屬層或可為包括由不同金屬材料形成的多個子層的複合層。在一些實施例中，晶種層可包括鈦層及位於鈦層之上的銅層。導電材料可為金屬或金屬合金，包括鋁、鎳、銅、鈦、鎢及/或其合金。可使用物理氣相沈積(physical vapor deposition，PVD)或類似製程來形成晶種層。可使用電化學鍍覆(electro chemical plating，ECP)、無電鍍覆(electro-less plating) 或類似製程來實行鍍覆製程。
圖2至圖5示出一或多個附加絕緣層以及RDL的形成。相應的製程被示出為如圖21中所示的製程流程200中的製程208。參照圖2，在多條RDL 26上形成絕緣層28並對絕緣層28進行圖案化。絕緣層28的底部表面與多條RDL 26的頂部表面及絕緣層24的頂部表面接觸。絕緣層28可包含可選自用於形成絕緣層24的相同候選材料群組的有機或無機材料。對絕緣層28進行圖案化以在絕緣層28中形成多個開口30，從而暴露出多條RDL 26的部分。
在圖3中，將多條RDL 32形成為連接至多條RDL 26。多條RDL 32可包括位於絕緣層28之上的多條金屬線。多條RDL 32亦可包括延伸至絕緣層28中的多個開口30中的多個金屬通孔，以連接至多條RDL 26的導線。可使用與以上參照RDL 26所論述者相同或相似的材料及製程來形成RDL 32。在圖4中，在多條RDL 32及絕緣層28上形成絕緣層34並對絕緣層34進行圖案化。可使用與以上參照絕緣層24所論述者相同或相似的材料及製程來形成絕緣層34並對絕緣層34進行圖案化。
圖5示出多條RDL 36的形成，多條RDL 36電性連接至多條RDL 32的相應導電特徵。可使用與以上參照RDL 26所論述者相同或相似的材料及製程來形成RDL 36。在多條RDL 36上形成絕緣層38並對絕緣層38進行圖案化以形成多個開口40，且多條RDL 36的一些部分經由絕緣層38中的多個開口40而暴露 出。可使用與以上參照絕緣層24所論述者相同或相似的材料及製程來形成絕緣層38並對絕緣層38進行圖案化。儘管在圖5中示出三層RDL(RDL 26、RDL 32及RDL 36)作為實例，然而所述結構可具有任意數目個RDL層。
圖6示出例如凸塊下金屬(Under-Bump Metallurgy，UBM)42等導電接墊的形成。相應的製程被示出為如圖21中所示的製程流程200中的製程210。絕緣層38中的多個開口40(示出於圖5中)的位置可對應於欲形成多個UBM 42的位置。可使用與以上參照RDL 26所論述者相同或相似的材料及製程來形成UBM 42。絕緣層24、絕緣層28、絕緣層34及絕緣層38以及RDL 26、RDL 32及RDL 36可被稱為中介層46。在一些實施例中，導電接墊可包括導電柱(conductive pillar)。
圖1至圖6示出其中中介層46是形成於載體基底上的增層式中介層的實例。亦可使用其他中介層。在一些實施例中，中介層46是半導體中介層，其可包括半導體基底(例如矽基底)、延伸穿過矽基底的多個矽穿孔(through-silicon via)及形成於半導體基底上的多條重佈線線。
在圖7中，將封裝組件50A及封裝組件50B(統稱為或各別地稱為封裝組件50)接合至中介層46。相應的製程被示出為如圖21中所示的製程流程200中的製程212。多個封裝組件50中的每一者可為一或多個裝置晶粒、其中封裝有一或多個裝置晶粒的封裝、包括被封裝為系統的多個裝置晶粒的系統晶片(System- on-Chip，SoC)晶粒或類似組件。封裝組件50中的裝置晶粒可為或者可包括邏輯晶粒、記憶體晶粒、輸入-輸出晶粒、積體被動裝置(Integrated Passive Device，IPD)、或類似晶粒、或其組合。舉例而言，封裝組件50中的邏輯裝置晶粒可為中央處理單元(Central Processing Unit，CPU)晶粒、圖形處理單元(Graphic Processing Unit，GPU)晶粒、行動應用晶粒、微控制單元(Micro Control Unit，MCU)晶粒、基頻(BaseBand，BB)晶粒、應用處理器(Application processor，AP)晶粒或類似晶粒。封裝組件50中的記憶體晶粒可包括靜態隨機存取記憶體(Static Random Access Memory，SRAM)晶粒、動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)晶粒或類似晶粒。封裝組件50可包括多個外部連接件45。在一些實施例中，封裝組件50A可表示在貼合至中介層46之前尚未被封裝的裝置晶粒，而封裝組件50B可指代在貼合至中介層46之前被接合於一起的多個堆疊的裝置晶粒。
圖22A示出封裝組件50A的詳細剖視圖。當封裝組件50A是半導體晶粒時。封裝組件50A可形成於可包括不同裝置區的晶圓中，所述裝置區在後續步驟中被單體化以形成多個積體電路晶粒。可根據適用的製造製程來處理封裝組件50A，以形成積體電路。舉例而言，封裝組件50A包括半導體基底302(例如經摻雜或未經摻雜的矽)或者絕緣體上半導體(semiconductor-on-insulator，SOI)基底的有效層(active layer)。半導體基底302可包含：其他半導體材料，例如鍺；化合物半導體，包括碳化矽、砷化鎵、磷化 鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或者其組合。亦可使用其他基底，例如多層式基底(multi-layered substrate)或梯度基底(gradient substrate)。半導體基底302具有有時被稱為前側(front side)的主動表面(active surface)(例如，圖22A中面朝上的表面)以及有時被稱為背側(back side)的非主動表面(inactive surface)(例如，圖22A中面朝下的表面)。
可在半導體基底302的前表面處形成多個裝置(以電晶體為代表)304。裝置304可為主動裝置(例如，電晶體、二極體等)、電容器、電阻器等。半導體基底302的前表面之上具有層間介電質(inter-layer dielectric，ILD)306。ILD 306環繞裝置304且可覆蓋裝置304。ILD 306可包括由例如磷矽酸鹽玻璃(Phospho-Silicate Glass，PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass，BSG)、摻雜硼的磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass，BPSG)、未經摻雜矽酸鹽玻璃(USG)或類似材料等材料形成的一或多個介電層。
多個導電插塞308延伸穿過ILD 306，以對多個裝置304進行電性耦合及實體耦合。舉例而言，當裝置304為電晶體時，導電插塞308可對電晶體的閘極與源極/汲極區進行耦合。源極/汲極區可視上下文而定各別地或籠統地指代源極或汲極。導電插塞308可由鎢、鈷、鎳、銅、銀、金、鋁、類似材料或其組合形成。ILD 306及多個導電插塞308之上具有內連線結構310。內連線結構 310對多個裝置304進行內連以形成積體電路。內連線結構310可由例如ILD 306上的多個介電層中的多個金屬化圖案形成。所述金屬化圖案包括形成於一或多個低介電常數(low-k)介電層中的多條金屬線及多個通孔。內連線結構310的多個金屬化圖案藉由多個導電插塞308而電性耦合至多個裝置304。
封裝組件50A更包括與外部進行連接的多個接墊312(例如鋁接墊)。接墊312位於封裝組件50A的主動側上，例如位於內連線結構310中及/或位於內連線結構310上。一或多個鈍化膜314位於封裝組件50A上，例如位於內連線結構310的部分及多個接墊312的部分上。多個開口穿過多個鈍化膜314延伸至多個接墊312。多個晶粒連接件316(例如導電柱(例如，由金屬(例如銅)形成))延伸穿過多個鈍化膜314中的多個開口，且實體耦合至及電性耦合至多個接墊312中的相應者。可藉由例如鍍覆或類似製程來形成晶粒連接件316。多個晶粒連接件316對封裝組件50A的相應積體電路進行電性耦合。
圖22B示出封裝組件50B的詳細剖視圖。封裝組件50B可為包括多個封裝組件50A的堆疊式裝置。多個封裝組件50A中的每一者可包括上面形成有多個主動裝置的半導體基底。舉例而言，封裝組件50B可為包括多個記憶體晶粒的記憶體裝置，例如混合記憶體立方體(hybrid memory cube，HMC)模組、高頻寬記憶體(high bandwidth memory，HBM)模組或類似裝置。在此種實施例中，封裝組件50B包括藉由多個基底穿孔(through-substrate via，TSV)而內連的多個半導體基底，所述基底穿孔延伸穿過多個半導體基底中的每一者。多個半導體基底中的每一者上可(或者可不)形成有內連線結構。此外，可藉由模製化合物318對封裝組件50B中的多個封裝組件50A中的上部封裝組件進行包封。
重新參照圖7，在一些實施例中，使用多個電性連接件44將多個封裝組件50接合至中介層46。在一些實施例中，電性連接件44可為焊料球(solder ball)。在一些實施例中，電性連接件44可為非焊料金屬柱(non-solder metal pillar)或者位於非焊料金屬柱之上的金屬柱及焊料頂蓋(solder cap)，其可藉由鍍覆製程來形成。亦可使用其他類型的接合，例如金屬對金屬接合(metal-to-metal bonding)、介電質對介電質接合(dielectric-to-dielectric bonding)與金屬對金屬接合的組合或者類似接合。出於例示目的，圖7示出中介層46及載體20的一部分，其中三個封裝組件50貼合至中介層46。中介層46可在載體20的較大的部分之上延伸，其他封裝組件可在載體20的其他部分之上接合至中介層46。
在圖8中，在多個封裝組件50與中介層46之間形成底部填充膠56，以減小應力並保護多個封裝組件50與中介層46之間的多個接頭(joint)，例如多個電性連接件44。相應的製程被示出為如圖21中所示的製程流程200中的製程214。底部填充膠56可包含例如環氧樹脂等基礎材料(base material)以及所述環氧樹脂中的填料顆粒(filler particle)。可在多個封裝組件50接合至中介層46之後藉由毛細流動製程(capillary flow process)來沈積底 部填充膠56，或者可在多個封裝組件50接合至中介層46之前藉由適合的沈積方法來形成底部填充膠56。舉例而言，可自多個封裝組件50的一側對底部填充膠56進行分配，且底部填充膠56藉由毛細作用而流動至多個封裝組件50與中介層46之間的間隙中。隨後，可對底部填充膠56進行固化。
在圖9中，將多個封裝組件50包封於包封體60中。相應的製程被示出為如圖21中所示的製程流程200中的製程216。包封體60覆蓋多個封裝組件50，且可填充接合至中介層46的鄰近的封裝組件50之間的間隙(若存在)。包封體60可包含模製化合物、模製底部填充膠、環氧樹脂、樹脂或類似材料。在一些實施例中，包封體60可包含基礎材料及所述基礎材料中的填料顆粒，所述基礎材料可為聚合物、樹脂、環氧樹脂或類似材料。填料顆粒可包括氧化矽、氧化鋁、二氧化矽或類似材料的介電顆粒，且可具有球形形狀。此外，球形填料顆粒可具有相同或不同的直徑。可藉由壓縮模製(compression molding)、轉移模製(transfer molding)或類似製程來施加包封體60。可以液體或半液體形式施加包封體60，且隨後對包封體60進行固化。
可對包封體60實行平坦化製程(planarization process)，以暴露出多個封裝組件50的頂部表面。在平坦化製程之後，多個封裝組件50的頂部表面與包封體60的頂部表面在製程變化內實質上共面，且包封體60可在俯視圖中包圍多個封裝組件50。平坦化製程可為化學機械研磨(chemical-mechanical polish，CMP)、磨 製製程(grinding process)或類似製程。在一些實施例中，可省略平坦化。在一些實施例中，包封體60可保留於多個封裝組件50之上。多個封裝組件50、中介層46、底部填充膠56及/或包封體60可被統稱為晶圓結構64。
在圖10A中，在包封體60的頂部表面及多個封裝組件50的頂部表面上形成金屬層63。相應的製程被示出為如圖21中所示的製程流程200中的製程218。如以下所更詳細論述，金屬層63可在後續步驟中與熱介面材料(thermal interface material，TIM)進行接合，且將在操作期間由多個封裝組件50產生的熱量自封裝結構64’轉移出去。因此，金屬層63可促進完成的半導體封裝中的散熱。在一些實施例中，金屬層63可包括由不同金屬(例如鋁、鈦、鎳、釩、金或類似金屬)形成的一或多個子層(示出於圖10B中)。金屬層63可具有處於約0.6微米至約0.9微米的範圍內(例如0.75微米)的厚度。可使用例如PVD、化學氣相沈積(chemical vapor deposition，CVD)、原子層沈積(atomic layer deposition，ALD)或類似製程等對應的沈積製程來形成每一子層。
圖10B示出根據一些實施例的包括四個子層的金屬層63的詳細圖。可在包封體60的頂部表面及多個封裝組件50的頂部表面上形成包含鋁的第一子層63A，其中第一子層63A的厚度可為約0.2微米。可在第一子層63A上形成為鈦的第二子層63B，其中第二子層63B的厚度可為約0.1微米。可在第二子層63B上形成為鎳釩合金的第三子層63C，其中第三子層63C的厚度可為 約0.35微米。可在第三子層63C上形成為金的第四子層63D，其中第四子層63D的厚度可為約0.1微米。亦可使用其他配置。
圖11示出載體調換(carrier swap)及在中介層46的底側上形成底側電性連接件(bottom-side electrical connector)。相應的製程被示出為如圖21中所示的製程流程200中的製程220。使用例如LTHC材料等釋放膜68將載體66貼合至金屬層63的上部表面。自晶圓結構64折離載體20(示出於圖10中)。在其中釋放膜22包含LTHC材料的實施例中，折離製程可包括經由載體20(其可為透明的)將光束(例如雷射束)投射於釋放膜22上。作為曝光的結果，釋放膜22被分解，且載體20可被自釋放膜22提離(lifted off)。對應的製程亦被稱為剝離(de-bonding)。
作為剝離製程的結果，絕緣層24被顯露出。在中介層46上形成多個UBM 70及多個電性連接件72，以提供與多個封裝組件50之間的電性連接。相應的製程被示出為如圖21中所示的製程流程200中的製程222。形成製程可包括對絕緣層24進行圖案化以形成暴露出在多個RDL 26中形成的多個導電接墊的多個開口。多個UBM 70延伸至絕緣層24中的多個開口中，且形成於被暴露出的多個導電接墊上。可使用與以上參照RDL 26所論述者相同或相似的材料及製程來形成UBM 70。在多個UBM 70上形成多個電性連接件72。在一些實施例中，電性連接件72的形成可包括：在UBM 70的被暴露出的部分上放置焊料球，並對所述焊料球進行迴焊。在一些實施例中，電性連接件72可為非焊料金屬柱 或者位於非焊料金屬柱之上的金屬柱及焊料頂蓋。
在圖12中，例如藉由在釋放膜68上投射雷射束而自載體66(示出於圖11中)折卸晶圓結構64，以使得釋放膜68分解。將晶圓結構64放置於由框架76支撐的膠帶(tape)74上。沿多個切割道(scribe line)78對晶圓結構64進行單體化，以使得晶圓結構64被分離成分立的多個封裝結構64’。相應的製程被示出為如圖21中所示的製程流程200中的製程224。圖12示出封裝結構64’中的三個封裝組件50作為實例，封裝結構64’中可存在任何數目個封裝組件50。
在圖13中，將封裝結構64’與基底82接合。所述接合是藉由多個電性連接件72而進行，其中電性連接件72可包括焊料球。相應的製程被示出為如圖21中所示的製程流程200中的製程226。基底82可為或可包括中介層、封裝、芯體基底(core substrate)、無芯體基底(coreless substrate)、印刷電路板或類似基底。圖13將基底82示出為包括芯體材料84、多個穿孔(through via)86、填充材料88、多條重佈線結構90的芯體基底。每一重佈線結構90可包括介電層94、多個金屬化圖案96、多個UBM 98及多個阻焊劑(solder resist)100。每一重佈線結構90可具有較圖13中所示者多的介電層94及金屬化圖案96。在一些實施例中，基底82可具有藉由多個電性連接件80而接合至基底82的多個表面安裝裝置(surface mount device，SMD)79。SMD 79可為積體被動裝置(IPD)，例如2端子IPD(2-terminal IPD)、多端子IPD (multi-terminal IPD)或其他類型的被動裝置。SMD 79可包括電容器、電阻器、電感器、類似裝置或其組合。圖13示出在封裝結構64’接合至基底82之前將SMD 79接合至基底82來作為實例，亦可在封裝結構64’接合至基底82之後將SMD 79接合至基底82。圖13示出將兩個SMD 79接合至基底82來作為實例，亦可將其他數目個SMD 79接合至基底82。
在圖14中，在封裝結構64’與基底82之間形成底部填充膠102，以減小應力並保護封裝結構64’與基底82之間的多個接頭，例如多個電性連接件72。相應的製程被示出為如圖21中所示的製程流程200中的製程228。在一些實施例中，底部填充膠102可在包封體60的多個側壁上延伸。底部填充膠102可包含例如環氧樹脂等基礎材料以及環氧樹脂中的填料顆粒。可藉由毛細流動製程(capillary flow process)來沈積底部填充膠102。舉例而言，可自封裝結構64’的一側對底部填充膠102進行分配，且底部填充膠102藉由毛細作用而流動至封裝結構64’與基底82之間的間隙中。隨後，可對底部填充膠102進行固化。圖14示出底部填充膠102具有彎曲的側壁來作為實例，底部填充膠102的側壁亦可具有其他形狀。
在圖15中，將熱介面材料(TIM)104放置於金屬層63上。相應的製程被示出為如圖21中所示的製程流程200中的製程230。TIM 104可為熱量轉移層，且可將熱量自金屬層63轉移出去。因此，TIM 104可促進完成的半導體封裝中的散熱。TIM 104 可包含金屬材料，例如熔化溫度處於約160℃至約260℃的範圍內的金屬或金屬合金(例如銦、銦銀合金、錫銅合金、銦銀銅合金(例如，SAC305)或類似材料)。TIM 104可具有處於約100微米至約300微米的範圍內(例如200微米)的厚度T1。可在TIM 104被放置於金屬層63上之前將例如免清潔焊劑(no-clean flux)等焊劑分配於金屬層63上，且在TIM 104被放置於金屬層63上之後將所述焊劑分配於TIM 104上。焊劑可幫助TIM 104與位於下方的金屬層63及位於上方的隨後貼合的蓋進行接合，如以下所更詳細論述。
在圖16中，將第一黏合劑106及第二黏合劑108分配於基底82上。相應的製程被示出為如圖21中所示的製程流程200中的製程232。如以下所更詳細論述，第一黏合劑106可為隨後貼合的蓋提供支撐，並與蓋一起形成對TIM 104進行限定的密封件，且第二黏合劑108可將蓋貼合至基底82。可在分配第二黏合劑108之前或分配第二黏合劑108之後對第一黏合劑106進行分配。第一黏合劑106與第二黏合劑108可具有不同的化學組成物。第一黏合劑106可包含矽酮以及填料材料(filler material)(例如，氧化鋁)，所述矽酮可構成第一黏合劑106的約10%至約30%，所述填料材料可構成第一黏合劑106的約70%至約90%。在一些實施例中，第二黏合劑108可包含矽酮以及填料材料(例如，二氧化矽)，所述矽酮可構成第二黏合劑108的約70%至約90%，所述填料材料可構成第二黏合劑108的約10%至約30%。在一些實施例 中，第一黏合劑106可較第二黏合劑108包含更少的矽酮。如圖16中所示，將第一黏合劑106設置於基底82與底部填充膠102二者上。如以下針對圖18D所更詳細論述，第一黏合劑106可為在俯視圖中包圍封裝結構64’的單一特徵，且第二黏合劑108可包括在俯視圖中局部地環繞第一黏合劑106的多個分立的部分。
在圖17中，將蓋110貼合至基底82。相應的製程被示出為如圖21中所示的製程流程200中的製程234。蓋110可耗散由TIM 104轉移至蓋110的熱量。蓋110可包含導熱材料，例如銅、鎳或類似材料。在一些實施例中，蓋110可包括芯體110C(示出於圖18B中)以及塗層(coating layer)110D(示出於圖18B中)，芯體110C可包含銅或類似材料，塗層110D可包含鎳或類似材料。塗層110D可具有處於5微米至10微米的範圍內的厚度。蓋110可包括頂部部分110A及底部部分110B。頂部部分110A在俯視圖中可覆蓋基底82的大部分面積，且底部部分在俯視圖中可包圍封裝結構64’及第二黏合劑108。頂部部分110A的底部表面上可設置有金屬層112。金屬層112在俯視圖中可具有與TIM 104的大小相似的大小(例如，表面積)，且可具有處於約0.05微米至約0.2微米的範圍內(例如0.1微米)的厚度T2。金屬層112可包含金或類似材料，且可藉由電沈積(electrodeposition，ECP)、PVD、CVD、ALD或類似製程來將金屬層112沈積於頂部部分110A上。在一些實施例中，在沈積金屬層112之後，可實行圖案化製程(例如，微影(photolithography)及蝕刻)以自蓋110移除金屬層112 的過量部分。作為另外一種選擇，可在沈積金屬層112之前在蓋110上沈積經圖案化罩幕(未示出)，且可在經圖案化罩幕的多個開口中選擇性地沈積金屬層112。在一些實施例中，可以毯覆方式沈積(blanket deposit)金屬層112，且可省略圖案化製程。因此，金屬層112可覆蓋蓋110的面對TIM 104的整個表面，且金屬層112可具有較TIM 104大的表面積。可將金屬層112放置成與TIM 104的頂部表面接觸，可將頂部部分110A的底部表面的被暴露出的多個部分放置成與第一黏合劑106的頂部表面接觸，且可將底部部分110B的底部表面放置成與第二黏合劑108的多個頂部表面接觸。
在圖18A中，對第一黏合劑106及第二黏合劑108進行固化，且對TIM104進行迴焊以將蓋110黏合至基底82及TIM 104。金屬層112以及金屬層63的第四子層63D可藉由迴焊製程期間的反應而被完全消耗，如以下所更詳細論述。相應的製程被示出為如圖21中所示的製程流程200中的製程236。可在溫度處於約120℃至約140℃的範圍內(例如130℃)的環境氣氛(ambient atmosphere)中對第一黏合劑106及第二黏合劑108進行固化。在對第一黏合劑106及第二黏合劑108進行固化期間，可向第一黏合劑106及第二黏合劑108的多個頂部表面及多個底部表面施加壓縮壓力(compressive pressure)。在固化之後，第一黏合劑106可改變形狀並包括凹的內側壁及凸的外側壁，且第一黏合劑106、蓋110、封裝結構64’及底部填充膠102可形成對TIM 104進行限 定的密封件。如以下所更詳細論述，對TIM 104進行限定的密封件可在隨後的迴焊製程期間減少TIM 104中的空隙的數量及大小。
在固化之後，第一黏合劑106可具有處於約10百萬帕至約100百萬帕的範圍內(例如50百萬帕)的第一楊氏模數E1。在第一黏合劑106的第一楊氏模數E1處於此種範圍內的情況下，第一黏合劑106可為蓋110提供支撐，此可減輕蓋110的翹曲。因此，TIM 104與蓋110之間的接合以及TIM 104與金屬層63之間的接合(以下更詳細地論述所述接合)可得到改善。在固化之後，第二黏合劑108可具有處於約1百萬帕至約10百萬帕的範圍內(例如5百萬帕)的第二楊氏模數E2。在第二黏合劑108的第二楊氏模數E2處於此種範圍內的情況下，第二黏合劑108可減輕蓋110的熱膨脹係數(CTE)與基底82的CTE之間的不匹配。因此，可防止或減少封裝結構64’出現裂紋，藉此改善半導體封裝的長期可靠性。在一些實施例中，第一黏合劑106的第一楊氏模數E1大於第二黏合劑108的第二楊氏模數E2，且因此第一黏合劑106可具有較第二黏合劑108高的剛性。第一黏合劑106可具有處於約0.8毫米至1.1毫米的範圍內(例如1毫米)的高度H1，且第二黏合劑108可具有處於約0.05毫米至0.3毫米的範圍內(例如0.2毫米)的高度H2。
可在處於約160℃至約260℃的範圍內(例如180℃或250℃)的溫度下對TIM 104進行迴焊。可在環境氣氛中或在氮氣氛中對TIM 104進行迴焊。在迴焊製程期間，TIM 104可熔化並 藉由金屬對金屬接合而與位於上方的蓋110及位於下方的金屬層63進行接合，此會提供自多個封裝組件50至蓋110的熱量轉移途徑。圖18B示出半導體封裝120的一部分，所述部分在具有TIM 104與蓋110之間的介面以及TIM 104與金屬層63之間的介面的更多細節的圖18A中被稱為區116。在迴焊製程期間，TIM 104、金屬層112(示出於圖17中)及蓋110的塗層110D中的金屬材料可彼此反應，並在位於TIM 104與蓋110之間的介面處的區118中形成金屬間化合物(inter-metallic compound)。此種反應可將金屬層112完全消耗。此外，在迴焊製程期間，TIM 104、金屬層63的第四子層63D及金屬層63的第三子層63C中的金屬材料可彼此反應，並在位於TIM 104與金屬層63之間的介面處的區119中形成金屬間化合物。此種反應可將金屬層63的第四子層63D完全消耗。因此，在迴焊製程之後，TIM 104可與蓋110的塗層110D及金屬層63的第三子層63C接觸。圖18B的配置對應於圖10B中所示金屬層63的詳細配置，金屬層63的其他配置亦是可能的。
重新參照圖18A，由第一黏合劑106向蓋110提供的支撐可減輕蓋110的翹曲，此會改善TIM 104與金屬層63之間的接合以及TIM 104與蓋110之間的接合，藉此分別改善自金屬層63至TIM 104及自TIM 104至蓋110的熱量轉移效率。由於TIM 104被限定於由第一黏合劑106、蓋110、封裝結構64’及底部填充膠102形成的密封件中，迴焊製程期間的加熱可在密封件中產生高壓力，此可減少在迴焊製程期間TIM 104中的空隙的數量及大小， 藉此改善TIM 104的熱量轉移能力。因此，半導體封裝的長期可靠性可得到改善。
在迴焊製程之後，TIM 104可改變厚度及形狀，且可如圖18A中所示在底部填充膠102以及第一黏合劑106的內側壁上延伸。在一些實施例中，底部填充膠102可被第一黏合劑106及TIM 104完全覆蓋。TIM 104與第一黏合劑106的內側壁之間可設置有一或多個空氣間隙(air gap)。圖18A示出封裝結構64’的多個側壁被底部填充膠102完全覆蓋來作為實例。在其中封裝結構64’的多個側壁未被底部填充膠102完全覆蓋的實施例中，TIM 104可在封裝結構64’上延伸，例如在中介層46及/或包封體60上延伸。圖18A中所示結構可被稱為半導體封裝120。
圖18C示出半導體封裝120的一部分，所述部分在圖18A中被稱為區114。第一黏合劑106可具有寬度W1，寬度W1是第一黏合劑106的內側壁與外側壁之間的最小水平距離。寬度W1可處於約1毫米至約3毫米的範圍內。當寬度W1大於1毫米時，可防止第一黏合劑106被在如以上所論述的迴焊製程期間產生的高壓力破壞。第一黏合劑106可與封裝結構64’間隔開距離D1，距離D1是第一黏合劑106的內側壁與封裝結構64’的外側壁之間的最小水平距離。距離D1可處於約1毫米至約3毫米的範圍內。當距離D1大於1毫米時，可防止第一黏合劑106被在如以上所論述的迴焊製程期間熔化的TIM 104破壞。
圖18D示出圖18A中所示半導體封裝120的俯視圖， 其中相同的參考編號指代相同的特徵。圖18A中所示半導體封裝120的剖視圖可自圖18D中所示半導體封裝120的俯視圖中的參考橫截面A-A’獲得，其中出於例示性目的，省略蓋110、TIM 104及金屬層63。如圖18D中所示，第一黏合劑106可為單一特徵，所述單一特徵可呈框架(frame)的形狀且包圍封裝結構64’。第一黏合劑106可包括四個段(segment)，其中每一段與兩個鄰近段相交，且每一段延伸超過每一鄰近段的外邊緣。因此，可使第一黏合劑106的多個隅角增強，且可防止第一黏合劑106被在如以上所論述的迴焊製程期間產生的高壓力破壞。第二黏合劑108可具有藉由兩個開口而分離的兩個分立的部分。舉例而言，第二黏合劑108的每一部分可具有括弧(bracket)的形狀。因此，可防止或減少第一黏合劑106的外側壁與蓋110的底部部分110B的內側壁之間的空間中的壓力積聚(pressure build-up)。第二黏合劑108的所述兩個部分可局部地環繞第一黏合劑106。
圖19A示出根據一些實施例的與圖18A中所示半導體封裝120相似的半導體封裝122，其中相同的參考編號指代相同的特徵。在圖19A中，可將第一黏合劑106完全設置於底部填充膠102上，進而使得第一黏合劑106的部分均不接觸基底82的上部表面。半導體封裝122中的第一黏合劑106及第二黏合劑108的材料、形狀、大小可分別與如以上所論述的半導體封裝120中的第一黏合劑106及第二黏合劑108的材料、形狀、大小相同或相似。TIM 104可在底部填充膠102以及第一黏合劑106的內側壁 上延伸，且TIM 104與第一黏合劑106的內側壁之間可設置有一或多個空氣間隙。在一些實施例中，底部填充膠102可被TIM 104及第一黏合劑106局部地覆蓋，其中底部填充膠102的多個部分被暴露出。圖19A示出封裝結構64’的多個側壁被底部填充膠102完全覆蓋來作為實例。在其中封裝結構64’的多個側壁未被底部填充膠102完全覆蓋的實施例中，TIM 104可在封裝結構64’的多個側壁上延伸，例如在中介層46的多個側壁及/或包封體60的多個側壁上延伸。
圖19B示出半導體封裝122的一部分，所述部分在圖19A中被稱為區114。第一黏合劑106可具有寬度W2，寬度W2是第一黏合劑106的內側壁與外側壁之間的最小水平距離。寬度W2可處於約1毫米至約3毫米的範圍內。第一黏合劑106可與封裝結構64’間隔開距離D2，距離D2是第一黏合劑106的內側壁與封裝結構64’的外側壁之間的最小水平距離。距離D2可處於約1毫米至約3毫米的範圍內。寬度W2及距離D2處於此種範圍內的益處分別相似於如以上針對圖18C所論述的寬度W1及距離D1處於對應範圍內的益處。
圖20A示出根據一些實施例的與圖18A中所示半導體封裝120相似的半導體封裝124，其中相同的參考編號指代相同的特徵。在圖20A中，可將第一黏合劑106完全設置於基底82的上部表面上，進而使得第一黏合劑106的部分均不接觸底部填充膠102。半導體封裝124中的第一黏合劑106及第二黏合劑108的材 料、形狀、大小可分別與如以上所論述的半導體封裝120中的第一黏合劑106及第二黏合劑108的材料、形狀、大小相同或相似。TIM 104可在底部填充膠102以及第一黏合劑106的內側壁上延伸，且TIM 104與第一黏合劑106的內側壁之間可設置有一或多個空氣間隙。在一些實施例中，底部填充膠102可被TIM 104完全覆蓋。圖20A示出封裝結構64’的多個側壁被底部填充膠102完全覆蓋來作為實例。在其中封裝結構64’的多個側壁未被底部填充膠102完全覆蓋的實施例中，TIM 104可在封裝結構64’的多個側壁上延伸，例如在中介層46的多個側壁及/或包封體60的多個側壁上延伸。
圖20B示出半導體封裝124的一部分，所述部分在圖20A中被稱為區114。第一黏合劑106可具有寬度W3，寬度W3是第一黏合劑106的內側壁與外側壁之間的最小水平距離。寬度W3可處於約1毫米至約3毫米的範圍內。第一黏合劑106可與封裝結構64’間隔開距離D3，距離D3是第一黏合劑106的內側壁與封裝結構64’的外側壁之間的最小水平距離。距離D3可處於約1毫米至約3毫米的範圍內。寬度W3及距離D3處於此種範圍內的益處分別相似於如以上針對圖18C所論述的寬度W1及距離D1處於對應範圍內的益處。
本揭露的實施例具有一些有利特徵。藉由在蓋110與基底82之間利用具有高剛性的第一黏合劑106及具有低剛性的第二黏合劑108，自封裝組件50經由金屬層63及TIM 104而到達蓋 110的熱量轉移得到改善，且可防止或減少封裝結構64’出現裂紋。因此，半導體封裝120、半導體封裝122及半導體封裝124的長期可靠性可得到改善。
在實施例中，一種半導體封裝包括：封裝組件，包括半導體晶粒；基底，接合至封裝組件的第一側；第一黏合劑，位於基底之上，其中第一黏合劑在俯視圖中包圍封裝組件；熱量轉移層，位於封裝組件的第二側上，其中第一黏合劑在俯視圖中包圍熱量轉移層；以及蓋，所述蓋包括頂部部分以及底部部分，頂部部分位於熱量轉移層及第一黏合劑上，底部部分藉由第二黏合劑而貼合至基底，其中第二黏合劑的材料不同於第一黏合劑的材料，且其中底部部分在俯視圖中包圍第一黏合劑。在實施例中，第一黏合劑的楊氏模數大於第二黏合劑的楊氏模數。在實施例中，第一黏合劑的楊氏模數處於10百萬帕至100百萬帕的範圍內。在實施例中，第二黏合劑的楊氏模數處於1百萬帕至10百萬帕的範圍內。在實施例中，第一黏合劑在俯視圖中包括四個段，其中所述四個段中的每一段與所述四個段中的兩個鄰近段相交，且其中所述四個段中的每一段延伸超過所述四個段中的每一鄰近段的外邊緣。在實施例中，第二黏合劑在俯視圖中環繞第一黏合劑，且其中第二黏合劑包括藉由兩個開口而彼此實體地分離的兩個部分。在實施例中，第一黏合劑與封裝組件間隔開大於1毫米的距離。
在實施例中，一種半導體封裝包括：中介層；封裝組件，接合至中介層的第一側，封裝組件包括半導體晶粒；包封體，位於 中介層的第一側上，其中包封體在俯視圖中包圍封裝組件；基底，接合至中介層的第二側；底部填充膠，位於中介層與基底之間；第一黏合劑，位於基底之上，其中第一黏合劑在俯視圖中包圍中介層；金屬層，位於封裝組件之上，其中金屬層在底部填充膠上延伸；以及蓋結構，其中蓋結構的第一底部表面接合至金屬層且貼合至第一黏合劑，其中金屬層由蓋結構及第一黏合劑限定，其中蓋結構的第二底部表面藉由第二黏合劑而貼合至基底，且其中第一黏合劑具有與第二黏合劑不同的剛性。在實施例中，第一黏合劑局部地設置於底部填充膠上且局部地設置於基底上。在實施例中，第一黏合劑實體地接觸底部填充膠。在實施例中，第一黏合劑實體地接觸基底的上部表面。在實施例中，第一黏合劑具有大於1毫米的厚度。在實施例中，第一黏合劑的內側壁是凹的。
在實施例中，一種製造半導體封裝的方法包括：將封裝組件接合至基底，封裝組件包括中介層、半導體晶粒以及包封體，其中基底接合至中介層的第一側，半導體晶粒接合至中介層的第二側，包封體位於中介層的第二側上且包圍半導體晶粒，其中封裝組件上設置有與半導體晶粒接觸的第一金屬層；在封裝組件與基底之間形成底部填充膠；將金屬材料放置於第一金屬層上；在基底之上分配第一黏合劑及第二黏合劑，其中第一黏合劑的材料不同於第二黏合劑的材料，且其中第一黏合劑在俯視圖中封閉封裝組件；以及將蓋結構放置於基底之上，其中第一黏合劑與蓋結構的第一底部表面接觸，且其中第二黏合劑與蓋結構的第二底部表面以 及基底接觸。在實施例中，第一黏合劑的材料較第二黏合劑的材料包含更少的矽酮。在實施例中，所述方法更包括對第一黏合劑及第二黏合劑進行固化，其中對第一黏合劑及第二黏合劑進行固化包括在第一黏合劑及第二黏合劑的頂部表面及底部表面上施加壓縮壓力。在實施例中，所述方法更包括對金屬材料進行迴焊以形成第二金屬層，其中第二金屬層接合至第一金屬層及蓋結構。在實施例中，形成第二金屬層包括形成與第一黏合劑及底部填充膠接觸的第二金屬層。在實施例中，分配第一黏合劑包括與底部填充膠接觸地分配第一黏合劑。在實施例中，分配第一黏合劑包括與基底接觸地分配第一黏合劑。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本揭露的各態樣。熟習此項技術者應理解，他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，此種等效構造並不背離本揭露的精神及範圍，而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替及變更。
50A、50B:封裝組件
63:金屬層
64’:封裝結構
82:基底
84:芯體材料
86:穿孔
88:填充材料
90:重佈線結構
94:介電層
96:金屬化圖案
98:凸塊下金屬(UBM)
100:阻焊劑
102:底部填充膠
104:熱介面材料(TIM)
106:第一黏合劑
108:第二黏合劑
110:蓋
110A:頂部部分
110B:底部部分
114、116:區
120:半導體封裝
H1、H2:高度

Claims (10)

  1. 一種半導體封裝，包括：封裝組件，包括半導體晶粒；基底，接合至所述封裝組件的第一側；第一黏合劑，位於所述基底之上，其中所述第一黏合劑在俯視圖中包圍所述封裝組件；熱量轉移層，位於所述封裝組件的第二側上，其中所述第一黏合劑在所述俯視圖中包圍所述熱量轉移層；以及蓋，包括：頂部部分，位於所述熱量轉移層及所述第一黏合劑上，其中所述頂部部分與所述第一黏合劑的頂部表面接觸；以及底部部分，藉由第二黏合劑而貼合至所述基底，其中所述第二黏合劑的材料不同於所述第一黏合劑的材料，且其中所述底部部分在所述俯視圖中包圍所述第一黏合劑。
  2. 如請求項1所述的半導體封裝，所述第一黏合劑的楊氏模數大於所述第二黏合劑的楊氏模數。
  3. 如請求項1所述的半導體封裝，其中所述第一黏合劑在所述俯視圖中包括四個段，其中所述四個段中的每一段與所述四個段中的兩個鄰近段相交，且其中所述四個段中的每一段延伸超過所述四個段中的每一鄰近段的外邊緣；以及其中所述第二黏合劑在所述俯視圖中環繞所述第一黏合劑，且其中所述第二黏合劑包括藉由兩個開口而彼此實體地分離的兩個部 分。
  4. 一種半導體封裝，包括：中介層；封裝組件，接合至所述中介層的第一側，所述封裝組件包括半導體晶粒；包封體，位於所述中介層的所述第一側上，其中所述包封體在俯視圖中包圍所述封裝組件；基底，接合至所述中介層的第二側；底部填充膠，位於所述中介層與所述基底之間；第一黏合劑，位於所述基底之上，其中所述第一黏合劑在所述俯視圖中包圍所述中介層；金屬層，位於所述封裝組件之上，其中所述金屬層在所述底部填充膠上延伸；以及蓋結構，其中所述蓋結構的第一底部表面接合至所述金屬層且貼合至所述第一黏合劑，其中所述金屬層由所述蓋結構及所述第一黏合劑限定，其中所述蓋結構的第二底部表面藉由第二黏合劑而貼合至所述基底，且其中所述第一黏合劑具有與所述第二黏合劑不同的剛性。
  5. 如請求項4所述的半導體封裝，其中所述第一黏合劑局部地設置於所述底部填充膠上且局部地設置於所述基底上。
  6. 如請求項4所述的半導體封裝，其中所述第一黏合劑實體地接觸所述底部填充膠。
  7. 如請求項4所述的半導體封裝，其中所述第一黏合劑實體地接觸所述基底的上部表面。
  8. 一種製造半導體封裝的方法，所述方法包括：將封裝組件接合至基底，所述封裝組件包括：中介層，其中所述基底接合至所述中介層的第一側；半導體晶粒，接合至所述中介層的第二側；以及包封體，位於所述中介層的所述第二側上且包圍所述半導體晶粒，其中所述封裝組件上設置有與所述半導體晶粒接觸的第一金屬層；在所述封裝組件與所述基底之間形成底部填充膠；將金屬材料放置於所述第一金屬層上；在所述基底之上分配第一黏合劑及第二黏合劑，其中所述第一黏合劑的材料不同於所述第二黏合劑的材料，且其中所述第一黏合劑在俯視圖中封閉所述封裝組件；以及將蓋結構放置於所述基底之上，其中所述第一黏合劑與所述蓋結構的第一底部表面接觸，且其中所述第二黏合劑與所述蓋結構的第二底部表面以及所述基底接觸。
  9. 如請求項8所述的製造半導體封裝的方法，其中所述第一黏合劑的所述材料較所述第二黏合劑的所述材料包含更少的矽酮。
  10. 如請求項8所述的製造半導體封裝的方法，更包括對所述第一黏合劑及所述第二黏合劑進行固化，其中對所述第一 黏合劑及所述第二黏合劑進行固化包括在所述第一黏合劑及所述第二黏合劑的多個頂部表面及多個底部表面上施加壓縮壓力。
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