TW202109801A - 半導體封裝體及其形成方法 - Google Patents

半導體封裝體及其形成方法 Download PDF

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TW202109801A
TW202109801A TW109127663A TW109127663A TW202109801A TW 202109801 A TW202109801 A TW 202109801A TW 109127663 A TW109127663 A TW 109127663A TW 109127663 A TW109127663 A TW 109127663A TW 202109801 A TW202109801 A TW 202109801A
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chip
rewiring
rewiring structure
semiconductor package
redistribution
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TW109127663A
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TWI731773B (zh
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莊博堯
蔡柏豪
林孟良
吳逸文
鄭心圃
翁得期
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台灣積體電路製造股份有限公司
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Priority claimed from US16/811,465 external-priority patent/US11322447B2/en
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Publication of TW202109801A publication Critical patent/TW202109801A/zh
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Abstract

一半導體封裝體藉由將一第一元件貼附至一第二元件製造。第一元件藉由在一基板之上形成一第一重佈線結構裝配。一貫通孔接著形成在第一重佈線結構之上，且一晶片貼附至第一重佈線結構，主動側朝下。第二元件包括一第二重佈線結構，其接著貼附至貫通孔。一成型模料沉積在第一重佈線結構和第二重佈線結構之間，且更包圍第二元件的側邊。

Description

半導體封裝體及其形成方法
本發明實施例係有關於一種半導體封裝體。更具體地來說，本發明實施例有關於一種具有封裝膠的半導體封裝體。
由於各種電子元件(例如電晶體、二極體、電阻、電容等)的積體密度不斷改進，半導體產業經歷快速成長。在大多數情況下，積體密度的改善已從最小特徵大小的反覆減少得到，該減少允許更多的元件可被整合至給定區域中。因為將電子裝置縮小之需求的增長，已浮現對於較小且更有創意之半導體晶片封裝技術的需求。此種封裝系統的一範例為堆疊式封裝層疊(Package-on-Package, PoP)技術。在堆疊式封裝層疊裝置中，頂部半導體封裝體被堆疊在底部半導體封裝體的頂部上，以提供高度積體化及元件密度。堆疊式封裝層疊技術一般能夠生產具有增強功能性且在印刷電路板(printed circuit board, PCB)上有小覆蓋區(footprints)的半導體裝置。
本發明實施例提供一種半導體封裝體的形成方法，包括形成一第一元件，且形成該第一元件包括：在一第一基板之上形成一第一重佈線結構；在第一重佈線結構之上形成一貫通孔；將一第一晶片貼附至第一重佈線結構，第一晶片的主動側面向且電性耦合至第一重佈線結構。半導體封裝體的形成方法更包括將一第二元件貼附至貫通孔，第二元件包括貼附至一第二基板的一第二重佈線結構、以及在貼附第二元件之後，在第一重佈線結構和第二重佈線結構之間沉積一成型模料，成型模料之部分圍繞第二重佈線結構的側邊邊緣。
本發明實施例亦提供一種半導體封裝體，包括一第一元件、一第二元件、以及一封裝膠。第一元件包括一第一重佈線結構、一貫通孔、以及一第一晶片。貫通孔設置在第一重佈線結構之上。第一晶片貼附至第一重佈線結構，且第一晶片的主動側面向第一重佈線結構。第二元件包括一第二重佈線結構、一連接器、以及一第二晶片。連接器將貫通孔耦合至第二重佈線結構。第二晶片貼附至第二重佈線結構的一第一側，第二晶片的主動側面向第二重佈線結構。封裝膠設置在第一重佈線結構和第二重佈線結構之間。
本發明實施例更提供一種半導體封裝體，包括一第一重佈線結構、一第二重佈線結構、一第一晶片、一第二晶片、一封裝膠、以及一貫通孔。第一重佈線結構具有一第一寬度。第二重佈線結構設置在第一重佈線結構之上，且包括從一第一金屬走線延伸至一第二金屬走線的一導電通孔。第一金屬走線沿著第二重佈線結構的一第一側設置，第二金屬走線沿著第二重佈線結構的一第二側設置。第二重佈線結構具有一第二寬度，且第一寬度大於第二寬度。第一晶片貼附至第一重佈線結構，第一晶片的一第一主動側面向且電性耦合至第一重佈線結構。第二晶片貼附至第二重佈線結構，第二晶片的一第二主動側面向且電性耦合至第二重佈線結構。封裝膠直接插入第一重佈線結構和第二重佈線結構之間。貫通孔延伸穿過封裝膠，貫通孔將第一重佈線結構電性耦合至第二重佈線結構。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，若是本揭露書敘述了一第一特徵形成於一第二特徵之上或上方，即表示其可能包含上述第一特徵與上述第二特徵是直接接觸的實施例，亦可能包含了有附加特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與第二特徵可能未直接接觸的實施例。另外，以下揭露書不同範例可能重複使用相同的參考符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所描述的不同實施例及/或結構之間有特定的關係。
再者，為了方便描述圖式中一元件或特徵與另一(複數)元件或(複數)特徵的關係，可使用空間相關用語，例如「下面」、「下方」、「之下」、「上方」、「之上」及類似的用語等。除了圖式所繪示的方位之外，空間相關用語涵蓋裝置在使用或操作中的不同方位。所述裝置也可被另外定位(旋轉90度或在其他方位上)，且同樣可對應地解讀於此所使用的空間相關描述。
根據一些實施例，一或多個積體電路晶片或其他裝置會貼附於多個雙邊重佈線結構(dual-sided redistribution structures)且嵌埋在封裝物中，以形成一半導體系統級封裝(system-in-package, SiP)結構。所述重佈線結構之一可具有扇出型(fan-out)設計，且其他的再分布結構可形成為載體型基板(carrier-type substrate)。積體電路晶片的放置和重佈線結構的佈置在整個封裝中提供了多樣性。此外，封裝和重佈線結構的設計、以及設計方法(methodology)使得較薄的系統級封裝結構具有較佳的強度和減量的整體封裝翹曲。
第1圖係表示根據一些實施例，一積體電路晶片50的剖視圖。積體電路晶片50將在隨後的製程封裝以形成一積體電路封裝體。積體電路晶片50可為一邏輯晶片(例如中央處理器(central processing unit, CPU)、圖形處理器(graphics processing unit, GPU)、單晶片系統(system-on-a-chip, SoC)、應用處理器(application processor, AP)、微控制器(microcontroller)等)、一記憶晶片(例如動態隨機存取記憶體(dynamic random access memory, DRAM)晶片、靜態隨機存取記憶體(static random access memory, SRAM)晶片等)、一電源管理晶片(例如電源管理積體電路(power management integrated circuit, PMIC)晶片)、一射頻(radio frequency, RF)晶片、一感應器晶片、一微機電系統(micro-electro-mechanical-system, MEMS)晶片、一訊號處理晶片(例如數位訊號處理(digital signal processing, DSP)晶片)、一前端晶片(例如類比前端(analog front-end, AFE)晶片)、類似物、或其組合。
積體電路晶片50可形成在一晶圓中，所述晶圓可包括在後續步驟中單體化(singulated)的多個相異裝置區域，以形成複數個積體電路晶片。積體電路晶片50可根據適用的製造製程處理以形成晶體電路。舉例而言，積體電路晶片50包括一半導體基板52，例如矽、摻雜或無摻雜、或絕緣層上矽晶(semiconductor-on-insulator, SOI)基板的主動層。半導體基板52可包括其他半導體材料，例如鍺、化合物半導體(包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦)、合金半導體(包括矽化鍺(SiGe)、磷化砷鎵(GaAsP)、砷化銦鋁(AlInAs)、砷化鋁鎵(AlGaAs)、砷化銦鎵(GaInAs)、磷化銦鎵(GaInP)、及/或砷磷化銦鎵(GaInAsP))、或其組合。例如多層或梯度(gradient)基板的其他基板亦可被使用。半導體基板52具有一主動表面(例如第1圖中面朝上的表面)和一非主動表面(例如第1圖中面朝下的表面)，主動表面有時被稱作一前側，且非主動表面有時被稱作一背側。
多個裝置(一個顯示於第1圖中)54可形成在半導體基板52的前表面。裝置54可為主動裝置(例如電晶體(transistors)、二極體(diodes)等)、電容、電阻等。一層間介電質(inter-layer dielectric, ILD)56在半導體基板52的前表面之上。層間介電質56圍繞裝置54且可覆蓋裝置54。層間介電質56可包括一或多個介電層，形成所述介電層的材料例如磷矽酸鹽玻璃(Phospho-Silicate Glass, PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass, BSG)、硼磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass, BPSG)、無摻雜矽玻璃(undoped Silicate Glass, USG)、或類似物。
導電插塞58延伸穿過層間介電質56且與裝置54物理地耦合。舉例而言，當裝置54為電晶體時，導電插塞58可與電晶體的閘極和源極/汲極區域耦合。導電插塞58可由鎢、鈷、鎳、銅、銀、金、鋁、類似物、或其組合形成。互連結構60在層間介電質56和導電插塞58之上。互連結構60和裝置54互連以形成一積體電路。舉例而言，互連結構60可由層間介電質56的介電層中的金屬化圖案形成。金屬化圖案包括由一或多個低介電系數(low-k)介電層形成的金屬線路和導通孔。互連結構60的金屬化圖案藉由導電插塞58電耦合至裝置54。
積體電路晶片50更包括多個襯墊62以建立外部連接，例如鋁襯墊。襯墊62位於積體電路晶片50的主動側，例如在互連結構60之中及/或之上。一或多個鈍化膜64位在積體電路晶片50上，例如位在互連結構60和襯墊62的部分上。開口延伸穿過鈍化膜64至襯墊62。晶片連接器66延伸穿過鈍化膜64中的開口，並物理地且電性地耦合至各個襯墊62。前述晶片連接器66例如為導電柱(舉例而言，由像是銅的金屬形成)。在一些實施例中，晶片連接器66包括凸塊下金屬化(under-bump metallization, UBM)結構。雖然第1圖中僅表示了四個晶片連接器66，但可能還有更多，將在積體電路晶片50的之後的繪圖中表示。舉例而言，晶片連接器66(例如銅柱)可由電鍍或類似方式形成。晶片連接器66電性地耦合積體電路晶片50的各個積體電路。
選擇性地，焊料區域(例如焊球或焊料凸塊，未圖示)可設置在襯墊62及/或晶片連接器66上。焊料區域可用來在積體電路晶片50上施行裸晶針測(chip probe, CP)試驗。裸晶針測試驗可在積體電路晶片50上施行以確認積體電路晶片50是否是為良裸晶粒(known good die, KGD)。因此，只有是良裸晶粒的積體電路晶片50會接受之後的製程而封裝，在裸晶針測試驗不合格的積體電路晶片50則不會封裝。在試驗之後，焊料區域可在之後的製程步驟移除。
一介電層68可(或可不)設在積體電路晶片50的主動側，例如在鈍化膜64和晶片連接器66上。介電層68橫向地封裝晶片連接器66，且介電層68在單體化後與積體電路晶片50橫向地相接。最初，介電層68可埋藏晶片連接器66，從而介電層68的最頂端表面會在晶片連接器66的最頂端表面之上。在焊料區域設置在晶片連接器66上的一些實施例中，介電層同樣可埋藏焊料區域。或者，焊料區域可在形成介電層68之前被移除。
介電層68可為聚合物(例如PBO、聚醯亞胺、BCB、或類似物)、氮化物(例如氮化矽或類似物)、氧化物(例如氧化矽、PSG、BSG、BPSG、或類似物)、類似物、或其組合。舉例而言，介電層68可藉由旋轉塗布、層壓、化學氣相沉積(chemical vapor deposition, CVD)、或類似方式形成。在一些實施例中，晶片連接器66在形成積體電路晶片50的期間通過介電層68暴露。在一些實施例中，晶片連接器66保持埋藏且在之後封裝積體電路晶片50的製程期間暴露。暴露晶片連接器66可移除任何存在在晶片連接器66上的焊料區域。
一黏貼層70可在製程中的某些時點施加在積體電路晶片50的背側。在一些實施例中，黏貼層是在將積體電路晶片貼附至一半導體封裝元件(將在以下詳述)之前形成在積體電路晶片50的背側之上。
在一些實施例中，積體電路晶片50為包括多個半導體基板52的疊層裝置。舉例而言，積體電路晶片50可為記憶體裝置，例如混合記憶體立方體(hybrid memory cube, HMC)模組、高頻寬記憶體(high bandwidth memory, HBM)模組、或包括多個記憶體晶片的類似物。在這些實施例中，積體電路晶片50包括多個藉由基板穿孔技術(through-substrate vias, TSVs)互連的半導體基板52。每個半導體基板52可(或可不)具有一互連結構60。
以下將描述根據一些實施例，包含積體電路晶片50的半導體封裝體的形成。第2A圖至第2G圖描述了根據一些實施例，一第一元件的形成中的各種中間步驟。如將要討論的，第一元件可包括具有積體電路晶片50貼附的一扇出型重佈線結構。第3A圖至第3H圖描述了根據一些實施例，一第二元件的形成，其中第二元件可貼附至參考第2A圖至第2G圖描述的第一元件。如將要討論的，第二元件可包括一基板型重佈線結構。雖然未特別描述，第二元件亦可包括一扇出型重佈線結構，且此扇出型重佈線結構與第一元件的扇出型重佈線結構類似。第4A圖至第4H圖描述了根據一些實施例，將第二元件貼附至第一元件，以及更進一步的製程以形成一半導體封裝體。
首先請參閱第2A圖，在一第一元件100的形成中，一第一承載基板102被提供，且一釋放層104形成在第一承載基板102上。第一承載基板102可為玻璃承載基板、陶瓷承載基板、或類似物。第一承載基板102可為晶圓，從而多個封裝體可同時形成在第一承載基板102上，其中每個封裝體可包含一或多個晶片。釋放層104可由一聚合物基材料(polymer-based material)形成，其可以與第一承載基板102一同從上覆結構移除，所述上覆結構是在之後的步驟中形成。在一些實施例中，釋放層104為環氧基材料(epoxy-based material)，其會在加熱時失去自身的黏著性，例如光熱轉換(light-to-heat-conversion, LTHC)防黏塗料。在一些實施例中，釋放層104可為紫外光(ultraviolet, UV)膠，其會在暴露於紫外光光線時失去自身的黏著性。釋放層104可以液體形式分配且固化，可以為層壓在第一承載基板102上的層壓膜，或者可以為類似物。
在第2B圖至第2E圖中，一第一側重佈線結構106可形成在釋放層104上。在所示的實施例中，第一側重佈線結構106包括一或多個介電層和金屬化圖案(有時稱作重佈線層或重佈線線路)。第一側重佈線結構106將被描述為具有三層金屬化圖案。更多或更少的介電層和金屬化圖案亦可形成在第一側重佈線結構106中。若更少的介電層和金屬化圖案要被形成，以下討論的步驟和製程可被省略。若更多的介電層和金屬化圖案要被形成，以下討論的步驟和製程可被重複。
現請參閱第2B圖，一介電層110形成在釋放層104上。介電層110的底面可接觸釋放層104的頂面。在一些實施例中，介電層110可由感光材料(photo-sensitive material)形成，例如聚苯並噁唑(polybenzoxazole, PBO)、聚醯亞胺、苯並環丁烯(benzocyclobutene, BCB)、或類似物，其可利用微影遮罩來圖案化。在一些實施例中，介電層110由氮化物形成，例如氮化矽、磷矽酸鹽玻璃(phosphosilicate glass, PSG)、硼矽酸鹽玻璃(borosilicate glass, BSG)、硼磷矽酸鹽玻璃(boron-doped phosphosilicate glass, BPSG)、或類似物。介電層110可藉由旋轉塗布、層壓、化學氣相沉積、類似方式、或其組合形成。介電層110被圖案化，以形成使釋放層104的部分暴露的開口。圖案化可藉由可接受的製程，例如藉由將介電層110暴露至光線、顯影、以及在介電層110是感光材料時固化，或是藉由蝕刻，舉例而言，使用各向異性蝕刻。
金屬化圖案112接著形成在介電層110上。金屬化圖案112包括線路部分(亦被稱為導線)，位於介電層110的主要表面上且沿著介電層110的主要表面延伸。金屬化圖案112更包括導通孔部分(亦被稱為導電通孔)，延伸穿過介電層110以使第一側重佈線結構106與外部連接器物理地且電性地耦合，所述外部連接器可在之後的步驟中形成。作為形成金屬化圖案112的一個範例，一晶種層(seed layer)形成在介電層110之上、以及在延伸穿過介電層110的開口中。在一些實施例中，晶種層為一金屬層，其可為單層或包括複數個由不同材料形成的子層的複合層。在一些實施例中，晶種層包括一鈦層和一銅層，銅層位在鈦層之上。舉例而言，晶種層可利用物理氣相沉積(physical vapor deposition, PVD)或類似方式形成。一光阻接著形成且圖案化於晶種層上。光阻可藉由旋轉塗布或類似方式形成，且可暴露至光線以圖案化。光阻的圖案對應於金屬化圖案112。圖案化將形成穿過光阻的開口，以暴露晶種層。一導電材料接著形成在光阻的開口中、以及在晶種層的暴露部分上。導電材料可藉由電鍍(例如有電電鍍(electroplating)或無電電鍍(electroless plating))或類似方式形成。導電材料可包括金屬，像是銅、鈦、鎢、鋁、或類似物。光阻和晶種層上沒有形成導電材料的部分將被移除。光阻可藉由可接受的灰化(ashing)或剝除(stripping)製程移除，例如利用氧電漿(oxygen plasma)或類似物。一旦光阻被移除，晶種層的暴露部分將被移除，例如藉由使用可接受的蝕刻製程，像是藉由濕式蝕刻或乾式蝕刻。導電材料的保留部分和晶種層的底層部分形成金屬化圖案112。
在第2C圖中，一介電層114沉積在金屬化圖案112和介電層110上。介電層114可以以與介電層110類似的方式形成和圖案化。
接著形成金屬化圖案116。金屬化線路116包括線路部分，位於介電層114的主要表面上且沿著介電層114的主要表面延伸。金屬化圖案116更包括導通孔部分，延伸穿過介電層114以物理地且電性地耦合金屬化圖案112。金屬化圖案116可以以與金屬化圖案112類似的方式和類似的材料形成。在一些實施例中，金屬化圖案116具有與金屬化圖案112不同的尺寸。舉例而言，金屬化圖案112的導線及/或導通孔可較寬或較厚於金屬化圖案116的導線及/或導通孔。再者，金屬化圖案112可形成為跟金屬化圖案116相比具有更大的間距。
在第2D圖中，一介電層118沉積在金屬化圖案116和介電層114上。介電層118可以以與介電層110及/或介電層114類似的方式形成和圖案化。
接著形成金屬化圖案120。金屬化圖案120包括線路部分，位於介電層118的主要表面上且沿著介電層118的主要表面延伸。金屬化圖案120更包括導通孔部分，延伸穿過介電層118以物理地且電性地耦合金屬化圖案116。金屬化圖案120可以以與金屬化圖案112及/或金屬化圖案116類似的方式和類似的材料形成。
在第2E圖中，一介電層122沉積在金屬化圖案120和介電層118上。介電層122可以以與介電層110類似的方式形成和圖案化，以形成開口124。
介電層110和金屬化圖案112分別為第一側重佈線結構106最底部的介電層和金屬化圖案。因此，第一側重佈線結構106之所有中間的介電層和金屬化圖案(例如介電層114、118、122，以及金屬化圖案116、120)會設置在介電層110/金屬化圖案112和隨後要形成或貼附在第一側重佈線結構106之上的元件之間。在一些實施例中，金屬化圖案112具有與金屬化圖案116、120不同的尺寸。舉例而言，金屬化圖案112的導線可具有約0.5微米至約15微米的厚度、或約5微米的厚度，且金屬化圖案116和120的導線可具有約0.5微米至約15微米的厚度、或約5微米的厚度。金屬化圖案112的厚度和金屬化圖案120的厚度的比值可為約0.3至約3、或約1。再者，金屬化圖案112可形成為跟金屬化圖案116、120相比具有更大的間距。舉例而言，金屬化圖案112的導線可具有約1微米至約100微米的間距、或約10微米的間距，且金屬化線路116和120的導線可具有約1微米至約100微米的間距、或約10微米的間距。金屬化圖案112的間距和金屬化圖案120的間距的比值可為約0.1至約10、或約1。應注意的是，第一側重佈線結構106可包括任何數量的介電層和金屬化圖案。若更多的介電層和金屬化圖案要被形成，前述步驟和製程可被重複。
在第2F圖中，貫通孔(through vias)126形成在一些開口124中，且往遠離第一側重佈線結構106的最頂部的介電層(例如介電層122)的方向延伸。作為形成貫通孔126的一個範例，一晶種層(未圖示)形成在第一側重佈線結構106之上，例如在介電層122和金屬化圖案120藉由開口暴露的部分上。在一些實施例中，晶種層為一金屬層，其可為單層或包括複數個由不同材料形成的子層的複合層。在一些實施例中，晶種層包括一鈦層和一銅層，銅層位在鈦層之上。在一些實施例中，晶種層由銅、鈦、鎳、金、鈀、類似物、或其組合製成。舉例而言，晶種層可利用物理氣相沉積(physical vapor deposition, PVD)或類似方式形成。一遮罩(例如一光阻(未圖示))形成且圖案化於晶種層上。光阻可藉由旋轉塗布或類似方式形成，且可暴露至光線以圖案化。光阻的圖案對應於貫通孔126且暴露晶種層。一導電材料接著形成在光阻的開口中、以及在晶種層的暴露部分上。導電材料可藉由電鍍(例如電化學電鍍製程(electro-chemical plating process)或無電電鍍(electroless plating))、化學氣相沉積、原子層沉積(atomic layer deposition, ALD)、物理氣相沉積、類似方式、或其組合形成。導電材料可包括金屬，像是銅、鈦、鎢、鋁、或類似物。光阻可被移除。
請繼續參閱第2F圖，接合墊128形成在一些開口124中，且往遠離介電層122的方向延伸。接合墊128可以以與貫通孔126類似的方式形成，且可由與貫通孔126相同的材料形成。此外，接合墊128可在貫通孔126之前、之後、或同時形成。
用於接合墊128和貫通孔126的光阻以及晶種層上未形成接合墊128和貫通孔126的部分將被移除。光阻可藉由可接受的灰化或剝除製程移除，例如利用氧電漿或類似物。一旦光阻被移除，晶種層的暴露部分將被移除，例如藉由使用可接受的蝕刻製程，像是藉由濕式蝕刻或乾式蝕刻。晶種層和導電材料的保留部分形成接合墊128和貫通孔126。
如前所述，一積體電路晶片(例如參考第1圖前述的積體電路晶片50)可貼附至接合墊128。在一些實施例中，接合墊128為凸塊下金屬化結構(UBMs)，舉例而言，其可包括三層導電材料，像是一層鈦、一層銅、以及一層鎳。其他材料和層的配置亦可被利用來形成接合墊128，例如鉻/鉻-銅合金/銅/金的配置、鈦/鎢化鈦/銅的配置、或銅/鎳/金的配置。可使用於接合墊128的任何適合的材料和材料層完全包含於本發明實施例的範圍中。
在第2G圖中，一或多個半導體裝置(例如第一積體電路晶片50)將貼附至接合墊128，以建立與第一側重佈線結構106的電性連接。舉例而言，第一積體電路晶片50可藉由在晶片連接器66(無論是導電柱或是凸塊下金屬化結構)上形成焊點130、將晶片連接器66壓至接合墊128、以及回焊焊點130以將第一積體電路晶片50貼合至第一側重佈線結構106來貼合。在一些實施例中，第一積體電路晶片50可利用直接金屬-金屬鍵合(direct metal-to-metal bonding)或混合鍵合(hybrid bonding)來貼附。第2G圖描繪了積體電路晶片50為具有比貫通孔126更高的高度。然而，應注意的是，貫通孔126可具有與積體電路晶片50大約相等的高度或比積體電路晶片50更高的高度。舉例而言，貫通孔126可具有約10微米至約200微米的高度HTV ，且積體電路晶片50可具有約30微米至約250微米的高度HIC1 。高度HTV 和高度HIC1 的比值可為約0.04至約8。
應注意的是，對於積體電路晶片50而言，第一側重佈線結構106可為一扇出型重佈線結構。因此，金屬化圖案(例如金屬化圖案112、116、120)在橫向方向上可比積體電路晶片50更為延伸。扇出型設計允許了更薄的重佈線結構，且亦可容置更多的外部連接器，所述外部連接器可因而在橫向方向上比積體電路晶片50更為延伸。第一側重佈線結構106形成為具有厚度T1 ，此厚度T1 可為約20微米至100微米。
一底部填充材料(underfill material)132可分配在第一積體電路晶片50和第一側重佈線裝置106之間。底部填充材料132圍繞焊點130和接合墊128。底部填充材料132可為任何可接受的材料，例如聚合物、環氧樹脂、模製底膠(molding underfill)、或類似物。底部填充材料132可利用針頭或噴射分配器分配、利用毛細管流製程分配、或利用其他適合的製程分配。在一些實施例中，一固化製程可被執行，以固化底部填充材料132。雖然未明確地顯示於第2G圖中，底部填充材料132可沿著第一積體電路晶片50的側壁延伸。
為了說明的目的，第2G圖係表示貼附至接合墊128的單一積體電路晶片50。在一些實施例中，兩個或多個積體電路晶片50(每個積體電路晶片50具有相同或不同的功能)可貼附至接合墊128。
第3A圖至第3H圖係表示根據一些實施例，形成一第二元件200的製程期間的中間步驟的剖視圖。如前所述，第二元件200可接著貼附至關於第2A-2G圖所述的第一元件100上。第二元件200可形成為個別的封裝體或可由晶圓級(wafer-level)製程形成。只有一個個別的封裝元件200被表示，但應注意的是第二元件200可為晶圓的一部分。在形成後，個別的第二元件200將單體化。最終的第二元件200亦可被稱作一積體封裝體(integrated package)。
在第3A圖中，一第二承載基板202被提供，且一第二側重佈線結構可形成在第二承載基板202上。第二承載基板202可為玻璃承載基板、陶瓷承載基板、或類似物。第二承載基板202可為晶圓，從而多個封裝體可同時形成在第二承載基板202上。一第一金屬膜204形成在第二承載基板202上。第一金屬膜204可包括銅，像是一銅箔(copper foil)。第二承載基板202可具有約10微米至約400微米的厚度、或約200微米的厚度。第一金屬膜204可具有約1微米至約20微米的厚度、或約3微米的厚度。第一金屬膜204可包括銅或其他導電材料。
在第3B圖中，一光阻208接著在第一金屬膜204上形成和圖案化。光阻208可藉由旋轉塗布或類似方式形成，且可暴露至光線以圖案化。圖案化將形成穿過光阻208的開口，以暴露第一金屬膜204。
在第3C圖中，一第二側重佈線結構206形成在第一金屬膜204之上。首先，一第一金屬走線210形成在第一金屬膜204之上，且光阻208被移除。第一金屬走線210可藉由有電電鍍形成且可包括一或多層導電材料。舉例而言，一層金(Au)可首先沉積，一層鎳(Ni)其次，且一層銅(Cu)在最後。金可沉積為厚度大於或大約0.1微米，例如約0.01微米至約3微米。鎳可沉積為厚度大於或大約3微米，例如約0.1微米至約10微米。銅可沉積為厚度大於或大約7微米，例如約1微米至約25微米。因此，第一金屬走線210可具有厚度大於或大約1微米至35微米，例如大於或大約10微米。像是這樣的厚度有益於將第一金屬走線210黏貼至第一金屬膜204、保持內部凝聚力(internal cohesiveness)、及/或提供充足的導電性能。少於此的厚度可能會造成較差的黏著性、凝聚力、及/或導電性。光阻208可藉由任何適合的剝除方法移除。
在第3D圖中，一介電層212形成在第一金屬走線210之上。介電層212可藉由一熱層壓製程(thermal lamination process)形成。介電層212可包括預浸料(prepreg)或ABF膜(Ajinomoto Build-up Film)。在一些實施例中，介電層212可為具有約10微米至約100微米的厚度的預浸料，例如約30微米，或可為具有約10微米至約100微米的厚度的ABF膜，例如約20微米。使用預浸料或ABF膜材料作為介電層212的好處為第二側重佈線結構206將具有高等級的強度和可靠度。當之後與第一側重佈線結構106耦合時，整個半導體封裝體將不易翹曲。
在第3E圖中，介電層212被圖案化以形成暴露第一金屬走線210之部分的開口。開口包括通孔開口(via openings)214，延伸穿過介電層212以暴露第一金屬走線210的部分。開口更包括線路開口(line openings)216，連接通孔開口214且提供佈線可能性(routing capabilities)。介電層212可利用單一鑲嵌(damascene)或雙鑲嵌製程圖案化。圖案化可藉由任何適合的方法執行，例如形成一光阻並濕式蝕刻或乾式蝕刻介電層212及/或使用一雷射剝蝕(laser ablation)(或雷射鑽孔(laser drilling))技術。雖然描繪為垂直側壁，應注意的是，雷射鑽孔技術可產生具有非垂直側壁的通孔開口214。通孔開口214可具有約30微米至約150微米的寬度，例如約65微米。
在第3F圖中，在介電層212上方區域的通孔開口214和線路開口216將填充一導電材料，以形成導電通孔218(在通孔開口214中)和第二金屬走線220(在線路開口216中)。導電材料可藉由有電電鍍或無電電鍍、或任何適合的方法沉積。第二金屬走線220可具有約10微米的厚度。或者，導電通孔218可在介電層212被圖案化以形成第二金屬走線220之前在最初形成。
第二側重佈線結構206(包括第一金屬走線210、導電通孔218、以及第二金屬走線220)形成為具有厚度T2 ，此厚度T2 可為約20微米至約150微米。第二側重佈線結構206的厚度可大於或相等於背側重佈線結構106的厚度T1 。厚度T2 和厚度T1 的比值可為約0.3至約3。比值在此範圍內提供了合適的剛性以避免或減少因為不同的熱膨脹係數(coefficient of thermal expansions, CTEs)而產生的翹曲，舉例而言，當第二元件200接著貼附至第一元件100時，第一側重佈線結構106的介電層和金屬化圖案以及包括積體電路晶片50的材料的不同熱膨脹係數。比值小於此數值可能無法提供充足的剛性予第二元件200以抗衡第一元件100的元件膨脹。比值大於此數值可能會增加訊號長度，從而減少了封裝裝置的性能。
在第3G圖中，阻焊材料222形成且圖案化以形成暴露導電通孔218及/或第二金屬走線220的開口224。此外，為了保護的目的，導電通孔218和第二金屬走線220的暴露部分可被處理。舉例而言，化鎳鈀金(eletroless nickel electroless palladium immersion glod, ENEPIG)處理或有機保焊劑(organic solderability preservative, OSP)可於導電通孔218和第二金屬走線220的暴露部分實施。阻焊材料可具有約5微米至約40微米的厚度，例如約10微米。阻焊材料222亦可用來保護第二側重佈線結構206的保護區域不受外部損害。
在第3H圖中，連接器226形成在導電通孔218和第二金屬走線220的暴露部分之上。連接器226可為焊球，以類似於第一積體電路晶片50上的焊料區域的方法形成，且可以以類似於第一積體電路晶片50上的焊料區域的材料形成。
就晶圓級製程以形成第二元件200而言，一單體化製程可藉由沿著相鄰第二元件200的劃線區域(切割道)鋸切來執行。如以下所說明的，生成的單體化的第二元件200耦合至第一元件100。在一些實施例中，在第二元件200貼附之前，第一元件100也類似地單體化。在一些實施例中，第一元件100在貼附至第二元件200後單體化。
第4A圖至第4H圖係表示根據一些實施例，貼附第二元件200至第一元件100的中間步驟的剖視圖，以及額外製程，以形成一封裝體400。
首先請參閱第4A圖，封裝體400被表示，其中第一元件100為晶圓的一部份。在一些實施例中(但未表示於第4A圖中)，第一元件100在劃線區域404已經單體化。
每個單體化的第二元件200利用連接器226安裝至第一元件100。如前所述，第一元件100包括用來貼附的貫通孔126。因此，連接器226結合至對應的貫通孔126。在一些實施例中，連接器226被回焊以將第二元件200貼附至貫通孔126。連接器226將第二元件200電性耦合至第一封裝元件100的第一側重佈線結構106。連接器226可具有形成於其上的環氧樹脂助焊劑(epoxy flux，未圖示)，因為在第二元件200貼附至第一元件100之後，其會與餘留的環氧樹脂助焊劑的環氧樹脂部分的至少一些回焊。此餘留的環氧樹脂部分可充當底部填充體，以減少應力且保護回焊連接器226產生的接點。在第二元件200貼附至第一元件100之後，第一側重佈線結構106和第二側重佈線結構206可彼此分離一厚度T3 。厚度T3 可為約50微米至約500微米。厚度T3 和厚度T1 的比值可為約0.4至約5。厚度T3 和厚度T2 的比值可為約0.3至約4。
在第4B圖中，一封裝膠(encapsulant)310形成在第一元件100之上且包圍第二元件200。封裝膠310更封裝貫通孔126、第一積體電路晶片50、以及貼附至第一元件100及/或第二元件200的任何其他裝置(若有)。封裝膠310更形成在相鄰第二元件200的間隙區域中。封裝膠310可在第二封裝元件200貼附之後藉由一毛細管流製程形成、或在第二封裝元件200貼附之前藉由一適合的沉積方法形成。在一些實施例中，封裝膠310可藉由壓縮成型(compression molding)、轉注成型(transfer molding)、或類似方法施加。封裝膠310可以液體或半液體(semi-liquid)形式被施加，且接著隨後固化。封裝膠310可為成型模料(molding compound)、環氧樹脂、或類似物。
如第4B圖中的插圖401、402所表示，封裝膠310可形成為包圍第二元件200的第二側重佈線結構206的側邊邊緣。封裝膠310可部分地或完全地覆蓋第二元件200的側邊邊緣。舉例而言，如插圖401所描繪，封裝膠310可具有凹陷的上表面，其最高點位於接近的二元件200的側邊邊緣。封裝膠310可部分地或完全地覆蓋的二側重佈線結構206的側邊邊緣。在一些實施例中，封裝膠310更可覆蓋第二承載基板202的側邊邊緣的部分。此外，上表面的最低點可低於第二側重佈線結構206最接近第二承載基板202的部分。如插圖402所描繪，封裝膠310可形成來覆蓋的二側重佈線結構206的所有側邊邊緣，以及第二承載基板202的所有或部分側邊邊緣。在一些實施例中，封裝膠310可覆蓋第二承載基板202的全部的側邊邊緣，甚至是第二承載基板202的上表面的部分(未特別繪出)。
封裝膠310提供了第二側重佈線結構206額外的支持，這使得整體封裝體400更強固、更可靠、且更不易翹曲。如前所述，增加的強度和堅固性是由封裝膠310的上部分黏貼至第二元件200的側邊邊緣而來。封裝膠310可朝遠離第二元件200之側邊邊緣的方向向下傾斜，如第4B圖的插圖401所描繪。傾斜可與水平線成一角度θ。所述角度θ可為約0度至約45度、或約45度至約60度。
在第4C圖中，根據一些實施例，第二承載基板202從封裝體400移除，暴露第二側重佈線結構206。第二承載基板202可利用例如一熱處理來改變設置在第二承載基板202上的釋放層的黏著性，以從第二側重佈線結構206拆卸(demounted)、脫膠(debonded)、或機械地剝離(peeled off)。在一些實施例中，一能量源被利用來照射及加熱釋放層直到釋放層失去至少一些自身的黏著性，所述能量源例如為一紫外線(ultraviolet, UV)雷射、一二氧化碳(carbon dioxide, CO2 )雷射、或一紅外線(infrared, IR)雷射。一旦執行後，第二承載基板202和金屬膜204可物理地分離且從第二側重佈線結構206移除。在一些實施例中，一平坦化製程或一機械剝離製程可被執行，以移除第二承載基板202來暴露第二側重佈線結構206。平坦化結構亦可移除一些可能形成在第二側重佈線結構206的上層之上的封裝膠310。舉例而言，平坦化結構可為化學機械拋光(chemical-mechanical polish, CMP)、研磨製程、或類似方式。需特別說明的是，即便在本實施例中封裝膠310形成為完全覆蓋第二元件的側邊邊緣(且或許在第二承載基板202的上表面之上(例如大體描繪在第4B圖的插圖402中))，因為第二承載基板202的保護，封裝體400仍不易在第二側重佈線結構206的上表面上成型蔓延(creep)封裝膠310。因此，在移除第二承載基板202後，第二側重佈線結構206的上表面沒有封裝膠310。因此，封裝膠310的最頂部表面可以與第二側重佈線結構206的上表面齊平或自第二側重佈線結構206的上表面凹陷。
請繼續參閱第4C圖，在一些實施例中，鈍化層320在暴露的第二側重佈線結構206之上形成和圖案化。鈍化層320可為一介電材料，其形成的方法和材料可類似於介電層110、114、118、122中的任一者。或者，鈍化層320可為一阻焊材料，其形成的方法和材料可類似於阻焊材料222。
在第4D圖中，封裝體400可翻轉於臨時基板406之上且貼附於臨時基板406，所述臨時基板406例如為膠帶、晶圓、面板、框架、環體、或類似物。第一承載基板102接著被移除。在一些實施例中，承載基板拆除被執行以使第一承載基板102從第一側重佈線結構106分離(或拆卸或脫膠)，例如介電層110。根據一些實施例，拆除包括投射光線(例如雷射光或紫外線光)在釋放層104上，從而釋放層104在光線的熱能之下分解，第一承載基板102可被移除。
在第4E圖中，導電連接器410形成在第一側重佈線結構106上。導電連接器410可為球柵陣列封裝(ball grid array, BGA)連接器、焊球、金屬柱、C4(controlled collapse chip connection)凸塊、微凸塊、化鎳鈀金技術(ENEPIG)形成的凸塊、或類似物。導電連接器410可包括一導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物、或其組合。在一些實施例中，導電連接器410藉由最初通過蒸鍍法(evaporation)形成一層焊料、有電電鍍、印製(printing)、焊料轉移(solder transfer)、植球(ball placement)、或類似方式形成。一旦一層焊料形成在結構上，回焊可被執行，以使材料被塑形為所所需的凸塊形狀。在另一實施例中，導電連接器410包括金屬柱(例如銅柱)，藉由濺鍍、印製、有電電鍍、無電電鍍、化學氣相沉積、或類似方式形成。金屬柱可不需要焊料且可具有大致垂直的側壁。在一些實施例中，一金屬蓋層形成在金屬柱的頂部。金屬蓋層可包括鎳、錫、錫鉛(tin-lead)、金、銀、鈀、銦、鎳鈀金(nickel-palladium-gold)、鎳金(nickel-gold)、類似物、或其組合，且可藉由電鍍製程形成。
根據一些實施例，若尚未單體化，結構可接著沿著劃線區域404(例如參見第4A圖)單體化。或者，結構可在形成導電連接器410之前單體化。在一些實施例中，結構可利用一或多個鋸刃單體化，將封裝體400分開為分離的片塊，形成一或多個單體化封裝體400。然而，任何適合的單體化方法(包括雷射剝蝕(laser ablation)或一或多個濕式蝕刻)也可以被利用。
在單體化之後，第一側重佈線結構106具有寬度W1 ，所述寬度W1 可為約3毫米至約150毫米。第二元件200及其第二側重佈線結構206具有寬度W2 ，所述寬度W2 可為約3毫米至約150毫米。寬度W2 可小於或相等於寬度W1 (例如第一元件及其第一重佈線結構106的寬度)。寬度W1 和寬度W2 的比值可為約1至約3、或約1。比值在此範圍中可使整個半導體封裝體在第二側重佈線結構206耦合至第一側重佈線結構106時不易翹曲。換言之，第二側重佈線結構206的強度和寬度W2 將平衡第一側重佈線結構106可能會發生的翹曲。
在第4F圖和第4G圖中，在單體化之後，封裝體400可從臨時基板406移除，並翻轉於另外的基板之上且貼附至此另外的基板，所述另外的基板例如基板503(例如承載基板、封裝基板、印刷電路板(PCB)、或類似物)。如圖所示，封裝體400可以以鈍化層320作為特點(第4F圖)或者鈍化層320可被省略(第4G圖)。在封裝體400中的一些情況中，貫通孔126可對齊導電通孔218，如第4G圖的擴展部分所描繪。取決於形成的方法，導電通孔218可具有向內傾斜的側壁。在一些情況下，向內傾斜的側壁可具有內凹(concave)形狀，使導電通孔218具有沙漏形狀。此外，導電通孔218可具有齒狀側壁。齒狀側壁某些部份是歸因於鑽孔穿過介電層212的雷射剝蝕方式，如關於第3F圖先前所說明的。
在第4H圖中，示出了一個實施例，類似於關於第4F圖先前所說明的，其中額外裝置511貼附至基板503。額外裝置511可包括主動裝置及/或被動裝置，例如積體被動裝置(integrated passive devices)和表面安裝元件(surface mount devices, SMD)(例如電容)。此外，額外裝置511可包括類似於積體電路晶片50的裝置，以及為了預期目的設計的裝置，像是記憶體晶片(例如動態隨機存取記憶體(DRAM)晶片、堆疊式記憶體晶片(stacked memory die)、高頻寬記憶體(HBM)晶片等)、邏輯晶片、中央處理器(CPU)晶片、單晶片系統(SoC)、晶圓上元件(a component on a wafer, CoW)、積體扇出型結構(integrated fan-out structure, InFO)、封裝體、類似物、或其組合。
第5A圖至第5H圖以及第6A圖至第6H圖描述了根據一些實施例，形成第一元件(包括第一積體電路晶片50)、形成第二元件(包括第二積體電路晶片50的貼附)、以及將第二元件貼附至第一元件和形成半導體封裝體的其他製程的各種中間步驟。
第5A圖至第5H圖係表示根據一些實施例，形成第一元件501、第二元件502、以及封裝體504的中間步驟的剖視圖。具體而言，所述圖式描繪了形成第一元件501、將第二元件502貼附至第一元件501(以及額外步驟)以形成封裝體504的某些中間步驟。
在第5A圖中，第一元件501的第一側重佈線結構106被提供，且貫通孔126和接合墊128形成在第一側重佈線結構106之上。類似於先前關於第2A圖至第2F圖所說明的製程和材料可被使用。在第5B圖中，第一積體電路晶片50與一或多個其他的半導體裝置550一起貼附(僅表示了一個，但可有複數個額外的半導體裝置)。類似於先前關於第2G圖所說明的製程和材料可被使用。
第一積體電路晶片50和其他裝置550可包括為了預期目的設計的裝置，像是記憶體晶片(例如動態隨機存取記憶體(DRAM)晶片、堆疊式記憶體晶片(stacked memory die)、高頻寬記憶體(HBM)晶片等)、邏輯晶片、中央處理器(CPU)晶片、單晶片系統(SoC)、晶圓上元件(CoW)、積體扇出型結構(InFO)、封裝體、類似物、或其組合。第一積體電路晶片50和其他裝置550可在同一技術節點(technology node)的製程中形成，或是可在相異技術節點的製程中形成。舉例而言，第一積體電路晶片50可為比其他裝置550更進步的技術節點。第一積體電路晶片50和其他裝置550可具有相異尺寸(例如相異高度及/或表面面積)，或可具有相同尺寸(例如相同高度及/或表面面積)。第一側重佈線結構106的優勢在於在積體電路晶片50、其他裝置550、隨後貼附的第二元件502、以及隨後貼附至第一側重佈線結構106的另一側的元件之間提供電性連接。
在一些實施例中，第一積體電路晶片50和其他裝置包括電晶體、電容、電感、電阻、金屬化層、外部連接器、以及類似物在其中，為了特定功能設計。在一些實施例中，第一積體電路晶片50和其他裝置可包括多於一個相同類型的裝置，或可包括不同的裝置。第5B圖顯示了單一積體電路晶片50，但在一些實施例中，一個、兩個、或更多的積體電路晶片50或其他裝置可貼附至第一側重佈線結構106。第5B圖描繪了積體電路晶片50為具有比貫通孔126較低的高度。這是為了容置第二元件502，第二元件502將包括另一積體電路晶片(如之後的圖式中所示)。舉例而言，貫通孔126可具有約10微米至約200微米的高度HTV ，且積體電路晶片50可具有約30微米至約250微米的高度HIC1 。高度HTV 和高度HIC1 的比值可為約0.04至約8。
在第5C圖中，提供了第二元件502的第二側重佈線結構206，且阻焊材料222可形成和圖案化，以形成除了開口224以外的開口228。類似於先前關於第3A圖至第3H圖所說明的製程和材料可被使用。一些或所有的開口228可暴露導電通孔218和第二金屬走線220的部分。開口228與開口224可使用相同或不同的圖案化方法同時形成或在不同時間點形成。
在第5D圖中，一第二積體電路晶片50可於開口228處貼附至第二側重佈線結構206，且電性耦合至導電通孔218和第二金屬走線220。類似於先前關於第2G圖至第5B圖所說明的製程和材料可被使用，包括接合墊528、焊料接點530、以及底部填充材料532的形成。此外，連接器226可在開口224中形成。
在第5E圖中，第二元件502(包括第二側重佈線結構206和第二積體電路晶片50)貼附至第一元件501，且第二承載基板202利用類似於先前關於第4A圖至第4C圖所說明的製程和材料移除。如先前關於封裝體400所說明的，封裝體504具有的第一側重佈線結構106的寬度W1 大於第二側重佈線結構206的寬度W2 ，且可形成封裝膠310包圍第二側重佈線結構206的側邊邊緣，類似於第4B圖至第4H圖所示。如所示，第二元件502被貼附，從而第一積體電路晶片50和第二積體電路晶片50的背側相互面向對方。第一和第二積體電路晶片50的任一者或兩者可具有沿著背側的介電層510，其可接著直接插入於第一和第二積體電路晶片50之間。
請繼續參閱第5E圖，介電層510可類似於黏貼層70，且可以以類似方式應用。第一和第二積體電路晶片50可垂直地排列，因此第二積體電路晶片50的至少一部份直接在第一積體電路晶片的至少一部份之上。第一和第二積體電路晶片50可位於彼此中央，或者是非對稱地設置。
封裝體504可接著被完成，如第5F圖至第5H圖所示，且可以以如前所述的類似方式，例如關於第4D圖至第4H圖。如第5G圖所示，第三積體電路晶片50可藉由類似於先前關於第2G、5B、5D圖所說明的製程和材料貼附至第一側重佈線結構106。如第5H圖所示，第四積體電路晶片50和額外裝置550可利用類似於先前關於第2G、4H、5B、5D圖所說明的製程和材料貼附至第二側重佈線結構206。前述佈置的優勢包括在水平方向給予更狹小的封裝體504及/或沿著第一側重佈線結構106提供更多空間以貼附額外裝置。
如前所述，第一側重佈線結構106和第二側重佈線結構206分離一厚度T3 。在本實施例中，厚度T3 可為約60微米至約500微米。厚度T3 和厚度T1 的比值可為約0.5至約25。厚度T3 和厚度T2 的比值可為約0.4至約25。此外，連接器226可具有約10微米至約300微米的高度HC 、或約150微米。因此，封裝體504中的貫通孔126和連接器226的總高度可為約50微米至約500微米、或約250微米(應注意的是總高度可小於高度HC 和高度HTV 的總合，因為回焊了連接器226)，所述總高度可大致相等於第一側重佈線結構106和第二側重佈線結構206之間的區域的厚度T3 。再如第5H圖所示，第一積體電路晶片50和第二積體電路晶片的總高度(分別為高度HIC1 和高度HIC2 ，加上介電層510的厚度)可大致相等於厚度T3 。
第6A圖至第6H圖係表示根據一些實施例，形成封裝體604的中間步驟的剖視圖。具體而言，所述圖式描繪了形成第一元件601、將第二元件602貼附至第一元件601(以及額外步驟)以形成封裝體604的某些中間步驟。
在第6A圖中，第一元件601的第一側重佈線結構106被提供，且貫通孔126和接合墊128形成在第一側重佈線結構106之上。類似於先前關於第2A圖至第2F圖和第5A圖所說明的製程和材料可被使用。在第6B圖中，第一積體電路晶片50與一或多個其他的半導體裝置650一起貼附。類似於先前關於第2G圖和第5B圖所說明的製程和材料可被使用。第6B圖描繪了積體電路晶片50為具有比貫通孔126較低的高度。這是為了容置第二元件602，第二元件602將包括另一積體電路晶片50。舉例而言，貫通孔126可具有約10微米至約300微米的高度HTV ，且積體電路晶片50可具有約30微米至約300微米的高度HIC1 。高度HTV 和高度HIC1 的比值可為約0.03至約10。
在第6C圖中，提供了第二元件602的第二側重佈線結構206，且阻焊材料222可形成和圖案化，以形成除了開口224以外的開口228。類似於先前關於第3A圖至第3H圖和第5C圖所說明的製程和材料可被使用。一些或所有的開口228可暴露導電通孔218和第二金屬走線220的部分。開口228與開口224可使用相同或不同的圖案化方法同時形成或在不同時間點形成。
在第6D圖中，一第二積體電路晶片50可於開口228處貼附至第二側重佈線結構206，且電性耦合至導電通孔218和第二金屬走線220。類似於先前關於第2G、5B、5D、6B圖所說明的製程和材料可被使用，包括接合墊628、焊料接點630、以及底部填充材料632的形成。
在第6E圖中，第二元件602(包括第二側重佈線結構206和第二積體電路晶片50)貼附至第一元件601，且第二承載基板202利用類似於先前關於第4A圖至第4C圖和第5E圖所說明的製程和材料移除。如先前關於封裝體400、504所說明的，封裝體604具有的第一側重佈線結構106的寬度W1 大於第二側重佈線結構206的寬度W2 ，且可形成封裝膠310包圍第二側重佈線結構206的側邊邊緣，類似於第4B圖至第4H圖所示。如所示，第二元件602被貼附，從而第二積體電路晶片50從第一積體電路晶片50橫向地位移。此橫向位移允許第二積體電路晶片50的背側表面低於第一積體電路晶片50的背側表面，雖然所述背側表面可位於同一水平、或第二積體電路晶片50的背側表面可高於第一積體電路晶片50的背側表面。
封裝體604可接著被完成，如第6F圖至第6H圖所示，且可以以如前所述的類似方式，例如關於第4D圖至第4H圖以及第5F圖至第5H圖。如第6G圖所示，第三積體電路晶片50可藉由類似於先前關於第2G、5B、5D、6B、6D圖所說明的製程和材料貼附至第一側重佈線結構106。此外，外部連接器610可形成，以提供隨後貼附其他積體電路裝置或封裝體的元件。如第6H圖所示，第四積體電路晶片50和額外裝置650可利用類似於先前關於第2G、4H、5B、5D、5G、5H、6B、6D圖所說明的製程和材料貼附至第二側重佈線結構206。前述佈置的優勢包括提供更薄的封裝體604。
如前所述，第一側重佈線結構106和第二側重佈線結構206分離一厚度T3 。在本實施例中，厚度T3 可為約50微米至約500微米。厚度T3 和厚度T1 的比值可為約0.4至約25。厚度T3 和厚度T2 的比值可為約0.0.至約10。此外，連接器226可具有約10微米至約300微米的高度HC 、或約150微米。因此，封裝體604中的貫通孔126和連接器226的總高度可為約100微米至約600微米、或約300微米(應注意的是總高度可小於高度HC 和高度HTV 的總合，因為回焊了連接器226)，所述總高度可大致相等於第一側重佈線結構106和第二側重佈線結構206之間的區域的厚度T3 。再如第6H圖所示，厚度T3 小於第一積體電路晶片50和第二積體電路晶片(分別為高度HIC1 和高度HIC2 )堆疊的總高度。換言之，第一和第二積體電路晶片50相對於彼此的橫向位移允許了更低的厚度T3 。在一些實施例中，第一側重佈線結構106和第二積體電路晶片50的背側表面之間的封裝膠310的厚度可為約30微米至約300微米，例如約150微米。此外，第二側重佈線結構206和第一積體電路晶片50之間的封裝膠310的厚度可為約30微米至約300微米，例如150微米。
實施例對用於積體電路的系統級封裝(SiP)結構可達成許多優點。舉例而言，雙邊佈線(例如第二側和第一側重佈線結構)允許佈線的各側更薄，且允許整體半導體封裝體更薄同時減少整體封裝體翹曲。此外，用在佈線結構之一的載體型基板提供較佳的結構支撐，其同樣減少整體封裝體翹曲。再者，描述的設計方法提供嵌埋的積體電路晶片和其他裝置的佈線的多樣性。當然，垂直堆疊的積體電路晶片可提供足夠的空間予額外裝置來貼附至第一側重佈線結構，反之橫向位移的積體電路晶片可允許整體更薄的封裝體結構。應注意的是，第一側重佈線結構可比第二側重佈線結構更寬，這允許了形成封裝膠包圍第二側重佈線結構，以加強封裝體且更減少整體封裝體翹曲。當然，描述的設計方法提供封裝膠以沒有沿著第二側重佈線結構的外表面成型蔓延的風險的方式應用。這可確保額外裝置可貼附至第二側重佈線結構的外表面，而不會受到微量(trace amounts)封裝膠的干擾。
在一實施例中，一半導體封裝體藉由將一第一元件貼附至一第二元件製造。第一元件藉由在一基板之上形成一第一重佈線結構裝配。一貫通孔接著形成在第一重佈線結構之上，且一晶片貼附至第一重佈線結構，主動側朝下。第二元件包括一第二重佈線結構，其接著貼附至貫通孔。一成型模料沉積在第一重佈線結構和第二重佈線結構之間，且更包圍第二元件的側邊。
在另一實施例中，一半導體封裝體藉由形成一第一元件、形成一第二封裝元件、以及貼附第二元件至第一元件製造。第一元件藉由在一基板之上形成一重佈線結構、在重佈線結構之上形成一貫通孔、以及將一晶片貼附至重佈線結構形成。第二元件藉由在另一基板之上形成另一重佈線結構、在此重佈線結構之上形成一連接器、以及將另一晶片貼附至此重佈線結構形成。第二元件藉由將其在貫通孔上翻轉且利用回焊連接器接合連接器至貫通孔來貼附。在貼附之後，基板從第二元件移除。
在又一實施例中，一半導體封裝體包括在一基板上的一第一重佈線結構、以及堆疊在第一重佈線結構的頂部的第二重佈線結構。第二重佈線結構包括一導電通孔。第一重佈線結構比第二重佈線結構更寬。一貫通孔將第一重佈線結構電性耦合至第二重佈線結構。一晶片貼附至第一重佈線結構，晶片的主動側面向且電性耦合至第一重佈線結構。另一晶片貼附至第二重佈線結構，此晶片的主動側面向且電性耦合至第二重佈線結構。一封裝膠填充於第一重佈線結構和第二重佈線結構之間的區域中。
本發明實施例提供一種半導體封裝體的形成方法，包括形成一第一元件，且形成該第一元件包括：在一第一基板之上形成一第一重佈線結構；在第一重佈線結構之上形成一貫通孔；將一第一晶片貼附至第一重佈線結構，第一晶片的主動側面向且電性耦合至第一重佈線結構。半導體封裝體的形成方法更包括將一第二元件貼附至貫通孔，第二元件包括貼附至一第二基板的一第二重佈線結構、以及在貼附第二元件之後，在第一重佈線結構和第二重佈線結構之間沉積一成型模料，成型模料之部分圍繞第二重佈線結構的側邊邊緣。
在一些實施例中，半導體封裝體的形成方法更包括在第二基板之上形成第二重佈線結構、將一第二晶片貼附至第二重佈線結構，第二晶片的主動側面向且電性耦合至第二重佈線結構、以及在第二重佈線結構之上沉積一焊球。在一些實施例中，將第二元件貼附的步驟包括回焊焊球以將貫通孔電性耦合至第二重佈線結構。在一些實施例中，將第二元件貼附的步驟包括貼附第二元件使得第二晶片直接位在第一晶片之上，第一晶片的背側面向第二晶片的背側。在一些實施例中，將第二元件貼附的步驟包括貼附第二元件使得第二晶片自第一晶片橫向位移，第一晶片的側邊面向第二晶片的側邊。在一些實施例中，形成第二重佈線結構的步驟包括在第一基板之上形成一第一金屬走線、在第一金屬走線之上沉積一ABF膜(Ajinomoto Build-up Film)、在ABF膜中雷射鑽孔一開口、在開口中形成一導電通孔、以及在導電通孔之上形成一第二金屬走線。在一些實施例中，半導體封裝體的形成方法更包括移除第二基板、以及在移除第二基板之後，將複數個被動裝置貼附至第二重佈線結構。
本發明實施例亦提供一種半導體封裝體，包括一第一元件、一第二元件、以及一封裝膠。第一元件包括一第一重佈線結構、一貫通孔、以及一第一晶片。貫通孔設置在第一重佈線結構之上。第一晶片貼附至第一重佈線結構，且第一晶片的主動側面向第一重佈線結構。第二元件包括一第二重佈線結構、一連接器、以及一第二晶片。連接器將貫通孔耦合至第二重佈線結構。第二晶片貼附至第二重佈線結構的一第一側，第二晶片的主動側面向第二重佈線結構。封裝膠設置在第一重佈線結構和第二重佈線結構之間。
在一些實施例中，封裝膠封裝第一晶片和第二晶片的側邊邊緣。在一些實施例中，封裝膠接觸第二重佈線結構的側邊邊緣。在一些實施例中，半導體封裝體更包括一鈍化層和一第三晶片。鈍化層設置在第二重佈線結構的一第二側之上，第二側相反於第一側。第三晶片設置於在第二重佈線結構之第二側上的鈍化層之上。在一些實施例中，從平面圖看，第二晶片的部分與第一晶片的部分重疊。在一些實施例中，第二晶片自第一晶片橫向地位移。在一些實施例中，半導體封裝體更包括一被動裝置，貼附至第二重佈線結構的第二側。
本發明實施例更提供一種半導體封裝體，包括一第一重佈線結構、一第二重佈線結構、一第一晶片、一第二晶片、一封裝膠、以及一貫通孔。第一重佈線結構具有一第一寬度。第二重佈線結構設置在第一重佈線結構之上，且包括從一第一金屬走線延伸至一第二金屬走線的一導電通孔。第一金屬走線沿著第二重佈線結構的一第一側設置，第二金屬走線沿著第二重佈線結構的一第二側設置。第二重佈線結構具有一第二寬度，且第一寬度大於第二寬度。第一晶片貼附至第一重佈線結構，第一晶片的一第一主動側面向且電性耦合至第一重佈線結構。第二晶片貼附至第二重佈線結構，第二晶片的一第二主動側面向且電性耦合至第二重佈線結構。封裝膠直接插入第一重佈線結構和第二重佈線結構之間。貫通孔延伸穿過封裝膠，貫通孔將第一重佈線結構電性耦合至第二重佈線結構。
在一些實施例中，封裝膠接觸第一晶片的整個側邊邊緣、第二晶片的整個側邊邊緣、以及第二重佈線結構的側邊邊緣的至少一部份。在一些實施例中，第一重佈線結構為一扇出型重佈線結構。在一些實施例中，導電通孔直接設置在貫通孔之上且電性耦合至貫通孔。在一些實施例中，第一晶片包括一第一背側，相反於第一主動側，第二晶片包括一第二背側，相反於第二主動側，且第二背側比第一背側更為接近第一重佈線結構。在一些實施例中，半導體封裝體更包括一被動裝置，貼附且電性耦合至第二重佈線結構相反於第一重佈線結構的一側。
以上概略說明了本揭露數個實施例的特徵，使所屬技術領域中具有通常知識者可更為清楚地理解本揭露的各面向。任何所屬技術領域中具有通常知識者應瞭解到本揭露可作為其它結構或製程的設計或變更基礎，以進行相同於本揭露實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構或製程並未脫離本揭露之精神和保護範圍內，且可在不脫離本揭露之精神和範圍內，當可作更動、替代與潤飾。
50:積體電路晶片/第一積體電路晶片/第二積體電路晶片/第三積體電路晶片/第四積體電路晶片 52:半導體基板 54:裝置 56:層間介電質 58:導電插塞 60:互連結構 62:襯墊 64:鈍化膜 66:晶片連接器 68:介電層 70:黏貼層 100:第一元件/第一封裝元件 102:第一承載基板 104:釋放層 106:第一側重佈線結構/背側重佈線結構 110:介電層 112:金屬化圖案 114:介電層 116:金屬化圖案 118:介電層 120:金屬化圖案 122:介電層 124:開口 126:貫通孔 128:接合墊 130:焊點 132:底部填充材料 200:第二元件/第二封裝元件/封裝元件 202:第二承載基板 204:第一金屬膜/金屬膜 206:第二側重佈線結構 208:光阻 210:第一金屬走線 212:介電層 214:通孔開口 216:線路開口 218:導電通孔 220:第二金屬走線 222:阻焊材料 224:開口 226:連接器 228:開口 310:封裝膠 320:鈍化層 400:封裝體 401:插圖 402:插圖 404:劃線區域 406:臨時基板 410:導電連接器 501:第一元件 502:第二元件 503:基板 504:封裝體 510:介電層 511:額外裝置 528:接合墊 530:焊料接點 532:底部填充材料 550:其他的半導體裝置/其他裝置/額外裝置 601:第一元件 602:第二元件 604:封裝體 610:外部連接器 628:接合墊 630:焊料接點 632:底部填充材料 650:其他的半導體裝置/額外裝置 HC :連接器的高度 HIC1 :積體電路晶片/第一積體電路晶片的高度 HIC2 :第二積體電路晶片的高度 HTV :貫通孔的高度 T1 :第一側重佈線結構的厚度 T2 :第二側重佈線結構的厚度 T3 :第一側重佈線結構和第二側重佈線結構之間的厚度 W1 :第一側重佈線結構的寬度 W2 :第二側重佈線結構的寬度 θ:角度
第1圖係表示依據一些實施例，一積體電路晶片的剖視圖。 第2A圖至第2G圖係表示依據一些實施例，形成封裝體元件之製程期間的中間步驟的剖視圖。 第3A圖至第3H圖係表示依據一些實施例，形成封裝體元件之製程期間的中間步驟的剖視圖。 第4A圖至第4H圖係表示依據一些實施例，形成封裝體元件之製程期間的中間步驟的剖視圖。 第5A圖至第5H圖係表示依據一些實施例，形成封裝體元件之製程期間的中間步驟的剖視圖。 第6A圖至第6H圖係表示依據一些實施例，形成封裝體元件之製程期間的中間步驟的剖視圖。
50:積體電路晶片/第一積體電路晶片/第二積體電路晶片/第三積體電路晶片/第四 積體電路晶片
100:第一元件/第一封裝元件
106:第一側重佈線結構/背側重佈線結構
200:第二元件/第二封裝元件/封裝元件
202:第二承載基板
206:第二側重佈線結構
310:封裝膠
400:封裝體
401:插圖
402:插圖
T1:第一側重佈線結構的厚度
T2:第二側重佈線結構的厚度
T3:第一側重佈線結構和第二側重佈線結構之間的厚度
θ:角度

Claims (20)

  1. 一種半導體封裝體的形成方法，該形成方法包括： 形成一第一元件，形成該第一元件包括： 在一第一基板之上形成一第一重佈線結構； 在該第一重佈線結構之上形成一貫通孔； 將一第一晶片貼附至該第一重佈線結構，該第一晶片的主動側面向且電性耦合至該第一重佈線結構； 將一第二元件貼附至該貫通孔，該第二元件包括貼附至一第二基板的一第二重佈線結構；以及 在貼附該第二元件之後，在該第一重佈線結構和該第二重佈線結構之間沉積一成型模料，該成型模料之部分圍繞該第二重佈線結構的側邊邊緣。
  2. 如請求項1之形成方法，更包括： 在該第二基板之上形成該第二重佈線結構； 將一第二晶片貼附至該第二重佈線結構，該第二晶片的主動側面向且電性耦合至該第二重佈線結構；以及 在該第二重佈線結構之上沉積一焊球。
  3. 如請求項2之形成方法，其中將該第二元件貼附的步驟包括回焊該焊球以將該貫通孔電性耦合至該第二重佈線結構。
  4. 如請求項2之形成方法，其中將該第二元件貼附的步驟包括貼附該第二元件使得該第二晶片直接位在該第一晶片之上，該第一晶片的背側面向該第二晶片的背側。
  5. 如請求項2之形成方法，其中將該第二元件貼附的步驟包括貼附該第二元件使得該第二晶片自該第一晶片橫向位移，該第一晶片的側邊面向該第二晶片的側邊。
  6. 如請求項2之形成方法，其中形成該第二重佈線結構的步驟包括： 在該第一基板之上形成一第一金屬走線； 在該第一金屬走線之上沉積一ABF膜(Ajinomoto Build-up Film)； 在該ABF膜中雷射鑽孔一開口； 在該開口中形成一導電通孔；以及 在該導電通孔之上形成一第二金屬走線。
  7. 如請求項1之形成方法，更包括： 移除該第二基板；以及 在移除該第二基板之後，將複數個被動裝置貼附至該第二重佈線結構。
  8. 一種半導體封裝體，包括： 一第一元件，包括： 一第一重佈線結構； 一貫通孔，設置在該第一重佈線結構之上；以及 一第一晶片，貼附至該第一重佈線結構，該第一晶片的主動側面向該第一重佈線結構； 一第二元件，包括： 一第二重佈線結構； 一連接器，該連接器將該貫通孔耦合至該第二重佈線結構；以及 一第二晶片，貼附至該第二重佈線結構的一第一側，該第二晶片的主動側面向該第二重佈線結構；以及 一封裝膠，設置在該第一重佈線結構和該第二重佈線結構之間。
  9. 如請求項8之半導體封裝體，其中該封裝膠封裝該第一晶片和該第二晶片的側邊邊緣。
  10. 如請求項9之半導體封裝體，其中該封裝膠接觸該第二重佈線結構的側邊邊緣。
  11. 如請求項8之半導體封裝體，更包括： 一鈍化層，設置在該第二重佈線結構的一第二側之上，該第二側相反於該第一側；以及 一第三晶片，設置於在該第二重佈線結構之該第二側上的該鈍化層之上。
  12. 如請求項8之半導體封裝體，其中從平面圖看，該第二晶片的部分與該第一晶片的部分重疊。
  13. 如請求項8之半導體封裝體，其中該第二晶片自該第一晶片橫向地位移。
  14. 如請求項8之半導體封裝體，更包括一被動裝置，貼附至該第二重佈線結構的該第二側。
  15. 一種半導體封裝體，包括： 一第一重佈線結構，該第一重佈線結構具有一第一寬度； 一第二重佈線結構，設置在該第一重佈線結構之上，該第二重佈線結構包括從一第一金屬走線延伸至一第二金屬走線的一導電通孔，該第一金屬走線沿著該第二重佈線結構的一第一側設置，該第二金屬走線沿著該第二重佈線結構的一第二側設置，該第二重佈線結構具有一第二寬度，該第一寬度大於該第二寬度； 一第一晶片，貼附至該第一重佈線結構，該第一晶片的一第一主動側面向且電性耦合至該第一重佈線結構； 一第二晶片，貼附至該第二重佈線結構，該第二晶片的一第二主動側面向且電性耦合至該第二重佈線結構； 一封裝膠，直接插入該第一重佈線結構和該第二重佈線結構之間；以及 一貫通孔，延伸穿過該封裝膠，該貫通孔將該第一重佈線結構電性耦合至該第二重佈線結構。
  16. 如請求項15之半導體封裝體，其中該封裝膠接觸該第一晶片的整個側邊邊緣、該第二晶片的整個側邊邊緣、以及該第二重佈線結構的側邊邊緣的至少一部份。
  17. 如請求項15之半導體封裝體，其中該第一重佈線結構為一扇出型重佈線結構。
  18. 如請求項15之半導體封裝體，其中該導電通孔直接設置在該貫通孔之上且電性耦合至該貫通孔。
  19. 如請求項15之半導體封裝體，其中該第一晶片包括一第一背側，相反於該第一主動側，其中該第二晶片包括一第二背側，相反於該第二主動側，且其中該第二背側比該第一背側更為接近該第一重佈線結構。
  20. 如請求項15之半導體封裝體，更包括一被動裝置，貼附且電性耦合至該第二重佈線結構相反於該第一重佈線結構的一側。
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