CN112397396A - 半导体封装体及其形成方法 - Google Patents

半导体封装体及其形成方法 Download PDF

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Publication number
CN112397396A
CN112397396A CN202010818768.5A CN202010818768A CN112397396A CN 112397396 A CN112397396 A CN 112397396A CN 202010818768 A CN202010818768 A CN 202010818768A CN 112397396 A CN112397396 A CN 112397396A
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China
Prior art keywords
redistribution structure
chip
integrated circuit
redistribution
forming
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CN202010818768.5A
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Inventor
庄博尧
蔡柏豪
林孟良
吴逸文
郑心圃
翁得期
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US16/811,465 external-priority patent/US11322447B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN112397396A publication Critical patent/CN112397396A/zh
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Abstract

一半导体封装体及其形成方法，其中半导体封装体通过将一第一元件贴附至一第二元件制造。第一元件通过在一基板之上形成一第一重布线结构装配。一贯通孔接着形成在第一重布线结构之上，且一芯片贴附至第一重布线结构，主动侧朝下。第二元件包括一第二重布线结构，其接着贴附至贯通孔。一成型模料沉积在第一重布线结构和第二重布线结构之间，且还包围第二元件的侧边。

Description

半导体封装体及其形成方法
技术领域
本发明实施例有关于一种半导体封装体。更具体地来说，本发明实施例有关于一种具有封装胶的半导体封装体。
背景技术
由于各种电子元件(例如晶体管、二极管、电阻、电容等)的集成密度不断改进，半导体产业经历快速成长。在大多数情况下，集成密度的改善已从最小特征大小的反复减少得到，该减少允许更多的元件可被整合至给定区域中。因为将电子装置缩小的需求的增长，已浮现对于较小且更有创意的半导体芯片封装技术的需求。这种封装系统的一范例为堆叠式封装层叠(Package-on-Package,PoP)技术。在堆叠式封装层叠装置中，顶部半导体封装体被堆叠在底部半导体封装体的顶部上，以提供高度集成化及元件密度。堆叠式封装层叠技术一般能够生产具有增强功能性且在印刷电路板(printed circuit board,PCB)上有小覆盖区(footprints)的半导体装置。
发明内容
本发明实施例提供一种半导体封装体的形成方法，包括形成一第一元件，且形成该第一元件包括：在一第一基板之上形成一第一重布线结构；在第一重布线结构之上形成一贯通孔；将一第一芯片贴附至第一重布线结构，第一芯片的主动侧面向且电性耦合至第一重布线结构。半导体封装体的形成方法还包括将一第二元件贴附至贯通孔，第二元件包括贴附至一第二基板的一第二重布线结构、以及在贴附第二元件之后，在第一重布线结构和第二重布线结构之间沉积一成型模料，成型模料的部分围绕第二重布线结构的侧边边缘。
本发明实施例亦提供一种半导体封装体，包括一第一元件、一第二元件、以及一封装胶。第一元件包括一第一重布线结构、一贯通孔、以及一第一芯片。贯通孔设置在第一重布线结构之上。第一芯片贴附至第一重布线结构，且第一芯片的主动侧面向第一重布线结构。第二元件包括一第二重布线结构、一连接器、以及一第二芯片。连接器将贯通孔耦合至第二重布线结构。第二芯片贴附至第二重布线结构的一第一侧，第二芯片的主动侧面向第二重布线结构。封装胶设置在第一重布线结构和第二重布线结构之间。
本发明实施例更提供一种半导体封装体，包括一第一重布线结构、一第二重布线结构、一第一芯片、一第二芯片、一封装胶、以及一贯通孔。第一重布线结构具有一第一宽度。第二重布线结构设置在第一重布线结构之上，且包括从一第一金属走线延伸至一第二金属走线的一导电通孔。第一金属走线沿着第二重布线结构的一第一侧设置，第二金属走线沿着第二重布线结构的一第二侧设置。第二重布线结构具有一第二宽度，且第一宽度大于第二宽度。第一芯片贴附至第一重布线结构，第一芯片的一第一主动侧面向且电性耦合至第一重布线结构。第二芯片贴附至第二重布线结构，第二芯片的一第二主动侧面向且电性耦合至第二重布线结构。封装胶直接插入第一重布线结构和第二重布线结构之间。贯通孔延伸穿过封装胶，贯通孔将第一重布线结构电性耦合至第二重布线结构。
附图说明
图1是表示依据一些实施例，一集成电路芯片的剖视图。
图2A至图2G是表示依据一些实施例，形成封装体元件的工艺期间的中间步骤的剖视图。
图3A至图3H是表示依据一些实施例，形成封装体元件的工艺期间的中间步骤的剖视图。
图4A至图4H是表示依据一些实施例，形成封装体元件的工艺期间的中间步骤的剖视图。
图5A至图5H是表示依据一些实施例，形成封装体元件的工艺期间的中间步骤的剖视图。
图6A至图6H是表示依据一些实施例，形成封装体元件的工艺期间的中间步骤的剖视图。
附图标记说明：
50：集成电路芯片/第一集成电路芯片/第二集成电路芯片/第三集成电路芯片/第四集成电路芯片
52：半导体基板
54：装置
56：层间介电质
58：导电插塞
60：互连结构
62：衬垫
64：钝化膜
66：芯片连接器
68：介电层
70：粘贴层
100：第一元件/第一封装元件
102：第一承载基板
104：释放层
106：第一侧重布线结构/背侧重布线结构
110：介电层
112：金属化图案
114：介电层
116：金属化图案
118：介电层
120：金属化图案
122：介电层
124：开口
126：贯通孔
128：接合垫
130：焊点
132：底部填充材料
200：第二元件/第二封装元件/封装元件
202：第二承载基板
204：第一金属膜/金属膜
206：第二侧重布线结构
208：光刻胶
210：第一金属走线
212：介电层
214：通孔开口
216：线路开口
218：导电通孔
220：第二金属走线
222：阻焊材料
224：开口
226：连接器
228：开口
310：封装胶
320：钝化层
400：封装体
401：插图
402：插图
404：划线区域
406：临时基板
410：导电连接器
501：第一元件
502：第二元件
503：基板
504：封装体
510：介电层
511：额外装置
528：接合垫
530：焊料接点
532：底部填充材料
550：其他的半导体装置/其他装置/额外装置
601：第一元件
602：第二元件
604：封装体
610：外部连接器
628：接合垫
630：焊料接点
632：底部填充材料
650：其他的半导体装置/额外装置
HC：连接器的高度
HIC1：集成电路芯片/第一集成电路芯片的高度
HIC2：第二集成电路芯片的高度
HTV：贯通孔的高度
T1：第一侧重布线结构的厚度
T2：第二侧重布线结构的厚度
T3：第一侧重布线结构和第二侧重布线结构之间的厚度
W1：第一侧重布线结构的宽度
W2：第二侧重布线结构的宽度
θ：角度
具体实施方式
以下的公开内容提供许多不同的实施例或范例以实施本公开的不同特征。以下的公开内容叙述各个构件及其排列方式的特定范例，以简化说明。当然，这些特定的范例并非用以限定。例如，若是本公开书叙述了一第一特征形成于一第二特征之上或上方，即表示其可能包含上述第一特征与上述第二特征是直接接触的实施例，亦可能包含了有附加特征形成于上述第一特征与上述第二特征之间，而使上述第一特征与第二特征可能未直接接触的实施例。另外，以下公开书不同范例可能重复使用相同的参考符号及/或标记。这些重复是为了简化与清晰的目的，并非用以限定所描述的不同实施例及/或结构之间有特定的关系。
再者，为了方便描述附图中一元件或特征与另一(多个)元件或(多个)特征的关系，可使用空间相关用语，例如“下面”、“下方”、“之下”、“上方”、“之上”及类似的用语等。除了附图所示出的方位之外，空间相关用语涵盖装置在使用或操作中的不同方位。所述装置也可被另外定位(旋转90度或在其他方位上)，且同样可对应地解读于此所使用的空间相关描述。
根据一些实施例，一或多个集成电路芯片或其他装置会贴附于多个双边重布线结构(dual-sided redistribution structures)且嵌埋在封装物中，以形成一半导体系统级封装(system-in-package,SiP)结构。所述重布线结构的一可具有扇出型(fan-out)设计，且其他的再分布结构可形成为载体型基板(carrier-type substrate)。集成电路芯片的放置和重布线结构的布置在整个封装中提供了多样性。此外，封装和重布线结构的设计、以及设计方法(methodology)使得较薄的系统级封装结构具有较好的强度和减量的整体封装翘曲。
图1是表示根据一些实施例，一集成电路芯片50的剖视图。集成电路芯片50将在随后的工艺封装以形成一集成电路封装体。集成电路芯片50可为一逻辑芯片(例如中央处理器(central processing unit,CPU)、图形处理器(graphics processing unit,GPU)、单芯片系统(system-on-a-chip,SoC)、应用处理器(application processor,AP)、微控制器(microcontroller)等)、一存储芯片(例如动态随机存取存储器(dynamic random accessmemory,DRAM)芯片、静态随机存取存储器(static random access memory,SRAM)芯片等)、一电源管理芯片(例如电源管理集成电路(power management integrated circuit,PMIC)芯片)、一射频(radio frequency,RF)芯片、一感应器芯片、一微机电系统(micro-electro-mechanical-system,MEMS)芯片、一信号处理芯片(例如数字信号处理(digital signalprocessing,DSP)芯片)、一前端芯片(例如模拟前端(analog front-end,AFE)芯片)、类似物、或其组合。
集成电路芯片50可形成在一晶圆中，所述晶圆可包括在后续步骤中单体化(singulated)的多个相异装置区域，以形成多个集成电路芯片。集成电路芯片50可根据适用的制造工艺处理以形成晶体电路。举例而言，集成电路芯片50包括一半导体基板52，例如硅、掺杂或无掺杂、或绝缘层上硅晶(semiconductor-on-insulator,SOI)基板的主动层。半导体基板52可包括其他半导体材料，例如锗、化合物半导体(包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟)、合金半导体(包括硅化锗(SiGe)、磷化砷镓(GaAsP)、砷化铟铝(AlInAs)、砷化铝镓(AlGaAs)、砷化铟镓(GaInAs)、磷化铟镓(GaInP)、及/或砷磷化铟镓(GaInAsP))、或其组合。例如多层或梯度(gradient)基板的其他基板亦可被使用。半导体基板52具有一主动表面(例如图1中面朝上的表面)和一非主动表面(例如图1中面朝下的表面)，主动表面有时被称作一前侧，且非主动表面有时被称作一背侧。
多个装置(一个显示于图1中)54可形成在半导体基板52的前表面。装置54可为主动装置(例如晶体管(transistors)、二极管(diodes)等)、电容、电阻等。一层间介电质(inter-layer dielectric,ILD)56在半导体基板52的前表面之上。层间介电质56围绕装置54且可覆盖装置54。层间介电质56可包括一或多个介电层，形成所述介电层的材料例如磷硅酸盐玻璃(Phospho-Silicate Glass,PSG)、硼硅酸盐玻璃(Boro-Silicate Glass,BSG)、硼磷硅酸盐玻璃(Boron-Doped Phospho-Silicate Glass,BPSG)、无掺杂硅玻璃(undopedSilicate Glass,USG)、或类似物。
导电插塞58延伸穿过层间介电质56且与装置54物理地耦合。举例而言，当装置54为晶体管时，导电插塞58可与晶体管的栅极和源极/漏极区域耦合。导电插塞58可由钨、钴、镍、铜、银、金、铝、类似物、或其组合形成。互连结构60在层间介电质56和导电插塞58之上。互连结构60和装置54互连以形成一集成电路。举例而言，互连结构60可由层间介电质56的介电层中的金属化图案形成。金属化图案包括由一或多个低介电系数(low-k)介电层形成的金属线路和导通孔。互连结构60的金属化图案通过导电插塞58电耦合至装置54。
集成电路芯片50还包括多个衬垫62以建立外部连接，例如铝衬垫。衬垫62位于集成电路芯片50的主动侧，例如在互连结构60之中及/或之上。一或多个钝化膜64位在集成电路芯片50上，例如位在互连结构60和衬垫62的部分上。开口延伸穿过钝化膜64至衬垫62。芯片连接器66延伸穿过钝化膜64中的开口，并物理地且电性地耦合至各个衬垫62。前述芯片连接器66例如为导电柱(举例而言，由像是铜的金属形成)。在一些实施例中，芯片连接器66包括凸块下金属化(under-bump metallization,UBM)结构。虽然图1中仅表示了四个芯片连接器66，但可能还有更多，将在集成电路芯片50的之后的绘图中表示。举例而言，芯片连接器66(例如铜柱)可由电镀或类似方式形成。芯片连接器66电性地耦合集成电路芯片50的各个集成电路。
选择性地，焊料区域(例如焊球或焊料凸块，未图示)可设置在衬垫62及/或芯片连接器66上。焊料区域可用来在集成电路芯片50上施行裸晶针测(chip probe,CP)试验。裸晶针测试验可在集成电路芯片50上施行以确认集成电路芯片50是否是为良裸晶粒(knowngood die,KGD)。因此，只有是良裸晶粒的集成电路芯片50会接受之后的工艺而封装，在裸晶针测试验不合格的集成电路芯片50则不会封装。在试验之后，焊料区域可在之后的工艺步骤移除。
一介电层68可(或可不)设在集成电路芯片50的主动侧，例如在钝化膜64和芯片连接器66上。介电层68横向地封装芯片连接器66，且介电层68在单体化后与集成电路芯片50横向地相接。最初，介电层68可埋藏芯片连接器66，从而介电层68的最顶端表面会在芯片连接器66的最顶端表面之上。在焊料区域设置在芯片连接器66上的一些实施例中，介电层同样可埋藏焊料区域。或者，焊料区域可在形成介电层68之前被移除。
介电层68可为聚合物(例如PBO、聚酰亚胺、BCB、或类似物)、氮化物(例如氮化硅或类似物)、氧化物(例如氧化硅、PSG、BSG、BPSG、或类似物)、类似物、或其组合。举例而言，介电层68可通过旋转涂布、层压、化学气相沉积(chemical vapor deposition,CVD)、或类似方式形成。在一些实施例中，芯片连接器66在形成集成电路芯片50的期间通过介电层68暴露。在一些实施例中，芯片连接器66保持埋藏且在之后封装集成电路芯片50的工艺期间暴露。暴露芯片连接器66可移除任何存在在芯片连接器66上的焊料区域。
一粘贴层70可在工艺中的某些时点施加在集成电路芯片50的背侧。在一些实施例中，粘贴层是在将集成电路芯片贴附至一半导体封装元件(将在以下详述)之前形成在集成电路芯片50的背侧之上。
在一些实施例中，集成电路芯片50为包括多个半导体基板52的叠层装置。举例而言，集成电路芯片50可为存储器装置，例如混合存储器立方体(hybrid memory cube,HMC)模块、高频宽存储器(high bandwidth memory,HBM)模块、或包括多个存储器芯片的类似物。在这些实施例中，集成电路芯片50包括多个通过基板穿孔技术(through-substratevias,TSVs)互连的半导体基板52。每个半导体基板52可(或可不)具有一互连结构60。
以下将描述根据一些实施例，包含集成电路芯片50的半导体封装体的形成。图2A至图2G描述了根据一些实施例，一第一元件的形成中的各种中间步骤。如将要讨论的，第一元件可包括具有集成电路芯片50贴附的一扇出型重布线结构。图3A至图3H描述了根据一些实施例，一第二元件的形成，其中第二元件可贴附至参考图2A至图2G描述的第一元件。如将要讨论的，第二元件可包括一基板型重布线结构。虽然未特别描述，第二元件亦可包括一扇出型重布线结构，且此扇出型重布线结构与第一元件的扇出型重布线结构类似。图4A至图4H描述了根据一些实施例，将第二元件贴附至第一元件，以及更进一步的工艺以形成一半导体封装体。
首先请参阅图2A，在一第一元件100的形成中，一第一承载基板102被提供，且一释放层104形成在第一承载基板102上。第一承载基板102可为玻璃承载基板、陶瓷承载基板、或类似物。第一承载基板102可为晶圆，从而多个封装体可同时形成在第一承载基板102上，其中每个封装体可包含一或多个芯片。释放层104可由一聚合物基材料(polymer-basedmaterial)形成，其可以与第一承载基板102一同从上覆结构移除，所述上覆结构是在之后的步骤中形成。在一些实施例中，释放层104为环氧基材料(epoxy-based material)，其会在加热时失去自身的粘着性，例如光热转换(light-to-heat-conversion,LTHC)防粘涂料。在一些实施例中，释放层104可为紫外光(ultraviolet,UV)胶，其会在暴露于紫外光光线时失去自身的粘着性。释放层104可以液体形式分配且固化，可以为层压在第一承载基板102上的层压膜，或者可以为类似物。
在图2B至图2E中，一第一侧重布线结构106可形成在释放层104上。在所示的实施例中，第一侧重布线结构106包括一或多个介电层和金属化图案(有时称作重布线层或重布线线路)。第一侧重布线结构106将被描述为具有三层金属化图案。更多或更少的介电层和金属化图案亦可形成在第一侧重布线结构106中。若更少的介电层和金属化图案要被形成，以下讨论的步骤和工艺可被省略。若更多的介电层和金属化图案要被形成，以下讨论的步骤和工艺可被重复。
现请参阅图2B，一介电层110形成在释放层104上。介电层110的底面可接触释放层104的顶面。在一些实施例中，介电层110可由感光材料(photo-sensitive material)形成，例如聚苯并恶唑(polybenzoxazole,PBO)、聚酰亚胺、苯并环丁烯(benzocyclobutene,BCB)、或类似物，其可利用微影遮罩来图案化。在一些实施例中，介电层110由氮化物形成，例如氮化硅、磷硅酸盐玻璃(phosphosilicate glass,PSG)、硼硅酸盐玻璃(borosilicateglass,BSG)、硼磷硅酸盐玻璃(boron-doped phosphosilicate glass,BPSG)、或类似物。介电层110可通过旋转涂布、层压、化学气相沉积、类似方式、或其组合形成。介电层110被图案化，以形成使释放层104的部分暴露的开口。图案化可通过可接受的工艺，例如通过将介电层110暴露至光线、显影、以及在介电层110是感光材料时固化，或是通过蚀刻，举例而言，使用各向异性蚀刻。
金属化图案112接着形成在介电层110上。金属化图案112包括线路部分(亦被称为导线)，位于介电层110的主要表面上且沿着介电层110的主要表面延伸。金属化图案112还包括导通孔部分(亦被称为导电通孔)，延伸穿过介电层110以使第一侧重布线结构106与外部连接器物理地且电性地耦合，所述外部连接器可在之后的步骤中形成。作为形成金属化图案112的一个范例，一晶种层(seed layer)形成在介电层110之上、以及在延伸穿过介电层110的开口中。在一些实施例中，晶种层为一金属层，其可为单层或包括多个由不同材料形成的子层的复合层。在一些实施例中，晶种层包括一钛层和一铜层，铜层位在钛层之上。举例而言，晶种层可利用物理气相沉积(physical vapor deposition,PVD)或类似方式形成。一光刻胶接着形成且图案化于晶种层上。光刻胶可通过旋转涂布或类似方式形成，且可暴露至光线以图案化。光刻胶的图案对应于金属化图案112。图案化将形成穿过光刻胶的开口，以暴露晶种层。一导电材料接着形成在光刻胶的开口中、以及在晶种层的暴露部分上。导电材料可通过电镀(例如有电电镀(electroplating)或无电电镀(electrolessplating))或类似方式形成。导电材料可包括金属，像是铜、钛、钨、铝、或类似物。光刻胶和晶种层上没有形成导电材料的部分将被移除。光刻胶可通过可接受的灰化(ashing)或剥除(stripping)工艺移除，例如利用氧等离子体(oxygen plasma)或类似物。一旦光刻胶被移除，晶种层的暴露部分将被移除，例如通过使用可接受的蚀刻工艺，像是通过湿式蚀刻或干式蚀刻。导电材料的保留部分和晶种层的底层部分形成金属化图案112。
在图2C中，一介电层114沉积在金属化图案112和介电层110上。介电层114可以以与介电层110类似的方式形成和图案化。
接着形成金属化图案116。金属化线路116包括线路部分，位于介电层114的主要表面上且沿着介电层114的主要表面延伸。金属化图案116还包括导通孔部分，延伸穿过介电层114以物理地且电性地耦合金属化图案112。金属化图案116可以以与金属化图案112类似的方式和类似的材料形成。在一些实施例中，金属化图案116具有与金属化图案112不同的尺寸。举例而言，金属化图案112的导线及/或导通孔可较宽或较厚于金属化图案116的导线及/或导通孔。再者，金属化图案112可形成为跟金属化图案116相比具有更大的间距。
在图2D中，一介电层118沉积在金属化图案116和介电层114上。介电层118可以以与介电层110及/或介电层114类似的方式形成和图案化。
接着形成金属化图案120。金属化图案120包括线路部分，位于介电层118的主要表面上且沿着介电层118的主要表面延伸。金属化图案120还包括导通孔部分，延伸穿过介电层118以物理地且电性地耦合金属化图案116。金属化图案120可以以与金属化图案112及/或金属化图案116类似的方式和类似的材料形成。
在图2E中，一介电层122沉积在金属化图案120和介电层118上。介电层122可以以与介电层110类似的方式形成和图案化，以形成开口124。
介电层110和金属化图案112分别为第一侧重布线结构106最底部的介电层和金属化图案。因此，第一侧重布线结构106的所有中间的介电层和金属化图案(例如介电层114、118、122，以及金属化图案116、120)会设置在介电层110/金属化图案112和随后要形成或贴附在第一侧重布线结构106之上的元件之间。在一些实施例中，金属化图案112具有与金属化图案116、120不同的尺寸。举例而言，金属化图案112的导线可具有约0.5微米至约15微米的厚度、或约5微米的厚度，且金属化图案116和120的导线可具有约0.5微米至约15微米的厚度、或约5微米的厚度。金属化图案112的厚度和金属化图案120的厚度的比值可为约0.3至约3、或约1。再者，金属化图案112可形成为跟金属化图案116、120相比具有更大的间距。举例而言，金属化图案112的导线可具有约1微米至约100微米的间距、或约10微米的间距，且金属化线路116和120的导线可具有约1微米至约100微米的间距、或约10微米的间距。金属化图案112的间距和金属化图案120的间距的比值可为约0.1至约10、或约1。应注意的是，第一侧重布线结构106可包括任何数量的介电层和金属化图案。若更多的介电层和金属化图案要被形成，前述步骤和工艺可被重复。
在图2F中，贯通孔(through vias)126形成在一些开口124中，且往远离第一侧重布线结构106的最顶部的介电层(例如介电层122)的方向延伸。作为形成贯通孔126的一个范例，一晶种层(未图示)形成在第一侧重布线结构106之上，例如在介电层122和金属化图案120通过开口暴露的部分上。在一些实施例中，晶种层为一金属层，其可为单层或包括多个由不同材料形成的子层的复合层。在一些实施例中，晶种层包括一钛层和一铜层，铜层位在钛层之上。在一些实施例中，晶种层由铜、钛、镍、金、钯、类似物、或其组合制成。举例而言，晶种层可利用物理气相沉积(physical vapor deposition,PVD)或类似方式形成。一遮罩(例如一光刻胶(未图示))形成且图案化于晶种层上。光刻胶可通过旋转涂布或类似方式形成，且可暴露至光线以图案化。光刻胶的图案对应于贯通孔126且暴露晶种层。一导电材料接着形成在光刻胶的开口中、以及在晶种层的暴露部分上。导电材料可通过电镀(例如电化学电镀工艺(electro-chemical plating process)或无电电镀(electrolessplating))、化学气相沉积、原子层沉积(atomic layer deposition,ALD)、物理气相沉积、类似方式、或其组合形成。导电材料可包括金属，像是铜、钛、钨、铝、或类似物。光刻胶可被移除。
请继续参阅图2F，接合垫128形成在一些开口124中，且往远离介电层122的方向延伸。接合垫128可以以与贯通孔126类似的方式形成，且可由与贯通孔126相同的材料形成。此外，接合垫128可在贯通孔126之前、之后、或同时形成。
用于接合垫128和贯通孔126的光刻胶以及晶种层上未形成接合垫128和贯通孔126的部分将被移除。光刻胶可通过可接受的灰化或剥除工艺移除，例如利用氧等离子体或类似物。一旦光刻胶被移除，晶种层的暴露部分将被移除，例如通过使用可接受的蚀刻工艺，像是通过湿式蚀刻或干式蚀刻。晶种层和导电材料的保留部分形成接合垫128和贯通孔126。
如前所述，一集成电路芯片(例如参考图1前述的集成电路芯片50)可贴附至接合垫128。在一些实施例中，接合垫128为凸块下金属化结构(UBMs)，举例而言，其可包括三层导电材料，像是一层钛、一层铜、以及一层镍。其他材料和层的配置亦可被利用来形成接合垫128，例如铬/铬-铜合金/铜/金的配置、钛/钨化钛/铜的配置、或铜/镍/金的配置。可使用于接合垫128的任何适合的材料和材料层完全包含于本发明实施例的范围中。
在图2G中，一或多个半导体装置(例如第一集成电路芯片50)将贴附至接合垫128，以建立与第一侧重布线结构106的电性连接。举例而言，第一集成电路芯片50可通过在芯片连接器66(无论是导电柱或是凸块下金属化结构)上形成焊点130、将芯片连接器66压至接合垫128、以及回焊焊点130以将第一集成电路芯片50贴合至第一侧重布线结构106来贴合。在一些实施例中，第一集成电路芯片50可利用直接金属-金属键合(direct metal-to-metal bonding)或混合键合(hybrid bonding)来贴附。图2G描绘了集成电路芯片50为具有比贯通孔126更高的高度。然而，应注意的是，贯通孔126可具有与集成电路芯片50大约相等的高度或比集成电路芯片50更高的高度。举例而言，贯通孔126可具有约10微米至约200微米的高度HTV，且集成电路芯片50可具有约30微米至约250微米的高度HIC1。高度HTV和高度HIC1的比值可为约0.04至约8。
应注意的是，对于集成电路芯片50而言，第一侧重布线结构106可为一扇出型重布线结构。因此，金属化图案(例如金属化图案112、116、120)在横向方向上可比集成电路芯片50更为延伸。扇出型设计允许了更薄的重布线结构，且亦可容置更多的外部连接器，所述外部连接器可因而在横向方向上比集成电路芯片50更为延伸。第一侧重布线结构106形成为具有厚度T1，此厚度T1可为约20微米至100微米。
一底部填充材料(underfill material)132可分配在第一集成电路芯片50和第一侧重布线装置106之间。底部填充材料132围绕焊点130和接合垫128。底部填充材料132可为任何可接受的材料，例如聚合物、环氧树脂、模制底胶(molding underfill)、或类似物。底部填充材料132可利用针头或喷射分配器分配、利用毛细管流工艺分配、或利用其他适合的工艺分配。在一些实施例中，一固化工艺可被执行，以固化底部填充材料132。虽然未明确地显示于图2G中，底部填充材料132可沿着第一集成电路芯片50的侧壁延伸。
为了说明的目的，图2G是表示贴附至接合垫128的单一集成电路芯片50。在一些实施例中，两个或多个集成电路芯片50(每个集成电路芯片50具有相同或不同的功能)可贴附至接合垫128。
图3A至图3H是表示根据一些实施例，形成一第二元件200的工艺期间的中间步骤的剖视图。如前所述，第二元件200可接着贴附至关于图2A-图2G所述的第一元件100上。第二元件200可形成为个别的封装体或可由晶圆级(wafer-level)工艺形成。只有一个个别的封装元件200被表示，但应注意的是第二元件200可为晶圆的一部分。在形成后，个别的第二元件200将单体化。最终的第二元件200亦可被称作一集成封装体(integrated package)。
在图3A中，一第二承载基板202被提供，且一第二侧重布线结构可形成在第二承载基板202上。第二承载基板202可为玻璃承载基板、陶瓷承载基板、或类似物。第二承载基板202可为晶圆，从而多个封装体可同时形成在第二承载基板202上。一第一金属膜204形成在第二承载基板202上。第一金属膜204可包括铜，像是一铜箔(copper foil)。第二承载基板202可具有约10微米至约400微米的厚度、或约200微米的厚度。第一金属膜204可具有约1微米至约20微米的厚度、或约3微米的厚度。第一金属膜204可包括铜或其他导电材料。
在图3B中，一光刻胶208接着在第一金属膜204上形成和图案化。光刻胶208可通过旋转涂布或类似方式形成，且可暴露至光线以图案化。图案化将形成穿过光刻胶208的开口，以暴露第一金属膜204。
在图3C中，一第二侧重布线结构206形成在第一金属膜204之上。首先，一第一金属走线210形成在第一金属膜204之上，且光刻胶208被移除。第一金属走线210可通过有电电镀形成且可包括一或多层导电材料。举例而言，一层金(Au)可首先沉积，一层镍(Ni)其次，且一层铜(Cu)在最后。金可沉积为厚度大于或大约0.1微米，例如约0.01微米至约3微米。镍可沉积为厚度大于或大约3微米，例如约0.1微米至约10微米。铜可沉积为厚度大于或大约7微米，例如约1微米至约25微米。因此，第一金属走线210可具有厚度大于或大约1微米至35微米，例如大于或大约10微米。像是这样的厚度有益于将第一金属走线210粘贴至第一金属膜204、保持内部凝聚力(internal cohesiveness)、及/或提供充足的导电性能。少于此的厚度可能会造成较差的粘着性、凝聚力、及/或导电性。光刻胶208可通过任何适合的剥除方法移除。
在图3D中，一介电层212形成在第一金属走线210之上。介电层212可通过一热层压工艺(thermal lamination process)形成。介电层212可包括预浸料(prepreg)或ABF膜(Ajinomoto Build-up Film)。在一些实施例中，介电层212可为具有约10微米至约100微米的厚度的预浸料，例如约30微米，或可为具有约10微米至约100微米的厚度的ABF膜，例如约20微米。使用预浸料或ABF膜材料作为介电层212的好处为第二侧重布线结构206将具有高等级的强度和可靠度。当之后与第一侧重布线结构106耦合时，整个半导体封装体将不易翘曲。
在图3E中，介电层212被图案化以形成暴露第一金属走线210的部分的开口。开口包括通孔开口(via openings)214，延伸穿过介电层212以暴露第一金属走线210的部分。开口还包括线路开口(line openings)216，连接通孔开口214且提供布线可能性(routingcapabilities)。介电层212可利用单一镶嵌(damascene)或双镶嵌工艺图案化。图案化可通过任何适合的方法执行，例如形成一光刻胶并湿式蚀刻或干式蚀刻介电层212及/或使用一激光剥蚀(laser ablation)(或激光钻孔(laser drilling))技术。虽然描绘为垂直侧壁，应注意的是，激光钻孔技术可产生具有非垂直侧壁的通孔开口214。通孔开口214可具有约30微米至约150微米的宽度，例如约65微米。
在图3F中，在介电层212上方区域的通孔开口214和线路开口216将填充一导电材料，以形成导电通孔218(在通孔开口214中)和第二金属走线220(在线路开口216中)。导电材料可通过有电电镀或无电电镀、或任何适合的方法沉积。第二金属走线220可具有约10微米的厚度。或者，导电通孔218可在介电层212被图案化以形成第二金属走线220之前在最初形成。
第二侧重布线结构206(包括第一金属走线210、导电通孔218、以及第二金属走线220)形成为具有厚度T2，此厚度T2可为约20微米至约150微米。第二侧重布线结构206的厚度可大于或相等于背侧重布线结构106的厚度T1。厚度T2和厚度T1的比值可为约0.3至约3。比值在此范围内提供了合适的刚性以避免或减少因为不同的热膨胀系数(coefficient ofthermal expansions,CTEs)而产生的翘曲，举例而言，当第二元件200接着贴附至第一元件100时，第一侧重布线结构106的介电层和金属化图案以及包括集成电路芯片50的材料的不同热膨胀系数。比值小于此数值可能无法提供充足的刚性予第二元件200以抗衡第一元件100的元件膨胀。比值大于此数值可能会增加信号长度，从而减少了封装装置的性能。
在图3G中，阻焊材料222形成且图案化以形成暴露导电通孔218及/或第二金属走线220的开口224。此外，为了保护的目的，导电通孔218和第二金属走线220的暴露部分可被处理。举例而言，化镍钯金(eletroless nickel electroless palladium immersionglod,ENEPIG)处理或有机保焊剂(organic solderability preservative,OSP)可于导电通孔218和第二金属走线220的暴露部分实施。阻焊材料可具有约5微米至约40微米的厚度，例如约10微米。阻焊材料222亦可用来保护第二侧重布线结构206的保护区域不受外部损害。
在图3H中，连接器226形成在导电通孔218和第二金属走线220的暴露部分之上。连接器226可为焊球，以类似于第一集成电路芯片50上的焊料区域的方法形成，且可以以类似于第一集成电路芯片50上的焊料区域的材料形成。
就晶圆级工艺以形成第二元件200而言，一单体化工艺可通过沿着相邻第二元件200的划线区域(切割道)锯切来执行。如以下所说明的，生成的单体化的第二元件200耦合至第一元件100。在一些实施例中，在第二元件200贴附之前，第一元件100也类似地单体化。在一些实施例中，第一元件100在贴附至第二元件200后单体化。
图4A至图4H是表示根据一些实施例，贴附第二元件200至第一元件100的中间步骤的剖视图，以及额外工艺，以形成一封装体400。
首先请参阅图4A，封装体400被表示，其中第一元件100为晶圆的一部分。在一些实施例中(但未表示于图4A中)，第一元件100在划线区域404已经单体化。
每个单体化的第二元件200利用连接器226安装至第一元件100。如前所述，第一元件100包括用来贴附的贯通孔126。因此，连接器226结合至对应的贯通孔126。在一些实施例中，连接器226被回焊以将第二元件200贴附至贯通孔126。连接器226将第二元件200电性耦合至第一封装元件100的第一侧重布线结构106。连接器226可具有形成于其上的环氧树脂助焊剂(epoxy flux，未图示)，因为在第二元件200贴附至第一元件100之后，其会与余留的环氧树脂助焊剂的环氧树脂部分的至少一些回焊。此余留的环氧树脂部分可充当底部填充体，以减少应力且保护回焊连接器226产生的接点。在第二元件200贴附至第一元件100之后，第一侧重布线结构106和第二侧重布线结构206可彼此分离一厚度T3。厚度T3可为约50微米至约500微米。厚度T3和厚度T1的比值可为约0.4至约5。厚度T3和厚度T2的比值可为约0.3至约4。
在图4B中，一封装胶(encapsulant)310形成在第一元件100之上且包围第二元件200。封装胶310更封装贯通孔126、第一集成电路芯片50、以及贴附至第一元件100及/或第二元件200的任何其他装置(若有)。封装胶310更形成在相邻第二元件200的间隙区域中。封装胶310可在第二封装元件200贴附之后通过一毛细管流工艺形成、或在第二封装元件200贴附之前通过一适合的沉积方法形成。在一些实施例中，封装胶310可通过压缩成型(compression molding)、转注成型(transfer molding)、或类似方法施加。封装胶310可以液体或半液体(semi-liquid)形式被施加，且接着随后固化。封装胶310可为成型模料(molding compound)、环氧树脂、或类似物。
如图4B中的插图401、402所表示，封装胶310可形成为包围第二元件200的第二侧重布线结构206的侧边边缘。封装胶310可部分地或完全地覆盖第二元件200的侧边边缘。举例而言，如插图401所描绘，封装胶310可具有凹陷的上表面，其最高点位于接近的二元件200的侧边边缘。封装胶310可部分地或完全地覆盖的二侧重布线结构206的侧边边缘。在一些实施例中，封装胶310还可覆盖第二承载基板202的侧边边缘的部分。此外，上表面的最低点可低于第二侧重布线结构206最接近第二承载基板202的部分。如插图402所描绘，封装胶310可形成来覆盖的二侧重布线结构206的所有侧边边缘，以及第二承载基板202的所有或部分侧边边缘。在一些实施例中，封装胶310可覆盖第二承载基板202的全部的侧边边缘，甚至是第二承载基板202的上表面的部分(未特别绘出)。
封装胶310提供了第二侧重布线结构206额外的支持，这使得整体封装体400更强固、还可靠、且更不易翘曲。如前所述，增加的强度和坚固性是由封装胶310的上部分粘贴至第二元件200的侧边边缘而来。封装胶310可朝远离第二元件200的侧边边缘的方向向下倾斜，如图4B的插图401所描绘。倾斜可与水平线成一角度θ。所述角度θ可为约0度至约45度、或约45度至约60度。
在图4C中，根据一些实施例，第二承载基板202从封装体400移除，暴露第二侧重布线结构206。第二承载基板202可利用例如一热处理来改变设置在第二承载基板202上的释放层的粘着性，以从第二侧重布线结构206拆卸(demounted)、脱胶(debonded)、或机械地剥离(peeled off)。在一些实施例中，一能量源被利用来照射及加热释放层直到释放层失去至少一些自身的粘着性，所述能量源例如为一紫外线(ultraviolet,UV)激光、一二氧化碳(carbon dioxide,CO2)激光、或一红外线(infrared,IR)激光。一旦执行后，第二承载基板202和金属膜204可物理地分离且从第二侧重布线结构206移除。在一些实施例中，一平坦化工艺或一机械剥离工艺可被执行，以移除第二承载基板202来暴露第二侧重布线结构206。平坦化结构亦可移除一些可能形成在第二侧重布线结构206的上层之上的封装胶310。举例而言，平坦化结构可为化学机械抛光(chemical-mechanical polish,CMP)、研磨工艺、或类似方式。需特别说明的是，即便在本实施例中封装胶310形成为完全覆盖第二元件的侧边边缘(且或许在第二承载基板202的上表面之上(例如大体描绘在图4B的插图402中))，因为第二承载基板202的保护，封装体400仍不易在第二侧重布线结构206的上表面上成型蔓延(creep)封装胶310。因此，在移除第二承载基板202后，第二侧重布线结构206的上表面没有封装胶310。因此，封装胶310的最顶部表面可以与第二侧重布线结构206的上表面齐平或自第二侧重布线结构206的上表面凹陷。
请继续参阅图4C，在一些实施例中，钝化层320在暴露的第二侧重布线结构206之上形成和图案化。钝化层320可为一介电材料，其形成的方法和材料可类似于介电层110、114、118、122中的任一者。或者，钝化层320可为一阻焊材料，其形成的方法和材料可类似于阻焊材料222。
在图4D中，封装体400可翻转于临时基板406之上且贴附于临时基板406，所述临时基板406例如为胶带、晶圆、面板、框架、环体、或类似物。第一承载基板102接着被移除。在一些实施例中，承载基板拆除被执行以使第一承载基板102从第一侧重布线结构106分离(或拆卸或脱胶)，例如介电层110。根据一些实施例，拆除包括投射光线(例如激光光或紫外线光)在释放层104上，从而释放层104在光线的热能之下分解，第一承载基板102可被移除。
在图4E中，导电连接器410形成在第一侧重布线结构106上。导电连接器410可为球栅阵列封装(ball grid array,BGA)连接器、焊球、金属柱、C4(controlled collapse chipconnection)凸块、微凸块、化镍钯金技术(ENEPIG)形成的凸块、或类似物。导电连接器410可包括一导电材料，例如焊料、铜、铝、金、镍、银、钯、锡、类似物、或其组合。在一些实施例中，导电连接器410通过最初通过蒸镀法(evaporation)形成一层焊料、有电电镀、印制(printing)、焊料转移(solder transfer)、植球(ball placement)、或类似方式形成。一旦一层焊料形成在结构上，回焊可被执行，以使材料被塑形为所所需的凸块形状。在另一实施例中，导电连接器410包括金属柱(例如铜柱)，通过溅镀、印制、有电电镀、无电电镀、化学气相沉积、或类似方式形成。金属柱可不需要焊料且可具有大致垂直的侧壁。在一些实施例中，一金属盖层形成在金属柱的顶部。金属盖层可包括镍、锡、锡铅(tin-lead)、金、银、钯、铟、镍钯金(nickel-palladium-gold)、镍金(nickel-gold)、类似物、或其组合，且可通过电镀工艺形成。
根据一些实施例，若尚未单体化，结构可接着沿着划线区域404(例如参见图4A)单体化。或者，结构可在形成导电连接器410之前单体化。在一些实施例中，结构可利用一或多个锯刃单体化，将封装体400分开为分离的片块，形成一或多个单体化封装体400。然而，任何适合的单体化方法(包括激光剥蚀(laser ablation)或一或多个湿式蚀刻)也可以被利用。
在单体化之后，第一侧重布线结构106具有宽度W1，所述宽度W1可为约3毫米至约150毫米。第二元件200及其第二侧重布线结构206具有宽度W2，所述宽度W2可为约3毫米至约150毫米。宽度W2可小于或相等于宽度W1(例如第一元件及其第一重布线结构106的宽度)。宽度W1和宽度W2的比值可为约1至约3、或约1。比值在此范围中可使整个半导体封装体在第二侧重布线结构206耦合至第一侧重布线结构106时不易翘曲。换言之，第二侧重布线结构206的强度和宽度W2将平衡第一侧重布线结构106可能会发生的翘曲。
在图4F和图4G中，在单体化之后，封装体400可从临时基板406移除，并翻转于另外的基板之上且贴附至此另外的基板，所述另外的基板例如基板503(例如承载基板、封装基板、印刷电路板(PCB)、或类似物)。如图所示，封装体400可以以钝化层320作为特点(图4F)或者钝化层320可被省略(图4G)。在封装体400中的一些情况中，贯通孔126可对齐导电通孔218，如图4G的扩展部分所描绘。取决于形成的方法，导电通孔218可具有向内倾斜的侧壁。在一些情况下，向内倾斜的侧壁可具有内凹(concave)形状，使导电通孔218具有沙漏形状。此外，导电通孔218可具有齿状侧壁。齿状侧壁某些部分是归因于钻孔穿过介电层212的激光剥蚀方式，如关于图3F先前所说明的。
在图4H中，示出了一个实施例，类似于关于图4F先前所说明的，其中额外装置511贴附至基板503。额外装置511可包括主动装置及/或被动装置，例如集成被动装置(integrated passive devices)和表面安装元件(surface mount devices,SMD)(例如电容)。此外，额外装置511可包括类似于集成电路芯片50的装置，以及为了预期目的设计的装置，像是存储器芯片(例如动态随机存取存储器(DRAM)芯片、堆叠式存储器芯片(stackedmemory die)、高频宽存储器(HBM)芯片等)、逻辑芯片、中央处理器(CPU)芯片、单芯片系统(SoC)、晶圆上元件(a component on a wafer,CoW)、集成扇出型结构(integrated fan-out structure,InFO)、封装体、类似物、或其组合。
图5A至图5H以及图6A至图6H描述了根据一些实施例，形成第一元件(包括第一集成电路芯片50)、形成第二元件(包括第二集成电路芯片50的贴附)、以及将第二元件贴附至第一元件和形成半导体封装体的其他工艺的各种中间步骤。
图5A至图5H是表示根据一些实施例，形成第一元件501、第二元件502、以及封装体504的中间步骤的剖视图。具体而言，所述附图描绘了形成第一元件501、将第二元件502贴附至第一元件501(以及额外步骤)以形成封装体504的某些中间步骤。
在图5A中，第一元件501的第一侧重布线结构106被提供，且贯通孔126和接合垫128形成在第一侧重布线结构106之上。类似于先前关于图2A至图2F所说明的工艺和材料可被使用。在图5B中，第一集成电路芯片50与一或多个其他的半导体装置550一起贴附(仅表示了一个，但可有多个额外的半导体装置)。类似于先前关于图2G所说明的工艺和材料可被使用。
第一集成电路芯片50和其他装置550可包括为了预期目的设计的装置，像是存储器芯片(例如动态随机存取存储器(DRAM)芯片、堆叠式存储器芯片(stacked memory die)、高频宽存储器(HBM)芯片等)、逻辑芯片、中央处理器(CPU)芯片、单芯片系统(SoC)、晶圆上元件(CoW)、集成扇出型结构(InFO)、封装体、类似物、或其组合。第一集成电路芯片50和其他装置550可在同一技术节点(technology node)的工艺中形成，或是可在相异技术节点的工艺中形成。举例而言，第一集成电路芯片50可为比其他装置550更进步的技术节点。第一集成电路芯片50和其他装置550可具有相异尺寸(例如相异高度及/或表面面积)，或可具有相同尺寸(例如相同高度及/或表面面积)。第一侧重布线结构106的优势在于在集成电路芯片50、其他装置550、随后贴附的第二元件502、以及随后贴附至第一侧重布线结构106的另一侧的元件之间提供电性连接。
在一些实施例中，第一集成电路芯片50和其他装置包括晶体管、电容、电感、电阻、金属化层、外部连接器、以及类似物在其中，为了特定功能设计。在一些实施例中，第一集成电路芯片50和其他装置可包括多于一个相同类型的装置，或可包括不同的装置。图5B显示了单一集成电路芯片50，但在一些实施例中，一个、两个、或更多的集成电路芯片50或其他装置可贴附至第一侧重布线结构106。图5B描绘了集成电路芯片50为具有比贯通孔126较低的高度。这是为了容置第二元件502，第二元件502将包括另一集成电路芯片(如之后的附图中所示)。举例而言，贯通孔126可具有约10微米至约200微米的高度HTV，且集成电路芯片50可具有约30微米至约250微米的高度HIC1。高度HTV和高度HIC1的比值可为约0.04至约8。
在图5C中，提供了第二元件502的第二侧重布线结构206，且阻焊材料222可形成和图案化，以形成除了开口224以外的开口228。类似于先前关于图3A至图3H所说明的工艺和材料可被使用。一些或所有的开口228可暴露导电通孔218和第二金属走线220的部分。开口228与开口224可使用相同或不同的图案化方法同时形成或在不同时间点形成。
在图5D中，一第二集成电路芯片50可于开口228处贴附至第二侧重布线结构206，且电性耦合至导电通孔218和第二金属走线220。类似于先前关于图2G至图5B所说明的工艺和材料可被使用，包括接合垫528、焊料接点530、以及底部填充材料532的形成。此外，连接器226可在开口224中形成。
在图5E中，第二元件502(包括第二侧重布线结构206和第二集成电路芯片50)贴附至第一元件501，且第二承载基板202利用类似于先前关于图4A至图4C所说明的工艺和材料移除。如先前关于封装体400所说明的，封装体504具有的第一侧重布线结构106的宽度W1大于第二侧重布线结构206的宽度W2，且可形成封装胶310包围第二侧重布线结构206的侧边边缘，类似于图4B至图4H所示。如所示，第二元件502被贴附，从而第一集成电路芯片50和第二集成电路芯片50的背侧相互面向对方。第一和第二集成电路芯片50的任一者或两者可具有沿着背侧的介电层510，其可接着直接插入于第一和第二集成电路芯片50之间。
请继续参阅图5E，介电层510可类似于粘贴层70，且可以以类似方式应用。第一和第二集成电路芯片50可垂直地排列，因此第二集成电路芯片50的至少一部分直接在第一集成电路芯片的至少一部分之上。第一和第二集成电路芯片50可位于彼此中央，或者是非对称地设置。
封装体504可接着被完成，如图5F至图5H所示，且可以以如前所述的类似方式，例如关于图4D至图4H。如图5G所示，第三集成电路芯片50可通过类似于先前关于图2G、图5B、图5D所说明的工艺和材料贴附至第一侧重布线结构106。如图5H所示，第四集成电路芯片50和额外装置550可利用类似于先前关于图2G、图4H、图5B、图5D所说明的工艺和材料贴附至第二侧重布线结构206。前述布置的优势包括在水平方向给予更狭小的封装体504及/或沿着第一侧重布线结构106提供更多空间以贴附额外装置。
如前所述，第一侧重布线结构106和第二侧重布线结构206分离一厚度T3。在本实施例中，厚度T3可为约60微米至约500微米。厚度T3和厚度T1的比值可为约0.5至约25。厚度T3和厚度T2的比值可为约0.4至约25。此外，连接器226可具有约10微米至约300微米的高度HC、或约150微米。因此，封装体504中的贯通孔126和连接器226的总高度可为约50微米至约500微米、或约250微米(应注意的是总高度可小于高度HC和高度HTV的总合，因为回焊了连接器226)，所述总高度可大致相等于第一侧重布线结构106和第二侧重布线结构206之间的区域的厚度T3。再如图5H所示，第一集成电路芯片50和第二集成电路芯片的总高度(分别为高度HIC1和高度HIC2，加上介电层510的厚度)可大致相等于厚度T3。
图6A至图6H是表示根据一些实施例，形成封装体604的中间步骤的剖视图。具体而言，所述附图描绘了形成第一元件601、将第二元件602贴附至第一元件601(以及额外步骤)以形成封装体604的某些中间步骤。
在图6A中，第一元件601的第一侧重布线结构106被提供，且贯通孔126和接合垫128形成在第一侧重布线结构106之上。类似于先前关于图2A至图2F和图5A所说明的工艺和材料可被使用。在图6B中，第一集成电路芯片50与一或多个其他的半导体装置650一起贴附。类似于先前关于图2G和图5B所说明的工艺和材料可被使用。图6B描绘了集成电路芯片50为具有比贯通孔126较低的高度。这是为了容置第二元件602，第二元件602将包括另一集成电路芯片50。举例而言，贯通孔126可具有约10微米至约300微米的高度HTV，且集成电路芯片50可具有约30微米至约300微米的高度HIC1。高度HTV和高度HIC1的比值可为约0.03至约10。
在图6C中，提供了第二元件602的第二侧重布线结构206，且阻焊材料222可形成和图案化，以形成除了开口224以外的开口228。类似于先前关于图3A至图3H和图5C所说明的工艺和材料可被使用。一些或所有的开口228可暴露导电通孔218和第二金属走线220的部分。开口228与开口224可使用相同或不同的图案化方法同时形成或在不同时间点形成。
在图6D中，一第二集成电路芯片50可于开口228处贴附至第二侧重布线结构206，且电性耦合至导电通孔218和第二金属走线220。类似于先前关于图2G、图5B、图5D、图6B所说明的工艺和材料可被使用，包括接合垫628、焊料接点630、以及底部填充材料632的形成。
在图6E中，第二元件602(包括第二侧重布线结构206和第二集成电路芯片50)贴附至第一元件601，且第二承载基板202利用类似于先前关于图4A至图4C和图5E所说明的工艺和材料移除。如先前关于封装体400、504所说明的，封装体604具有的第一侧重布线结构106的宽度W1大于第二侧重布线结构206的宽度W2，且可形成封装胶310包围第二侧重布线结构206的侧边边缘，类似于图4B至图4H所示。如所示，第二元件602被贴附，从而第二集成电路芯片50从第一集成电路芯片50横向地位移。此横向位移允许第二集成电路芯片50的背侧表面低于第一集成电路芯片50的背侧表面，虽然所述背侧表面可位于同一水平、或第二集成电路芯片50的背侧表面可高于第一集成电路芯片50的背侧表面。
封装体604可接着被完成，如图6F至图6H所示，且可以以如前所述的类似方式，例如关于图4D至图4H以及图5F至图5H。如图6G所示，第三集成电路芯片50可通过类似于先前关于图2G、图5B、图5D、图6B、图6D所说明的工艺和材料贴附至第一侧重布线结构106。此外，外部连接器610可形成，以提供随后贴附其他集成电路装置或封装体的元件。如图6H所示，第四集成电路芯片50和额外装置650可利用类似于先前关于图2G、图4H、图5B、图5D、图5G、图5H、图6B、图6D所说明的工艺和材料贴附至第二侧重布线结构206。前述布置的优势包括提供更薄的封装体604。
如前所述，第一侧重布线结构106和第二侧重布线结构206分离一厚度T3。在本实施例中，厚度T3可为约50微米至约500微米。厚度T3和厚度T1的比值可为约0.4至约25。厚度T3和厚度T2的比值可为约0.0.至约10。此外，连接器226可具有约10微米至约300微米的高度HC、或约150微米。因此，封装体604中的贯通孔126和连接器226的总高度可为约100微米至约600微米、或约300微米(应注意的是总高度可小于高度HC和高度HTV的总合，因为回焊了连接器226)，所述总高度可大致相等于第一侧重布线结构106和第二侧重布线结构206之间的区域的厚度T3。再如图6H所示，厚度T3小于第一集成电路芯片50和第二集成电路芯片(分别为高度HIC1和高度HIC2)堆叠的总高度。换言之，第一和第二集成电路芯片50相对于彼此的横向位移允许了更低的厚度T3。在一些实施例中，第一侧重布线结构106和第二集成电路芯片50的背侧表面之间的封装胶310的厚度可为约30微米至约300微米，例如约150微米。此外，第二侧重布线结构206和第一集成电路芯片50之间的封装胶310的厚度可为约30微米至约300微米，例如150微米。
实施例对用于集成电路的系统级封装(SiP)结构可实现许多优点。举例而言，双边布线(例如第二侧和第一侧重布线结构)允许布线的各侧更薄，且允许整体半导体封装体更薄同时减少整体封装体翘曲。此外，用在布线结构之一的载体型基板提供较好的结构支撑，其同样减少整体封装体翘曲。再者，描述的设计方法提供嵌埋的集成电路芯片和其他装置的布线的多样性。当然，垂直堆叠的集成电路芯片可提供足够的空间予额外装置来贴附至第一侧重布线结构，反之横向位移的集成电路芯片可允许整体更薄的封装体结构。应注意的是，第一侧重布线结构可比第二侧重布线结构更宽，这允许了形成封装胶包围第二侧重布线结构，以加强封装体且更减少整体封装体翘曲。当然，描述的设计方法提供封装胶以没有沿着第二侧重布线结构的外表面成型蔓延的风险的方式应用。这可确保额外装置可贴附至第二侧重布线结构的外表面，而不会受到微量(trace amounts)封装胶的干扰。
在一实施例中，一半导体封装体通过将一第一元件贴附至一第二元件制造。第一元件通过在一基板之上形成一第一重布线结构装配。一贯通孔接着形成在第一重布线结构之上，且一芯片贴附至第一重布线结构，主动侧朝下。第二元件包括一第二重布线结构，其接着贴附至贯通孔。一成型模料沉积在第一重布线结构和第二重布线结构之间，且还包围第二元件的侧边。
在另一实施例中，一半导体封装体通过形成一第一元件、形成一第二封装元件、以及贴附第二元件至第一元件制造。第一元件通过在一基板之上形成一重布线结构、在重布线结构之上形成一贯通孔、以及将一芯片贴附至重布线结构形成。第二元件通过在另一基板之上形成另一重布线结构、在此重布线结构之上形成一连接器、以及将另一芯片贴附至此重布线结构形成。第二元件通过将其在贯通孔上翻转且利用回焊连接器接合连接器至贯通孔来贴附。在贴附之后，基板从第二元件移除。
在又一实施例中，一半导体封装体包括在一基板上的一第一重布线结构、以及堆叠在第一重布线结构的顶部的第二重布线结构。第二重布线结构包括一导电通孔。第一重布线结构比第二重布线结构更宽。一贯通孔将第一重布线结构电性耦合至第二重布线结构。一芯片贴附至第一重布线结构，芯片的主动侧面向且电性耦合至第一重布线结构。另一芯片贴附至第二重布线结构，此芯片的主动侧面向且电性耦合至第二重布线结构。一封装胶填充于第一重布线结构和第二重布线结构之间的区域中。
本发明实施例提供一种半导体封装体的形成方法，包括形成一第一元件，且形成该第一元件包括：在一第一基板之上形成一第一重布线结构；在第一重布线结构之上形成一贯通孔；将一第一芯片贴附至第一重布线结构，第一芯片的主动侧面向且电性耦合至第一重布线结构。半导体封装体的形成方法还包括将一第二元件贴附至贯通孔，第二元件包括贴附至一第二基板的一第二重布线结构、以及在贴附第二元件之后，在第一重布线结构和第二重布线结构之间沉积一成型模料，成型模料的部分围绕第二重布线结构的侧边边缘。
在一些实施例中，半导体封装体的形成方法还包括在第二基板之上形成第二重布线结构、将一第二芯片贴附至第二重布线结构，第二芯片的主动侧面向且电性耦合至第二重布线结构、以及在第二重布线结构之上沉积一焊球。在一些实施例中，将第二元件贴附的步骤包括回焊焊球以将贯通孔电性耦合至第二重布线结构。在一些实施例中，将第二元件贴附的步骤包括贴附第二元件使得第二芯片直接位在第一芯片之上，第一芯片的背侧面向第二芯片的背侧。在一些实施例中，将第二元件贴附的步骤包括贴附第二元件使得第二芯片自第一芯片横向位移，第一芯片的侧边面向第二芯片的侧边。在一些实施例中，形成第二重布线结构的步骤包括在第一基板之上形成一第一金属走线、在第一金属走线之上沉积一ABF膜(Ajinomoto Build-up Film)、在ABF膜中激光钻孔一开口、在开口中形成一导电通孔、以及在导电通孔之上形成一第二金属走线。在一些实施例中，半导体封装体的形成方法还包括移除第二基板、以及在移除第二基板之后，将多个被动装置贴附至第二重布线结构。
本发明实施例亦提供一种半导体封装体，包括一第一元件、一第二元件、以及一封装胶。第一元件包括一第一重布线结构、一贯通孔、以及一第一芯片。贯通孔设置在第一重布线结构之上。第一芯片贴附至第一重布线结构，且第一芯片的主动侧面向第一重布线结构。第二元件包括一第二重布线结构、一连接器、以及一第二芯片。连接器将贯通孔耦合至第二重布线结构。第二芯片贴附至第二重布线结构的一第一侧，第二芯片的主动侧面向第二重布线结构。封装胶设置在第一重布线结构和第二重布线结构之间。
在一些实施例中，封装胶封装第一芯片和第二芯片的侧边边缘。在一些实施例中，封装胶接触第二重布线结构的侧边边缘。在一些实施例中，半导体封装体还包括一钝化层和一第三芯片。钝化层设置在第二重布线结构的一第二侧之上，第二侧相反于第一侧。第三芯片设置于在第二重布线结构的第二侧上的钝化层之上。在一些实施例中，从平面图看，第二芯片的部分与第一芯片的部分重叠。在一些实施例中，第二芯片自第一芯片横向地位移。在一些实施例中，半导体封装体还包括一被动装置，贴附至第二重布线结构的第二侧。
本发明实施例更提供一种半导体封装体，包括一第一重布线结构、一第二重布线结构、一第一芯片、一第二芯片、一封装胶、以及一贯通孔。第一重布线结构具有一第一宽度。第二重布线结构设置在第一重布线结构之上，且包括从一第一金属走线延伸至一第二金属走线的一导电通孔。第一金属走线沿着第二重布线结构的一第一侧设置，第二金属走线沿着第二重布线结构的一第二侧设置。第二重布线结构具有一第二宽度，且第一宽度大于第二宽度。第一芯片贴附至第一重布线结构，第一芯片的一第一主动侧面向且电性耦合至第一重布线结构。第二芯片贴附至第二重布线结构，第二芯片的一第二主动侧面向且电性耦合至第二重布线结构。封装胶直接插入第一重布线结构和第二重布线结构之间。贯通孔延伸穿过封装胶，贯通孔将第一重布线结构电性耦合至第二重布线结构。
在一些实施例中，封装胶接触第一芯片的整个侧边边缘、第二芯片的整个侧边边缘、以及第二重布线结构的侧边边缘的至少一部分。在一些实施例中，第一重布线结构为一扇出型重布线结构。在一些实施例中，导电通孔直接设置在贯通孔之上且电性耦合至贯通孔。在一些实施例中，第一芯片包括一第一背侧，相反于第一主动侧，第二芯片包括一第二背侧，相反于第二主动侧，且第二背侧比第一背侧更为接近第一重布线结构。在一些实施例中，半导体封装体还包括一被动装置，贴附且电性耦合至第二重布线结构相反于第一重布线结构的一侧。
以上概略说明了本公开数个实施例的特征，使所属技术领域中技术人员可更为清楚地理解本公开的各面向。任何所属技术领域中技术人员应了解到本公开可作为其它结构或工艺的设计或变更基础，以进行相同于本公开实施例的目的及/或获得相同的优点。任何所属技术领域中技术人员也可理解与上述等同的结构或工艺并未脱离本公开的构思和保护范围内，且可在不脱离本公开的构思和范围内，当可作变动、替代与润饰。

Claims (10)

1.一种半导体封装体的形成方法，该形成方法包括：
形成一第一元件，形成该第一元件包括：
在一第一基板之上形成一第一重布线结构；
在该第一重布线结构之上形成一贯通孔；
将一第一芯片贴附至该第一重布线结构，该第一芯片的主动侧面向且电性耦合至该第一重布线结构；
将一第二元件贴附至该贯通孔，该第二元件包括贴附至一第二基板的一第二重布线结构；以及
在贴附该第二元件之后，在该第一重布线结构和该第二重布线结构之间沉积一成型模料，该成型模料的部分围绕该第二重布线结构的侧边边缘。
2.如权利要求1的形成方法，还包括：
在该第二基板之上形成该第二重布线结构；
将一第二芯片贴附至该第二重布线结构，该第二芯片的主动侧面向且电性耦合至该第二重布线结构；以及
在该第二重布线结构之上沉积一焊球。
3.如权利要求2的形成方法，其中将该第二元件贴附的步骤包括贴附该第二元件使得该第二芯片直接位在该第一芯片之上，该第一芯片的背侧面向该第二芯片的背侧。
4.如权利要求2的形成方法，其中将该第二元件贴附的步骤包括贴附该第二元件使得该第二芯片自该第一芯片横向位移，该第一芯片的侧边面向该第二芯片的侧边。
5.一种半导体封装体，包括：
一第一元件，包括：
一第一重布线结构；
一贯通孔，设置在该第一重布线结构之上；以及
一第一芯片，贴附至该第一重布线结构，该第一芯片的主动侧面向该第一重布线结构；
一第二元件，包括：
一第二重布线结构；
一连接器，该连接器将该贯通孔耦合至该第二重布线结构；以及
一第二芯片，贴附至该第二重布线结构的一第一侧，该第二芯片的主动侧面向该第二重布线结构；以及
一封装胶，设置在该第一重布线结构和该第二重布线结构之间。
6.如权利要求5的半导体封装体，还包括：
一钝化层，设置在该第二重布线结构的一第二侧之上，该第二侧相反于该第一侧；以及
一第三芯片，设置于在该第二重布线结构的该第二侧上的该钝化层之上。
7.如权利要求5的半导体封装体，还包括一被动装置，贴附至该第二重布线结构的该第二侧。
8.一种半导体封装体，包括：
一第一重布线结构，该第一重布线结构具有一第一宽度；
一第二重布线结构，设置在该第一重布线结构之上，该第二重布线结构包括从一第一金属走线延伸至一第二金属走线的一导电通孔，该第一金属走线沿着该第二重布线结构的一第一侧设置，该第二金属走线沿着该第二重布线结构的一第二侧设置，该第二重布线结构具有一第二宽度，该第一宽度大于该第二宽度；
一第一芯片，贴附至该第一重布线结构，该第一芯片的一第一主动侧面向且电性耦合至该第一重布线结构；
一第二芯片，贴附至该第二重布线结构，该第二芯片的一第二主动侧面向且电性耦合至该第二重布线结构；
一封装胶，直接插入该第一重布线结构和该第二重布线结构之间；以及
一贯通孔，延伸穿过该封装胶，该贯通孔将该第一重布线结构电性耦合至该第二重布线结构。
9.如权利要求8的半导体封装体，其中该封装胶接触该第一芯片的整个侧边边缘、该第二芯片的整个侧边边缘、以及该第二重布线结构的侧边边缘的至少一部分。
10.如权利要求8的半导体封装体，其中该第一芯片包括一第一背侧，相反于该第一主动侧，其中该第二芯片包括一第二背侧，相反于该第二主动侧，且其中该第二背侧比该第一背侧更为接近该第一重布线结构。
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