TW202234646A - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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Publication number
TW202234646A
TW202234646A TW111106006A TW111106006A TW202234646A TW 202234646 A TW202234646 A TW 202234646A TW 111106006 A TW111106006 A TW 111106006A TW 111106006 A TW111106006 A TW 111106006A TW 202234646 A TW202234646 A TW 202234646A
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Taiwan
Prior art keywords
redistribution structure
redistribution
core substrate
layer
conductive
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TW111106006A
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English (en)
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吳俊毅
余振華
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台灣積體電路製造股份有限公司
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Publication of TW202234646A publication Critical patent/TW202234646A/zh

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Abstract

一種半導體裝置包括：重佈線結構；積體電路封裝，貼合到重佈線結構的第一側；以及芯體基底，利用第一導電連接件及第二導電連接件耦合到重佈線結構的第二側。第二側與第一側相對。半導體裝置還包括：包含介電材料的芯體基底的頂部層以及設置在重佈線結構與芯體基底之間的晶片。晶片夾置在介電材料的側壁之間。

Description

半導體裝置及其形成方法
本發明實施例涉及一種半導體裝置及其形成方法。
由於各種電子元件（例如，電晶體、二極體、電阻器、電容器等）的積體密度的持續改善，半導體行業已經歷快速發展。在很大程度上，積體密度的改善源自於最小特徵大小（minimum feature size）的不斷減小，此使得更多的組件能夠積體到給定面積中。隨著對縮小電子元件的需求已增加，已出現對更小且更具創造性的半導體晶粒封裝技術的需要。此種封裝系統的實例是疊層封裝（Package-on-Package，PoP）技術。在PoP裝置中，頂部半導體封裝被堆疊在底部半導體封裝的頂部上，以提供高積體水準及元件密度。PoP技術一般能夠生產功能性得到增強且在印刷電路板（printed circuit board，PCB）上佔用空間小的半導體裝置。
本發明實施例提供一種半導體裝置，包括：重佈線結構；積體電路封裝，貼合到所述重佈線結構的第一側；芯體基底，利用第一導電連接件及第二導電連接件耦合到所述重佈線結構的第二側，所述第二側與所述第一側相對，所述芯體基底的頂部層包含介電材料；以及晶片，設置在所述重佈線結構與所述芯體基底之間，所述晶片夾置在所述介電材料的側壁之間。
以下揭露提供用於實施所提供主題的不同特徵的許多不同實施例或實例。下文描述組件及配置的具體實例用以簡化本揭露。當然，此等組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或第二特徵上的形成可包含第一特徵以及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複附圖標號及/或字母。此重複出於簡單及明晰的目的，且其本身並不指示所論述的各種實施例及/或組態之間的關係。
另外，為了便於描述，可在本文中使用諸如「在……之下」、「在……下方」、「下部」、「在……上方」、「上部」以及類似者的空間相對術語，以描述如圖中所示出的一個元件或特徵與另一（些）元件或特徵的關係。除圖中所描繪的定向外，空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。裝置可以其他方式定向（旋轉90度或處於其他定向），且本文中所使用的空間相對描述詞同樣可相應地進行解譯。
本文中論述的實施例可在特定的上下文（即包括一個或多個積體電路晶粒的封裝組件）中進行論述。在一些實施例中，封裝組件是積體基底上系統（system-on-integrated-substrate，SoIS）封裝。封裝組件包括晶片，例如積體電壓調節器（integrated voltage regulator，IVR），所述積體電壓調節器設置在重佈線結構與芯體基底之間，與積體電路封裝相對。在重佈線結構與芯體基底之間放置積體電壓調節器能夠使得積體電路封裝與積體電壓調節器之間的距離更短，此實現改善的電源完整性（power integrity）及更好的效能。
圖1示出根據一些實施例的經單體化封裝組件100的剖視圖。圖2示出根據一些實施例的圖1所示剖視圖的區1000的詳細視圖。經單體化封裝組件100包括半導體元件（例如，積體電路封裝110），所述半導體元件透過多個導電連接件170耦合到具有一個或多個重佈線層的重佈線結構210。保護環（protective ring）160可耦合到重佈線結構210且沿著積體電路封裝110的週邊延伸。保護環160的頂表面可與積體電路封裝110的頂表面齊平。在一些實施例中，保護環160具有從保護環160的頂表面到重佈線結構210的頂表面測量的高度H1，高度H1介於50 μm到1500 μm的範圍內。在一些實施例中，經單體化封裝組件100具有在相對的側壁之間測量的最大寬度W1，最大寬度W1介於30 mm到500 mm的範圍內。
芯體基底（core substrate）300透過多個導電連接件390在與積體電路封裝110相對的側上耦合到重佈線結構210。多個外部連接件620在芯體基底300的與重佈線結構210相對的側上提供通往芯體基底300的電連接。
在重佈線結構210與芯體基底300之間設置有積體電壓調節器（IVR）200。積體電壓調節器200可向積體電路封裝110供應電力及調節電力。與積體電路封裝110相對地將積體電壓調節器200貼合到重佈線結構210可在積體電壓調節器200與積體電路封裝110之間提供最短距離D1（最短距離D1介於0.1 mm到1.0 mm的範圍內，例如介於0.1 mm到0.3 mm的範圍內），此對於提供具有減輕的電壓降及功率降（voltage and power drop）的更高效的電壓域（voltage domain）為有用的，此可改善積體電路封裝110的電源完整性。經改善的電源完整性可能夠提高工作頻率（operation frequency）及降低電源電壓，以滿足高效能計算（high performance computing，HPC）要求。透過在重佈線結構210與芯體基底300之間封裝積體電壓調節器200，可形成提供更高的SoIS良率的緊湊的系統（compact system），所述緊湊的系統可利用現有的矽製造工具及製程進行製造。
最短距離D1介於0.1 mm到1.0 mm的範圍內可提供上述優點，例如改善積體電路封裝110的電源完整性。最短距離D1小於0.05 mm可能是不利的，因為它可能導致對積體電路封裝110不利的熱影響。最短距離D1大於1.0 mm可能是不利的，因為它可能導致積體電路封裝110中的電壓降及功率降，此可能降低裝置效能。
積體電路封裝110可包括多個積體電路晶粒（integrated circuit die），例如邏輯晶粒（例如，中央處理器（central processing unit，CPU）、圖形處理單元（graphic processing unit，GPU）、系統晶片（system-on-a-chip，SoC）、應用處理器（application processor，AP）、微控制器等）、記憶體晶粒（例如，動態隨機存取記憶體（dynamic random access memory，DRAM）晶粒、靜態隨機存取記憶體（static random access memory，SRAM）晶粒等）、功率管理晶粒（例如，功率管理積體電路（power management integrated circuit，PMIC）晶粒）、射頻（radio frequency，RF）晶粒、感測器晶粒（sensor die）、微機電系統（micro-electro-mechanical-system，MEMS）晶粒、訊號處理晶粒（例如，數位訊號處理（digital signal processing，DSP）晶粒）、前端晶粒（例如，類比前端（analog front-end，AFE）晶粒）、輸入/輸出（input/output，I/O）晶粒、類似晶粒、或其組合。如圖所示，出於例示目的，積體電路封裝110包括邏輯晶粒112（例如，SoC）及兩個I/O晶粒114。所述積體電路晶粒可形成在一個或多個晶圓中，所述一個或多個晶圓可包括在後續步驟中被單體化的不同裝置區。所述積體電路晶粒可使用例如積體扇出型（Integrated Fan-Out，INFO）封裝等製造技術與其他類似或不同的積體電路晶粒封裝在一起。積體電路封裝110可包括：重佈線結構116，在例如邏輯晶粒112與I/O晶粒114之間提供電路徑及電連接，以及提供從積體電路封裝110到導電連接件170的連接。
導電連接件170在重佈線結構210與積體電路封裝110之間提供電連接。可包括底部填充膠（underfill）195，以將積體電路封裝110牢固地接合到重佈線結構210且提供結構支撐及環境保護。
如以下所更詳細地論述，重佈線結構210透過導電連接件170及導電連接件390在積體電路封裝110與芯體基底300之間提供電路徑及電連接。在一些實施例中，重佈線結構210具有一個或多個重佈線層，所述一個或多個重佈線層包括多個金屬化圖案以及多個介電層，所述金屬化圖案包括例如多個導電線及多個導通孔，所述介電層將相鄰層的導電線隔開，如以下例如關於圖4到圖5所論述的。金屬化圖案的導電線可使用導通孔與上覆的導電特徵或下伏的導電特徵內連。
重佈線結構210電貼合及機械貼合到芯體基底300。芯體基底300可包括：芯體（core）310、具有延伸穿過芯體310的多個導通孔320、以及附加可選的多個重佈線結構340（沿著芯體310的相對的側）。在一些實施例中，芯體310在中心芯體的頂表面與底表面之間具有介於30 μm到2000 μm的範圍內的厚度。一般來說，芯體基底300為封裝組件提供結構支撐，並在積體電路封裝110與外部連接件620之間提供電訊號路由（electrical signal routing），外部連接件620可實體耦合和電耦合到下部的重佈線結構340的底表面上的凸塊下金屬（under-bump metallurgy，UBM）330。
在重佈線結構210與芯體基底300之間可包括包封體520，以牢固地接合相關聯的元件並提供結構支撐及環境保護。包封體520可由例如模制化合物、模制底部填充膠、環氧樹脂、樹脂、或類似物等有機材料形成或包含所述有機材料。
如在圖2中所更詳細地示出，積體電壓調節器200在芯體基底300上方貼合到重佈線結構210的下側。積體電壓調節器200可具有介於20 μm到100 μm的範圍內的高度H2。積體電壓調節器200的與重佈線結構210相對的側可具有介於500 μm 2到20000 μm 2的範圍內的表面積。在一些實施例中，積體電壓調節器200貼合到延伸穿過介電層220以接觸重佈線結構210的重佈線層209F的多個通孔212，且芯體基底300的凸塊下金屬330A上的多個導電連接件390耦合到通孔212上的多個凸塊下金屬（UBM）214。在其他實施例中，不存在通孔212及介電層220，且積體電壓調節器200及導電連接件390實體耦合及電耦合到重佈線結構210的重佈線層209F的多個導電特徵。
積體電壓調節器200可透過位於積體電壓調節器200的頂表面上的多個導電連接件202耦合到通孔212。導電連接件202可透過多個焊料區204（例如，如微凸塊）耦合到通孔212。然而，可使用任何合適的導電連接件來將積體電壓調節器200與通孔212或重佈線結構210的導電特徵耦合。在一些實施例中，導電連接件202及焊料區204具有介於10 μm到25 μm的範圍內的高度H3。可圍著導電連接件202及焊料區204在介電層220之上設置底部填充膠206。底部填充膠206可透過毛細流動製程或另一種合適的沉積方法在積體電壓調節器200與介電層220之間環繞導電連接件202及焊料區而形成。底部填充膠206可減少導電連接件202上的應力。底部填充膠206的材料可為液態環氧樹脂、可變形凝膠（deformable gel）、矽橡膠（silicon rubber）、其組合。
積體電壓調節器200可設置在芯體基底300的頂表面中（例如，如在芯體基底300的重佈線結構340A的頂表面之上的阻焊劑350A中）的開口360中。可形成穿過阻焊劑350A（參見下文，圖12）的開口360，以提供用於將積體電壓調節器200裝配在重佈線結構210與芯體基底300之間的空間。積體電壓調節器200的此種位置可提供具有減輕的電壓降及功率降的更高效的電壓域，此可改善後續貼合的積體電路封裝110（參見下文，圖18）的電源完整性。開口360可由積體電壓調節器200及包封體520填充。開口360可分別在阻焊劑350A與積體電壓調節器200的相對的側壁之間具有寬度W2（寬度W2介於5 μm到200 μm的範圍內），此對於提供用於將積體電壓調節器200裝配在重佈線結構210與芯體基底300之間的空間，從而改善積體電路封裝110的電源完整性是為有用的。寬度W2小於5 μm可能是不利的，因無提供足夠的空間來裝配積體電壓調節器200。寬度W2大於200 μm可能是不利的，因為它可能導致耦合重佈線結構210與芯體基底300的導電連接件390更少，此可能降低裝置效能。
在芯體基底300的重佈線結構340A與介電層220的相對的表面之間測量的距離D2介於147 μm到500 μm的範圍內，此對於提供用於將積體電壓調節器200裝配在重佈線結構210與芯體基底300之間的空間，從而改善積體電路封裝110的電源完整性是為有用的。小於147 μm的距離D2可能可能是不利的，因無提供足夠的空間來裝配積體電壓調節器200。大於500 μm的距離D2可能是不利的，因為它可能導致重佈線結構210與芯體基底300之間的連接變差（其在導電連接件390中具有更高的電阻），此可能降低裝置效能。
圖3到圖15、圖18及圖19示出根據一些實施例的用於形成經單體化封裝組件100的製程期間的中間步驟的剖視圖。示出第一封裝區（又稱封裝區）101A及第二封裝區（又稱封裝區）101B，且對多個積體電壓調節器200中的一或多者進行封裝以在封裝區101A及101B中的每一者中形成封裝組件。為易於例示，已在圖3到圖19中簡化各個特徵的例示。
在圖3中，提供載體基底102。載體基底102可包含例如矽系材料（例如矽基底（例如，矽晶圓）、玻璃材料、氧化矽）、或其它材料（例如氧化鋁、類似物，或組合）。在一些實施例中，載體基底102可為面板結構（panel structure），所述面板結構可為例如由合適的介電材料（例如玻璃材料或有機材料）形成的支撐基底，且所述面板結構可具有矩形形狀。載體基底102可為平坦的，以便適應附加特徵（例如絕緣層103）的形成。
在一些實施例中，可在載體基底102的頂表面上形成釋放層（未示出），以有利於載體基底102的後續剝離。釋放層可由聚合物系材料形成，釋放層可與載體基底102一起從將在後續步驟中形成的上覆結構被移除。在一些實施例中，釋放層是在受熱時會失去其粘合性質的環氧樹脂系熱釋放材料，例如光-熱轉換（Light-to-Heat-Conversion，LTHC）釋放塗層。在其他實施例中，釋放層可為在暴露於紫外（ultra-violet，UV）光時會失去其粘合性質的紫外（UV）膠。釋放層可作為液體進行分配並被固化，可為被層壓（laminated）到載體基底102上的層壓膜、或者類似物。釋放層的頂表面可被整平（leveled）且可具有高度的共面性（co-planarity）。
圖4及圖5示出在載體基底102上形成重佈線結構210。圖4示出重佈線結構210的絕緣層103及重佈線層104的形成，且圖5示出重佈線結構210的多個絕緣層208A到208F及多個重佈線層209A到209F的形成。
在圖4中，可在載體基底102之上形成絕緣層103。絕緣層103的底表面可與釋放層（未示出）的頂表面接觸。在一些實施例中，絕緣層103由聚合物（例如聚苯並噁唑（polybenzoxazole，PBO）、聚醯亞胺（polyimide，PI）、苯並環丁烯（benzocyclobutene，BCB）、或類似物）形成。在其他實施例中，絕緣層103由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃（phosphosilicate glass，PSG）、硼矽酸鹽玻璃（borosilicate glass，BSG）、摻雜硼的磷矽酸鹽玻璃（boron-doped phosphosilicate glass，BPSG）或類似物；或者類似材料。絕緣層103可透過例如旋轉塗布、化學氣相沉積（chemical vapor deposition，CVD）、層壓、類似製程、或其組合等任何可接受的沉積製程來形成。在一些實施例中，絕緣層103具有介於5 μm到50 μm的範圍內的厚度，但可使用任何合適的厚度。
在圖4中，可透過使用例如物理氣相沉積（physical vapor deposition，PVD）、CVD、濺鍍、或類似製程等合適的形成製程初始地形成鈦、銅或鈦銅合金的一個或多個層的晶種層（未示出）來形成重佈線層104。在一些實施例中，重佈線層104包括多個接觸焊盤104A及多個導電線104B，接觸焊盤104A可為後續形成的多個連接件（參見下文，圖15）的著落位置。在載體基底102或絕緣層103（如果存在的話）之上形成晶種層。然後可形成光阻（同樣未示出）以覆蓋晶種層，且然後將光阻圖案化以暴露出晶種層的位於隨後將形成重佈線層104的地方的那些部分。一旦已形成光阻且將光阻圖案化，便可在晶種層上形成導電材料。導電材料可為例如銅、鈦、鎢、鋁、另一種金屬、類似物、或其組合等材料。導電材料可透過例如電鍍（electroplating）或化學鍍（electroless plating）等沉積製程或者類似製程來形成。然而，儘管所論述的材料及方法適合於形成導電材料，但這些僅僅是實例。可替代地使用任何其他合適的材料或任何其他合適的形成製程（例如CVD或PVD）來形成重佈線層104。一旦已形成導電材料，便可透過合適的移除製程（例如灰化或化學剝除）來移除光阻。另外，在移除光阻之後，可透過例如合適的濕法蝕刻製程或乾法蝕刻製程來移除晶種層的被光阻覆蓋的那些部分，所述濕法蝕刻製程或乾法蝕刻製程可使用導電材料作為蝕刻罩幕。晶種層的剩餘部分及導電材料的剩餘部分形成重佈線層104。在一些實施例中，重佈線層104的導電材料具有介於2 μm到50 μm的範圍內的厚度，但可使用任何合適的厚度。
接下來，在圖5中，根據一些實施例，在重佈線層104、絕緣層103及載體基底102之上形成重佈線結構210的附加層。所示重佈線結構210包括絕緣層103、重佈線層104、絕緣層208A到208F（為清晰起見，僅標記出絕緣層208A及208F）且包括重佈線層209A到209F（為清晰起見，僅標記出重佈線層209A及209F）。在其他實施例中，可在重佈線結構210中形成與本文所述不同數目的絕緣層或重佈線層。在一些實施例中，重佈線結構210可以與本文所述不同的製程來形成。在一些實施例中，重佈線結構210可為例如扇出型結構。
仍然參照圖5，在重佈線層104及絕緣層103之上形成絕緣層208A。絕緣層208A可由例如以下等一種或多種合適的介電材料製成：氧化物（例如，氧化矽）、氮化物（例如，氮化矽）、聚合物材料（例如，感光性聚合物材料）、聚醯亞胺材料、低介電常數（low dielectric constant，low-k）介電材料、另一種介電材料、類似介電材料、或其組合。絕緣層208A可透過例如旋轉塗布、層壓、CVD、類似製程、或其組合等製程來形成。在一些實施例中，絕緣層208A具有介於5 μm到50 μm的範圍內的厚度，但可使用任何合適的厚度。可使用合適的微影罩幕及蝕刻製程來形成絕緣層208A中的多個開口。舉例來說，可在絕緣層208A之上形成光阻且將光阻圖案化，並且利用一種或多種蝕刻製程（例如，濕法蝕刻製程或乾法蝕刻製程）來移除絕緣層208A的多個部分。在一些實施例中，絕緣層208A由感光性聚合物（例如PBO、聚醯亞胺、BCB、或類似物）形成，其中可使用微影罩幕及蝕刻製程直接圖案化出多個開口。絕緣層208A中的開口可暴露出重佈線層104。
然後可形成重佈線層209A，以在重佈線結構210內提供附加布線以及電連接。在實施例中，可使用類似於重佈線層104的材料及製程來形成重佈線層209A。舉例來說，可形成晶種層，在晶種層的頂部上放置光阻且按照重佈線層209A所期望的圖案將光阻圖案化。然後可使用例如鍍覆製程在光阻的經圖案化的多個開口中形成導電材料（例如，銅、鈦、或類似物）。然後可移除光阻且蝕刻晶種層，從而形成重佈線層209A。以這種方式，重佈線層209A可形成通往重佈線層104的電連接。在一些實施例中，重佈線層209A的導電材料具有介於2 μm到50 μm的範圍內的厚度，但可使用任何合適的厚度。
然後，可在重佈線層209A及絕緣層208A之上形成附加的絕緣層208B到絕緣層208F及重佈線層209B到重佈線層209F，以在重佈線結構210內提供附加布線以及電連接。絕緣層208B到絕緣層208F與重佈線層209B到重佈線層209F以交替層的形式形成，且可使用與用於絕緣層208A或重佈線層209A的製程及材料類似的製程及材料來形成。舉例來說，可在重佈線層（例如，重佈線層209A）之上形成絕緣層（例如，絕緣層208B），且然後使用合適的微影罩幕及蝕刻製程穿過絕緣層形成多個開口以暴露出下伏的重佈線層的多個部分。可在絕緣層之上形成晶種層且在晶種層的多個部分上形成導電材料，從而形成上覆的重佈線層（例如，重佈線層209B）。可重複這些步驟以形成具有合適數目及配置的絕緣層及重佈線層的重佈線結構210。作為另外一種選擇，絕緣層208B到絕緣層208F或重佈線層209B到重佈線層209F可與絕緣層208A或重佈線層209A不同地形成。絕緣層208B到絕緣層208F可被形成為各自具有介於5 μm到50 μm的範圍內的厚度，但可使用任何合適的厚度。以這種方式，可形成電連接到重佈線層104的重佈線結構210。在一些實施例中，重佈線結構210是扇出型結構。在其他實施例中，重佈線結構210可以不同于本文所述的製程來形成。
接下來，在圖6中，在重佈線層209F的多個導電特徵上形成多個通孔212。通孔212可穿過後續形成的介電層220（參見下文，圖7）為後續貼合的積體電壓調節器200（參見下文，圖10A到圖10B）與芯體基底300（參見下文，圖13）提供電連接。作為形成通孔212的實例，在絕緣層208F及重佈線層209F上形成光阻且將光阻圖案化。光阻可透過旋轉塗布或類似製程來形成且可暴露於光以進行圖案化。光阻的圖案對應于導通孔。所述圖案化形成穿過光阻的多個開口以暴露出晶種層。在光阻的開口中及重佈線層209F的被暴露出的部分上形成導電材料，從而形成通孔212。導電材料可透過鍍覆（例如電鍍或化學鍍）或類似製程來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁、或類似物。例如透過例如使用氧電漿或類似物進行的可接受的灰化或剝除製程來移除光阻。
在圖7中，在重佈線結構210及通孔212之上形成介電層220。介電層220對於提供上面隨後會貼合積體電壓調節器200（參見下文，圖10A到圖10B）的表面可為有用的。在一些實施例中，介電層220由聚合物（例如聚苯並噁唑（PBO）、聚醯亞胺、苯並環丁烯（BCB）、或類似物）形成。在其他實施例中，介電層220由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、摻雜硼的磷矽酸鹽玻璃（BPSG）或類似物；或者類似材料。介電層220可透過例如層壓、旋轉塗布、CVD、類似製程、或其組合等任何可接受的沉積製程來形成。
在圖8中，實行例如研磨或化學機械拋光（chemical-mechanical polish，CMP）等平坦化以透過移除介電層220的頂部部分來暴露出通孔212的頂表面。暴露出通孔212的頂表面使得後續形成的凸塊下金屬214（參見下文，圖9）及後續貼合的積體電壓調節器200能夠實體耦合及電耦合到通孔212。
接下來，在圖9中，在介電層220上形成多個凸塊下金屬214，且將凸塊下金屬214實體耦合及電耦合到通孔212中的一些通孔212。凸塊下金屬214可為後續形成的導電連接件390提供著落位置，以將重佈線結構210與芯體基底300（參見下文，圖13）耦合。凸塊下金屬214可由與通孔212相同的材料形成。
在圖10A及圖10B中，將多個積體電壓調節器200貼合到重佈線結構210上的介電層220且將積體電壓調節器200耦合到未被凸塊下金屬214覆蓋的通孔212。圖10B示出圖10A所示區1002的詳細視圖。在一些實施例中，可使用拾取及放置製程或另一種合適的製程將積體電壓調節器200放置在介電層220上，且透過倒裝晶片接合製程或其他合適的接合製程將焊料區204接合到通孔212的頂表面。透過將導電連接件202直接接合到通孔212，可在重佈線結構210及後續貼合的芯體基底300（參見下文，圖13）之間為積體電壓調節器200提供更多的空間。
可在介電層220的表面上在導電連接件202及焊料區204周圍設置底部填充膠206。底部填充膠206可透過毛細流動製程或另一種合適的沉積方法在積體電壓調節器200與介電層220之間環繞導電連接件202而形成。底部填充膠206可減少導電連接件202及焊料區204上的應力。底部填充膠206的材料可為液態環氧樹脂、可變形凝膠、矽橡膠、其組合。
在一些實施例中，可省略通孔212及介電層220的形成。然後，可將積體電壓調節器200直接實體耦合及電耦合到重佈線層209F的導電特徵。可在重佈線層209F的其他導電特徵上形成後續形成的導電連接件390（參見下文，圖13）。
圖11示出芯體基底300，隨後將芯體基底300接合到重佈線結構210（參見下文，圖13）。利用芯體基底300，具有芯體基底300在分開的製程中製造的優點。另外，由於芯體基底300是在分開的製程中形成，因此可分開對芯體基底300進行測試，從而使用已知良好的芯體基底300。舉例來說，在一些實施例中，在將芯體基底300接合到重佈線結構210之前，可單獨地或批量地對芯體基底300進行測試、確認和/或驗證。
芯體基底300可為例如有機基底、陶瓷基底、矽基底或類似基底。使用後續形成的導電連接件390（參見圖12）將芯體基底300貼合到重佈線結構210。對芯體基底300進行貼合可包括：將芯體基底300放置在重佈線結構210上，且對導電連接件390進行回焊（reflow）以將芯體基底300與重佈線結構210實體耦合及電耦合。
在貼合到重佈線結構210之前，可根據適用的製造製程對芯體基底300進行處理，以在芯體基底300中形成重佈線結構。舉例來說，芯體基底300包括芯體310。芯體310可由以下材料的一個或多個層形成：玻璃纖維、樹脂、填料、預浸料、環氧樹脂、二氧化矽填料、味之素構成膜（Ajinomoto Build- up Film，ABF）、聚醯亞胺、模制化合物、其它材料、和/或其組合。舉例來說，在一些實施例中，兩層材料構成芯體310。芯體310可由有機材料和/或無機材料形成。在一些實施例中，芯體310包括嵌置在內部的一個或多個被動元件（未示出）。芯體310可包含其他材料或元件。形成延伸穿過芯體310的多個導通孔320。在一些實施例中，導通孔320包含導電材料320A，例如銅、銅合金或其他導體，且可包括阻擋層（未示出）、襯墊（未示出）、晶種層（未示出）、和/或填充材料320B。導通孔320提供從芯體310的一個側到芯體310的另一側的垂直電連接。舉例來說，導通孔320中的一些導通孔320耦合在位於芯體310的一個側處的導電特徵與位於芯體310的相對的側處的導電特徵之間。作為實例，可使用鑽孔製程、微影、雷射製程或其他方法來形成導通孔320的多個孔洞，且然後利用導電材料填充或鍍覆導通孔320的孔洞。在一些實施例中，導通孔320是中空導電穿孔（hollow conductive through via），所述中空導電穿孔具有填充有絕緣材料的中心。在芯體310的相對的側上形成重佈線結構340A與重佈線結構340B。重佈線結構340A與重佈線結構340B透過導通孔320電耦合，導通孔320可承載扇入/扇出型電訊號。
重佈線結構340A及重佈線結構340B各自包括由ABF、預浸料、或類似物形成的多個介電層以及多個金屬化圖案。每一相應的金屬化圖案具有位於相應的介電層的主表面上且沿著所述主表面延伸的多個線部分，且具有延伸穿過相應的介電層的多個通孔部分。在一些實施例中，相應的介電層具有介於5 μm到50 μm的範圍內的厚度，且相應的金屬化圖案具有介於2 μm到50 μm的範圍內的厚度，但可使用任何合適的厚度。重佈線結構340A及重佈線結構340B各自分別包括：多個凸塊下金屬（UBM）330A及多個凸塊下金屬330B，用於外部連接；以及阻焊劑350A及阻焊劑350B，用於保護重佈線結構340A及重佈線結構340B的多個特徵。重佈線結構340A隨後可透過凸塊下金屬330A利用導電連接件390貼合到重佈線結構210，如以下圖13中所示。與圖11中所示相比，在重佈線結構340A及重佈線結構340B中可形成更多或更少的介電層及金屬化圖案。
芯體基底300可包括主動元件及被動元件（未示出），或者可不具有主動元件、被動元件中的任一者或兩者。可使用各種各樣的元件，例如電晶體、電容器、電阻器、電感器、這些元件組合、及類似物。可使用任何合適的方法來形成元件。
阻焊層350A可包括直接形成在重佈線結構340A的不存在凸塊下金屬330A的區域之上的區352。隨後可移除這些區352以形成開口360（參見下文，圖12），以在將芯體基底300貼合到重佈線結構210時容納積體電壓調節器200。
在圖12中，移除阻焊劑350A的區352以形成開口360，且在凸塊下金屬330A上形成多個導電連接件390。在一些實施例中，阻焊劑350A包括可光可圖案化的絕緣材料（例如聚苯並噁唑（PBO）、聚醯亞胺（PI）、苯並環丁烯（BCB）、或類似物）的一個或多個層，且可使用旋轉塗布製程或類似製程來形成。此種可光可圖案化的絕緣材料可使用與光阻材料類似的微影方法進行圖案化，以移除區352且形成開口360。然而，可使用任何合適的方法來形成開口360。在一些實施例中，導電材料（例如，如凸塊下金屬330的銅）的一部分存在于區352中且也透過合適的製程（例如蝕刻）來移除。
可使用導電連接件390將芯體基底300A及芯體基底300B接合到重佈線結構210，如以下圖13中所示。可首先在芯體基底300A及芯體基底300B中的任一者上，或者在重佈線結構210（參見上文，圖9）的凸塊下金屬214上形成導電連接件390，且然後對導電連接件390進行回焊以完成接合。舉例來說，在圖12中所示的實施例中，以介於100 μm到1500 μm的範圍內的節距在頂部的重佈線結構（如重佈線結構340A）的凸塊下金屬330A上形成多個導電連接件390。導電連接件390可為球柵陣列（ball grid array，BGA）連接件、焊料球、金屬柱、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、微凸塊、無電鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）形成的凸塊、或類似物。導電連接件390可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料、或其組合等導電材料。此種導電連接件390的積體可為半導體元件（例如積體被動元件（integrated passive device，IPD）晶片、積體電壓調節器（IVR）、主動晶片以及其他電子元件）的放置提供靈活性，以實施系統晶片類型的封裝組件，因此降低製造複雜性。此種實施例同樣也可為各種其他封裝配置提供更大的靈活性。
在一些實施例中，導電連接件390透過利用蒸鍍、電鍍、印刷、焊料轉移、植球、或類似製程初始地形成焊料層來形成。一旦已在結構上形成焊料層，便可實行回焊，以便將材料成形為期望的凸塊形狀。在另一實施例中，導電連接件390包括透過濺鍍、印刷、電鍍、化學鍍、CVD或類似製程形成的金屬柱（例如銅柱）。金屬柱可不含有焊料且具有實質上垂直的側壁。在一些實施例中，在金屬柱的頂部上形成金屬頂蓋層。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似物、或其組合，且可透過鍍覆製程來形成。
在圖13中，分別在第一封裝區101A及第二封裝區101B中將芯體基底300A及芯體基底300B接合到重佈線結構210（參見上文，圖10A），且在各種元件上及周圍形成包封體520。在一些實施例中，可使用拾取及放置製程或另一種合適的製程將芯體基底300A及芯體基底300B放置在重佈線結構210上，且導電連接件390透過倒裝晶片接合製程或其他合適的接合製程進行接合。在一些實施例中，對導電連接件390進行回焊，以透過凸塊下金屬214將芯體基底300A及芯體基底300B貼合到重佈線結構210。導電連接件390透過重佈線結構210將芯體基底300A及芯體基底300B電耦合和/或實體耦合到後續貼合的積體電路封裝110（參見下文，圖18）。導電連接件390在回焊之前可具有形成在其上的環氧焊劑（未示出），在將芯體基底300A及芯體基底300B貼合到重佈線結構210之後，環氧焊劑的環氧部分中的至少一些保留下來。
可將積體電壓調節器200裝配到芯體基底300A及芯體基底300B中的開口360中，以便裝配在重佈線結構210與芯體基底300A及芯體基底300B之間，從而改善後續貼合的積體電路封裝110（參見下文，圖18）的電源完整性。
仍然參照圖13，透過在各種元件上及周圍形成包封體520來實行包封。在所述形成之後，包封體520環繞芯體基底300A及芯體基底300B，包括環繞導電連接件390、積體電壓調節器200、及介電層220的上部暴露表面。包封體520可由模制化合物、環氧樹脂、底部填充膠、模制底部填充膠、類似物、或其組合來形成或包含模制化合物、環氧樹脂、底部填充膠、模制底部填充膠、類似物、或其組合，且可透過壓縮模制、轉移模制或類似製程來施加。可以液體或半液體形式施加包封體520，且然後隨後將包封體520固化。包封體520可形成在各種元件之上，從而使得芯體基底300A及芯體基底300B被掩埋或覆蓋。積體電壓調節器200的側壁及積體電壓調節器200的與重佈線結構210相對的底表面可被包封體520覆蓋。
進一步參照圖13，如果需要，可對包封體520實行執行平坦化製程，以暴露出芯體基底300A及芯體基底300B的凸塊下金屬330B。在製程變化內在平坦化製程之後，包封體520的最頂部表面與凸塊下金屬330B的最頂部表面為平整的（例如，平坦的）。平面化製程可為例如化學機械拋光（CMP）、研磨製程、或類似製程。在一些實施例中，例如如果凸塊下金屬330B已被暴露出，則可省略平坦化。可使用其他製程來實現類似的結果。舉例來說，在形成包封體520之前，可在凸塊下金屬330B之上形成電介質或鈍化層（dielectric or passivation layer）。在這種情況下，可在後續步驟中將電介質或鈍化層圖案化，以暴露出凸塊下金屬330B的部分。
在圖14中，實行載體基底剝離，以將載體基底102從包括芯體基底300A及300B以及重佈線結構210以及其他結構的先前闡述步驟的所得積層分離（或“剝離”）。根據一些實施例，所述剝離包括將例如雷射或UV光等光投射在載體基底102（參見上文，圖3）的釋放層上，從而使得釋放層在光的熱量下分解，且可移除載體基底102。然後將所述結構翻轉並放置在另一載體基底802及釋放層（未示出）上。
仍然參照圖14，在重佈線結構210的絕緣層103中形成暴露出接觸焊盤104A的多個開口240。開口240可透過蝕刻、例如雷射鑽孔、機械鑽孔等鑽孔製程、或類似製程來形成。圖案化形成暴露出接觸焊盤104A的開口240。可透過可接受的製程進行圖案化，例如當絕緣層103是感光性材料時，透過將絕緣層103暴露於光及顯影來進行圖案化，或者當使用例如氧化矽、氮化矽或類似物等非感光性材料時，透過使用例如非等向性蝕刻進行蝕刻來進行圖案化。
可使用多個導電連接件170將重佈線結構210接合到積體電路封裝110（參見下文，圖18），且可首先在積體電路封裝110或重佈線結構210中的任一者上形成導電連接件170，且然後對導電連接件170進行回焊以完成接合。舉例來說，在圖15中所示的實施例中，首先在開口240（參見上文，圖14）中形成耦合到被暴露出的接觸焊盤104A的導電連接件170。導電連接件170可為球柵陣列（BGA）連接件、焊料球（如圖所示）、金屬柱、受控塌陷晶片連接（C4）凸塊、微凸塊、無電鍍鎳鈀浸金技術（ENEPIG）形成的凸塊、或類似物。導電連接件170可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料、或其組合等導電材料。在一些實施例中，導電連接件170透過利用蒸鍍、電鍍、印刷、焊料轉移、植球、或類似製程初始地形成焊料層來形成。一旦已在結構上形成焊料層，便可實行回焊，以便將材料成形為期望的凸塊形狀。在另一實施例中，導電連接件170包括透過濺鍍、印刷、電鍍、化學鍍、CVD或類似製程形成的金屬柱（例如銅柱）。金屬柱可不含有焊料且具有實質上垂直的側壁。在一些實施例中，在金屬柱的頂部上形成金屬頂蓋層。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似物、或其組合，且可透過鍍覆製程來形成。
如上所述，重佈線結構210可更大且包括多個封裝區，例如第一封裝區101A及第二封裝區101B。舉例來說，圖16示出如以上圖15中所示的重佈線結構210，其包括具有多個封裝區的圓形形狀的晶圓。在所示實施例中，晶圓上包括四個封裝區101A、101B、101C及101D，從而使得能夠在單個晶圓上製造四個最終封裝組件且稍後將所述四個最終封裝組件單體化。在其他實施例中，可在單個晶圓上利用更少或更多的封裝區。製程中的後續步驟使用載體基底802上的重佈線結構210作為基礎，在此基礎上繼續以下所進一步詳細闡述的製造製程。如以下所進一步詳細闡述，透過沿著線401且圍著封裝區101A、101B、101C及101D的外邊緣進行鋸切來將各個封裝區單體化。
圖17示出使用具有多個封裝區的面板形式（panel form）製造製程進行重佈線結構210的製造。在所示實施例中，在晶圓上包括九個封裝區101A到101I，從而使得能夠在單個晶圓或面板上製造九個最終封裝組件。在其他實施例中，可在單個晶圓或面板上利用更少或更多的封裝區。製程中的後續步驟使用載體基底802上的重佈線結構210作為基礎，在此基礎上繼續以下所進一步詳細闡述的製造製程。如以下所進一步詳細闡述，透過沿著線402且圍著封裝區101A到101I的周邊進行鋸切來將各個封裝區單體化。
在圖18中，透過沿著切割道區（例如，在第一封裝區101A與第二封裝區101B之間）進行鋸切來實行單體化製程，且將積體電路封裝110貼合到重佈線結構210。所述鋸切將第一封裝區101A從相鄰的封裝區單體化出來，以形成多個經單體化封裝組件100。如以上在圖15中所示，利用包封體520覆蓋芯體基底300A及芯體基底300B的側壁，由此在單體化期間及之後保護芯體基底300A及芯體基底300B的側壁。包封體520在芯體基底300的側壁上可具有介於0 μm到300 μm的範圍內的厚度。
仍然參照圖18，可透過導電連接件170將積體電路封裝110貼合到重佈線結構210。導電連接件170將積體電路封裝110貼合到重佈線結構210的接觸焊盤104A。對積體電路封裝110進行貼合可包括：將積體電路封裝110放置在導電連接件170上，且對導電連接件170進行回焊以將積體電路封裝110與重佈線結構210實體耦合及電耦合。積體電路封裝110可包括邏輯晶粒112、用於與邏輯晶粒112進行接合（interfacing）的一個或多個I/O晶粒114以及重佈線結構116，重佈線結構116在例如邏輯晶粒112與I/O晶粒114之間提供電路徑及電連接，以及提供從積體電路封裝110到導電連接件170的連接。積體電路封裝110中包括的晶粒的數目、類型及排列不受限制，且在不同的實施例中可利用其他替代的晶粒及排列。透過重複上述步驟可包括多個積體電路封裝，結合金屬化特徵，以提供通往所述多個積體電路封裝的電連接。
在一些實施例中，形成環繞導電連接件170及積體電路封裝110的底部填充膠195。底部填充膠195可減少應力且保護由導電連接件170的回焊形成的多個接頭（joint）。底部填充膠195可在積體電路封裝110被貼合之後透過毛細流動製程來形成，或者可透過合適的沉積方法來形成。在一些實施例中，在多個相鄰元件之下形成底部填充膠195的單個層，並且可在放置在重佈線結構210的頂部上的附加元件之下和/或周圍形成又一些後續底部填充膠（未示出）。
在圖19中，在經單體化封裝組件100的頂表面上安裝保護環160，且在芯體基底300的底表面上形成多個外部連接件620。將保護環160安裝到經單體化封裝組件100的頂部，保護環160圍繞積體電路封裝110。在一些實施例中，可添加保護環160以向經單體化封裝組件100提供附加的剛性（rigidity）且保護所安裝的積體電路封裝110免受可能損壞積體電路封裝110與重佈線結構210之間的電連接或積體電路封裝110本身的實體碰撞及撞擊。
進一步參照圖19，在芯體基底300的凸塊下金屬330B上形成外部連接件620。外部連接件620可為球柵陣列（BGA）連接件、焊料球、金屬柱、受控塌陷晶片連接（C4）凸塊、微凸塊、或類似物。外部連接件620可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料、或其組合等導電材料。在一些實施例中，外部連接件620是透過利用蒸鍍、電鍍、印刷、焊料轉移、植球、或類似製程在凸塊下金屬330B上初始地形成可回焊材料層來形成。一旦已在凸塊下金屬330B上形成可回焊材料層，便可實行回焊，以將材料成形為期望的凸塊形狀。在一些實施例中，外部連接件620以介於100 μm 到1500 μm的範圍內的節距形成。
圖20示出根據一些實施例的經單體化封裝組件400的剖視圖。經單體化封裝組件400可類似於以上參照圖1及圖19所述的經單體化封裝組件100，其中相同的參考編號表示使用相同製程形成的相同元件，但其中在重佈線結構210與芯體基底300之間設置積體被動元件（IPD）晶片500來取代積體電壓調節器200。儘管示出兩個IPD晶片500，但可在重佈線結構210與芯體基底300之間設置任何合適數目的IPD晶片500。在一些實施例中，IPD晶片500具有介於20 μm到500 μm的範圍內的厚度，且IPD晶片500的底側具有介於2 mm 2到30 mm 2的範圍內的面積。在一些實施例中，經單體化封裝組件100的通孔212及介電層220被省略，且IPD晶片500及導電連接件390直接實體耦合及電耦合到重佈線結構210的底側上的導電特徵。
經單體化封裝組件400的重佈線結構210與芯體基底300可隔開介於20 μm到600 μm的範圍內的距離D3，此可能因具有足夠的空間來裝配IPD晶片500而是有利的。小於20 μm的距離D3可能因無提供足夠的空間來裝配IPD晶片500而是不利的。大於600 μm的距離D3可能是不利的，因為它可能導致重佈線結構210與芯體基底300之間的連接變差（其中導電連接件390中具有更高的電阻），此可能降低裝置效能。
如圖所示，出於例示目的，貼合到重佈線結構210的頂表面的積體電路封裝410包括CPU或GPU 412及兩個記憶體晶粒414。在一些實施例中，如根據圖20所示，經單體化封裝組件400不包括保護環160（參見上文，圖1）。在其他實施例中，保護環160貼合到重佈線結構210，如以上圖1中所示。
實施例可提供多個優點。可在SoIS封裝中在重佈線結構與芯體基底之間設置例如積體電壓調節器（IVR）或者積體被動元件（IPD）晶片等晶片。積體電壓調節器可向重佈線結構上的積體電路封裝供應電力及調節電力。與積體電路封裝相對地將積體電壓調節器貼合到重佈線結構，可在積體電壓調節器與積體電路封裝之間提供最短距離，此對於提供具有減輕的電壓降及功率降的更高效的電壓域可為有用的。此可改善積體電路封裝的電源完整性且可能夠提高工作頻率及降低電源電壓，以滿足高效能計算（HPC）要求。透過在重佈線結構與芯體基底之間封裝積體電壓調節器，可形成緊湊的系統，由於利用現有的矽製造工具及製程進行製造，因此所述系統可提供更高的SoIS良率。
根據實施例，一種半導體裝置包括：重佈線結構；積體電路封裝，貼合到所述重佈線結構的第一側；芯體基底，利用第一導電連接件及第二導電連接件耦合到所述重佈線結構的第二側，所述第二側與所述第一側相對，所述芯體基底的頂部層包含介電材料；以及晶片，設置在所述重佈線結構與所述芯體基底之間，所述晶片夾置在所述介電材料的側壁之間。在實施例中，所述半導體裝置還包括：介電層，位於所述重佈線結構的所述第二側上；以及第一通孔、第二通孔及第三通孔，延伸穿過所述介電層。在實施例中，所述晶片實體耦合及電耦合到所述第一通孔。在實施例中，所述半導體裝置還包括：第一凸塊下金屬，位於所述介電層上，所述第一凸塊下金屬實體耦合及電耦合到所述第二通孔，所述第一導電連接件實體耦合及電耦合到所述第一凸塊下金屬；以及第二凸塊下金屬，位於所述介電層上，所述第二凸塊下金屬實體耦合及電耦合到所述第三通孔，所述第二導電連接件實體耦合及電耦合到所述第二凸塊下金屬。在實施例中，在所述芯體基底與所述介電層的相對的表面之間測量的距離介於147 μm到500 μm的範圍內。在實施例中，所述半導體裝置還包括包封體，所述包封體覆蓋所述芯體基底的側壁、所述晶片的側壁、以及所述晶片的與所述重佈線結構相對的底表面。在實施例中，所述晶片是內部電壓調節器。在實施例中，所述晶片與所述積體電路封裝之間的最短距離小於0.3 mm。
根據另一實施例，一種半導體裝置包括：第一通孔及第二通孔，從重佈線結構的第一側延伸，凸塊下金屬與所述重佈線結構相對地位於所述第二通孔上；電壓調節器，實體耦合及電耦合到所述第一通孔；積體電路封裝，透過所述重佈線結構耦合到所述電壓調節器，所述積體電路封裝位於所述重佈線結構的與所述第一側相對的第二側上；以及芯體基底，利用導電連接件貼合到所述凸塊下金屬，所述芯體基底上的介電材料夾置在所述導電連接件與所述電壓調節器之間。在實施例中，所述半導體裝置還包括底部填充膠，所述底部填充膠夾置在所述電壓調節器與所述重佈線結構之間。在實施例中，所述介電材料與所述電壓調節器之間的寬度介於5 μm到200 μm的範圍內。在實施例中，所述電壓調節器具有介於20 μm到100 μm的範圍內的高度。在實施例中，所述電壓調節器的底側具有介於500 μm 2到20000 μm 2的範圍內的表面積。
根據又一實施例，一種形成半導體裝置的方法包括：在第一基底上形成重佈線結構；將晶片貼合到所述重佈線結構的第一側；在芯體基底中形成開口；將所述芯體基底貼合到所述重佈線結構的所述第一側，所述晶片夾置在所述開口的側壁之間；利用包封體包封所述芯體基底，其中所述包封體沿著所述芯體基底的側壁延伸，其中所述包封體進一步包封所述晶片；從所述第一基底移除所述重佈線結構；以及將積體電路封裝貼合到所述重佈線結構的第二側，所述第二側與所述第一側相對。在實施例中，所述方法還包括：在所述重佈線結構上形成第一通孔及第二通孔；在所述重佈線結構之上形成介電層，所述介電層覆蓋所述第一通孔及所述第二通孔；以及將所述介電層平坦化以暴露出所述第一通孔的頂表面及所述第二通孔的頂表面。在實施例中，將所述晶片貼合到所述重佈線結構的所述第一側包括：將所述晶片上的第一導電連接件實體耦合及電耦合到所述第一通孔。在實施例中，所述方法還包括：在所述晶片與所述介電層之間形成底部填充膠。在實施例中，所述方法還包括：在所述介電層上形成凸塊下金屬，所述凸塊下金屬實體耦合及電耦合到所述第二通孔。在實施例中，將所述芯體基底貼合到所述重佈線結構的所述第一側包括：在所述凸塊下金屬與所述芯體基底之間耦合第二導電連接件。在實施例中，所述方法還包括：在所述重佈線結構上安裝保護環，所述保護環圍繞所述積體電路封裝。
前文概述若干實施例的特徵，使得所屬領域中具通常知識者可更佳地理解本揭露的態樣。所屬領域中具通常知識者應瞭解，其可容易地使用本揭露作為設計或修改用於進行本文中所引入的實施例的相同目的及/或實現相同優點的其他製程及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且所屬領域中具通常知識者可在不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
100、400:經單體化封裝組件 101A:第一封裝區/封裝區 101B:第二封裝區/封裝區 101C～101I:封裝區 102、802:載體基底 103、208A～208F:絕緣層 104、209A～209F:重佈線層 104A:接觸焊盤 104B:導電線 110、410:積體電路封裝 112:邏輯晶粒 114:I/O晶粒 116、210、340、340A、340B:重佈線結構 160:保護環 170、202、390:導電連接件 195、206:底部填充膠 200:積體電壓調節器 204:焊料區 212:通孔 214、330、330A、330B:凸塊下金屬 220:介電層 240、360:開口 300、300A、300B:芯體基底 310:芯體 320:導通孔 320A:導電材料 320B:填充材料 350A、350B:阻焊劑 352、1000、1002:區 401、402:線 412:CPU或GPU 414:記憶體晶粒 500:積體被動元件晶片 520:包封體 620:外部連接件 D1:最短距離 D2、D3:距離 H1、H2、H3:高度 W1:最大寬度 W2:寬度
當結合隨附圖式閱讀時，將自以下實施方式最佳地理解本揭露的態樣。應指出，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，出於論述的清楚起見，可任意增加或減小各種特徵的尺寸。 圖1示出根據一些實施例的封裝組件的剖視圖。 圖2示出根據一些實施例的圖1所示剖視圖的一部分的詳細視圖。 圖3到圖15、圖18及圖19示出根據一些實施例的用於形成封裝組件的製程期間的中間步驟的剖視圖。 圖16示出根據一些實施例的晶圓基底上的封裝區的佈局的剖視圖與平面圖。 圖17示出根據一些實施例的面板基底上的封裝區的佈局的剖視圖與平面圖。 圖20示出根據一些實施例的封裝組件的剖視圖。
100:經單體化封裝組件
110:積體電路封裝
112:邏輯晶粒
114:I/O晶粒
116、210、340:重佈線結構
160:保護環
170、390:導電連接件
195:底部填充膠
200:積體電壓調節器
300:芯體基底
310:芯體
320:導通孔
330:凸塊下金屬
520:包封體
620:外部連接件
1000:區
D1:最短距離
H1:高度
W1:最大寬度

Claims (1)

  1. 一種半導體裝置，包括： 重佈線結構； 積體電路封裝，貼合到所述重佈線結構的第一側； 芯體基底，利用第一導電連接件及第二導電連接件耦合到所述重佈線結構的第二側，所述第二側與所述第一側相對，所述芯體基底的頂部層包含介電材料；以及 晶片，設置在所述重佈線結構與所述芯體基底之間，所述晶片夾置在所述介電材料的側壁之間。
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