TW202021000A - 半導體裝置之製造方法及半導體裝置 - Google Patents
半導體裝置之製造方法及半導體裝置 Download PDFInfo
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Abstract
本發明係關於半導體裝置製造方法,該半導體裝置製造方法包括:在上面設置有金屬配線的半導體上形成有機絕緣層,該有機絕緣層具有開口,以露出金屬配線的一部分;形成種金屬,該種金屬覆蓋該金屬配線自該開口露出的該一部分、以及有機絕緣層的開口的內側面及有機絕緣層的開口的周緣部;形成掩模,該掩模覆蓋種金屬的邊緣,且露出種金屬在開口中所形成的一部分;且藉由無電解鍍敷在自該掩模露出的種金屬上形成阻擋金屬。掩模包括有機材料或無機介電材料。
Description
本發明係關於一種半導體裝置製造方法及一種半導體裝置。
日本未審查專利公開案第2005-150578號揭示一種涉及半導體裝置的技術及一種半導體裝置的製造方法。根據日本未審查專利公開案第2005-150578號中揭示之製造方法,使用導電膜(自下至上依次包括Ti膜及Pd膜)作為金凸點(Au bump)的基膜進行再分佈(UBM:凸點底部金屬)。藉由濺射沈積Ti膜及Pd膜。當再分佈之電阻引起問題時,在Pd膜上形成Au膜,以形成具有自下至上依次堆疊的Ti、Pd、Au的再分佈結構。
日本未審查專利公開案第2007-251158號揭示一種涉及凸點形成方法的技術。根據日本未審查專利公開案第 2007-251158號中揭示的凸點形成方法,在上面形成有導電墊的基板上形成擴散阻擋膜圖案,接著形成種膜。接下來,在種膜上形成導電凸點,且用導電凸點作為蝕刻掩模來圖案化種膜。藉由乾法蝕刻在擴散阻擋膜上形成擴散阻擋膜圖案,且藉由濕法蝕刻在種膜上形成種膜圖案。
日本未審查專利公開案第2017-130527號揭示一種涉及半導體裝置的技術。在日本未審查專利公開案第2017-130527號中揭示之半導體裝置中,在半導體基板的上端面側上形成的源電極經兩種類型的鈍化膜(硬鈍化膜及鈍化膜)覆蓋。覆蓋源電極的鈍化膜各自具有開口,且形成比該開口寬的用作阻擋膜的UBM。
為了將半導體裝置以倒裝芯片的方式安裝在基板或其類似物上,可使用球柵陣列(BGA)封裝。在此類半導體裝置的配線層上形成焊料凸點(例如參見日本未審查專利公開案第2005-150578號、日本未審查專利公開案第2007-251158號及日本未審查專利公開案第2017-130527號)。為了抑制在焊料及配線層之間的金屬材料的相互擴散,在配線層及焊料凸點之間設置阻擋金屬層(UBM)。此外,在半導體區域上設置諸如聚醯亞胺的絕緣膜。
根據本發明的一個態樣的一種半導體裝置製造方法包括:在上面設置有金屬配線的半導體上形成有機絕緣層,該有機絕緣層具有開口,以露出金屬配線的一部分;形成種金屬,該種金屬覆蓋該金屬配線自該開口露出的部分、以及有機絕緣層的開口的內側面及有機絕緣層的開口的周緣部;形成掩模,該掩模覆蓋種金屬的邊緣,且露出種金屬在開口中所形成的一部分;且藉由無電解鍍敷在自掩模露出的種金屬上形成阻擋金屬。掩模包括有機材料或無機介電材料。
[本發明待解決的問題]
當在用作UBM的阻擋金屬層及絕緣膜之間的黏附性低時,出現以下問題,即由於例如當安裝焊球時產生的熱應力,阻擋金屬層易於自絕緣膜分離。特別地,當絕緣膜包含諸如聚醯亞胺的有機絕緣體時,由於在阻擋金屬層及有機絕緣體之間的熱膨脹係數的差異大,所以趨於明顯地出現上述問題。當在阻擋金屬層及絕緣膜之間產生間隙時,焊料可能侵入至該間隙中。當焊料侵入至該間隙中時,在阻擋金屬層及配線層之間的界面處易於發生斷裂,此使半導體裝置的可靠性劣化。此現象在阻擋金屬層及配線層之間的界面處發生,因此,即使當阻擋金屬層變厚時,亦不能消除該現象。
本發明的一個態樣是一種半導體裝置的製造方法,該方法包括:第一步驟,在設置有金屬配線的半導體區域的表面上形成有機絕緣層,該有機絕緣層具有開口,以露出金屬配線的一部分;第二步驟,形成種金屬層,該種金屬層覆蓋自開口露出的金屬配線的部分、有機絕緣層的開口的內側面及有機絕緣層的開口的周邊;第三步驟,形成掩模,該掩模覆蓋種金屬層的邊緣,且露出在開口中所形成的種金屬層的一部分;及第四步驟,藉由無電解鍍敷在自掩模露出的種金屬層上形成阻擋金屬層。掩模主要包含有機材料或無機介電材料。
[本發明的效果]
根據本發明的一個態樣,一種半導體裝置製造方法及一種半導體裝置使得能夠減少由焊料侵入而引起的在阻擋金屬層及配線層之間的界面處的斷裂,且提高可靠性。
[本發明的實施例的描述]
以下將參考附圖描述根據本發明的實施例的半導體裝置及其製造方法的具體實例。此外,應當理解的是,本發明不限於此等實例,而是由申請專利範圍之範疇限定,且包括與申請專利範圍等同的含義及範疇內的所有改型。在以下描述中,在附圖的描述中,相同的元件由相同的附圖標記表示,且省略多餘的解釋。
(第一實施例)
圖1是示出根據第一實施例的半導體裝置1A的平面圖。如圖1中所示,本實施例的半導體裝置1A是BGA型半導體裝置,其具有設置在半導體區域10的表面上的多個焊球17。該多個焊球17以網格圖案佈置在半導體區域10的一面上。
圖2是沿圖1中所示的II-II線截取的截面(用於焊球17的基礎結構)的放大圖。如圖2中所示,半導體裝置1A包括半導體區域10、設置在半導體區域10的表面上的金屬配線12、設置在半導體區域10的表面上的無機絕緣層11,以及有機絕緣層14。此外,半導體裝置1A包括無機絕緣層13、種金屬層15、阻擋金屬層16及焊球17。
例如,氮化物半導體裝置的半導體區域10包括由氮化鎵(GaN)製成的溝道層及由氮化鋁鎵(AlGaN)或氮化銦鋁(InAlN)製成的阻擋層。具有此類配置的半導體裝置1A構成高電子遷移率電晶體(HEMT)。注意,半導體區域10可包括用於除HEMT之外的場效應電晶體(FET)或用於任何其他半導體功能裝置的半導體層。
金屬配線12設置在無機絕緣層11上。金屬配線12連接至與半導體區域10歐姆接觸(ohmic contact)的電極(例如,源電極及汲電極)或與半導體區域10肖特基接觸(Schottky contact)的電極(例如,柵電極)。金屬配線12由諸如金(Au)的金屬製成。無機絕緣層11置於金屬配線12及半導體區域10之間。無機絕緣層11由諸如氮化矽(SiN)的矽化合物製成。金屬配線12的厚度例如在0.5μm至3.0μm的範圍中。
無機絕緣層13例如是絕緣矽化合物層,且作為一個實例是SiN層或SiO2
層。無機絕緣層13設置在整個半導體區域10上且覆蓋第一無機絕緣層11及金屬配線12。無機絕緣層13與無機絕緣層11相接觸。此外,無機絕緣層11在金屬配線12上具有開口13a,以露出金屬配線12的一部分。當在半導體區域10的厚度方向上觀察時,開口13a與焊球17重疊。無機絕緣層13的厚度例如在0.03μm至3μm的範圍中。
有機絕緣層14例如是聚醯亞胺層。有機絕緣層14設置在半導體區域10的整個表面上,且覆蓋無機絕緣層11及金屬配線12。根據本實施例,有機絕緣層14設置在無機絕緣層13上,且與無機絕緣層13相接觸。類似於無機絕緣層13,有機絕緣層14在金屬配線12上具有開口14a,以露出金屬配線12的一部分。當在半導體區域10的厚度方向上觀察時,開口14a與無機絕緣層13的開口13a對準,且與焊球17重疊。有機絕緣層14的厚度例如在1μm至6μm的範圍中。
種金屬層15是例如由諸如鈦(Ti)或鈀(Pa)的金屬製成的層。在一個實例中,種金屬層15包括Ti層及設置在Ti層上的Pd層。利用此配置,Ti層的厚度例如在0.005μm至0.1μm的範圍中,且作為一個實例具有50nm的厚度。此外,Pd層的厚度例如在0.01μm至0.5μm的範圍中,且作為一個實例具有100nm的厚度。當藉由無電解鍍敷形成阻擋金屬層16時,種金屬層15用作種金屬。此外,當阻擋金屬層16包含Ni(或NiCr)且金屬配線12包含Au時,種金屬層15防止Ni(或NiCr)及Au形成合金。
種金屬層15覆蓋金屬配線12自開口13a、14a露出的部分、無機絕緣層13的開口13a的內側面、有機絕緣層14的開口14a的內側面及有機絕緣層14在開口14a的周邊上的表面14b。根據本實施例,種金屬層15與金屬配線12自開口13a、14a露出的該部分、無機絕緣層13的開口13a的內側面、有機絕緣層14的開口14a的內側面及有機絕緣層14在開口14a的周邊上的表面14b相接觸。
阻擋金屬層16是由諸如鎳(Ni)或鎳-鉻合金(NiCr)的金屬製成的層。設置阻擋金屬層16用於防止構成焊球17的焊料及構成金屬配線12的金(Au)的相互擴散。阻擋金屬層16設置在種金屬層15上且與種金屬層15相接觸。當阻擋金屬層16是Ni層時,阻擋金屬層16的厚度例如在3μm至6μm的範圍中。
當在阻擋金屬層16的厚度方向上觀察時,阻擋金屬層16的邊緣(外邊緣)16a位於種金屬層15的邊緣(外邊緣)15a內側(比金屬層15的邊緣15a靠近開口14a定位)。換言之,當在阻擋金屬層16的厚度方向上觀察時,阻擋金屬層16設置在種金屬層15內側。阻擋金屬層16的邊緣16a不延伸超過種金屬層15的邊緣15a,使得阻擋金屬層16及有機絕緣層14不彼此接觸(彼此分離)。自種金屬層15的邊緣15a至阻擋金屬層16的邊緣16a的距離W1例如在4μm至8μm的範圍中。注意,例如,種金屬層15及阻擋金屬層16在平面圖中具有圓形形狀。
焊球17具有由諸如錫及銀的合金(Sn-Ag)的金屬製成的基本上球狀的結構。焊球17設置在阻擋金屬層16上且覆蓋整個阻擋金屬層16。焊球17可部分地與種金屬層15相接觸。
以下將描述上述半導體裝置1A的製造方法。圖3A、3B及4是示出根據半導體裝置1A的製造方法的步驟的截面圖。
首先,在基板上進行半導體區域10的外延生長。此生長是藉由例如金屬有機化學氣相沈積(MOCVD)進行的。接下來,在半導體區域10上形成電極(未示出)(例如,柵電極、源電極及汲電極)。在半導體區域10上形成具有開口的抗蝕劑掩模,用作電極材料的金屬在抗蝕劑掩模的開口中且在抗蝕劑掩模上氣相沈積,且抗蝕劑掩模上的金屬與抗蝕劑掩模一起移除(剝離),從而形成電極。
隨後,如圖3A中所示,無機絕緣層11在半導體區域10上形成。無機絕緣層11能夠藉由例如電漿CVD形成。隨後,藉由例如電鍍在無機絕緣層11上形成具有預定平面圖案的金屬配線12。此時,金屬配線12及電極藉由在無機絕緣層11中形成的開口彼此連接。
隨後,在設置有金屬配線12的半導體區域10的表面上形成無機絕緣層13及有機絕緣層14(第一步驟)。無機絕緣層13藉由例如電漿CVD形成。有機絕緣層14藉由例如在半導體區域10上旋塗有機絕緣層14的材料(例如,聚醯亞胺)而形成。接著,具有對應於開口13a、14a的開口的掩模(未示出)在有機絕緣層14上形成,且藉由掩模蝕刻有機絕緣層14,以形成開口14a。掩模的材料例如是SiN或SiO2
。藉由光刻或電子束光刻形成掩模的開口。此後,藉由開口14a蝕刻無機絕緣層13,以形成開口13a。注意,開口13a、14a可藉由使用電漿的乾法蝕刻形成。
隨後,金屬配線12自開口13a、14a露出的部分、有機絕緣層14的開口14a的內側面、無機絕緣層13的開口13a的內側面,及有機絕緣層14的開口14a的周邊經種金屬層15覆蓋(第二步驟)。與每個電極一樣,種金屬層15藉由氣相沈積及剝離形成。即,在有機絕緣層14上形成抗蝕劑掩模,該抗蝕劑掩模具有對應於種金屬層15的平面位置及平面形狀的開口。接著,用作種金屬層15的材料的金屬在抗蝕劑掩模的開口中且在抗蝕劑掩模上氣相沈積,且抗蝕劑掩模上的金屬與抗蝕劑掩模一起移除(剝離)。
隨後,在有機絕緣層14上形成掩模R(第三步驟)。掩模R在種金屬層15上具有開口Ra,且開口Ra的直徑大於開口14a且直徑小於種金屬層15。因此,當在半導體區域10的厚度方向上觀察時,開口Ra位於種金屬層15內,且掩模R圍繞開口Ra的一部分覆蓋種金屬層15的邊緣15a。掩模R的開口Ra的內側面與種金屬層15的邊緣15a之間的距離W2例如在4μm至8μm的範圍中。此外,掩模R的開口Ra露出種金屬層15在開口13a、14a中形成的一部分。
掩模R主要包含有機材料。例如,掩模R包含負性抗蝕劑。作為一個實例,掩模R由負性抗蝕劑製成。利用此類配置,負性抗蝕劑塗佈至有機絕緣層14及種金屬層15上,且除了對應於開口Ra的區域之外的區域曝光及顯影,從而僅允許與開口對應的未曝光區域Ra經移除。
隨後,如圖3B中所示,阻擋金屬層16在自掩模R的開口Ra露出的種金屬層15上形成(第四步驟)。此時,使用種金屬層15作為種金屬藉由無電解鍍敷形成阻擋金屬層16。具體地,藉由使用次磷酸鹽作為用於自催化電鍍的催化劑的無電解鍍敷(例如,自催化無電解鍍敷)形成阻擋金屬層16。使用無電解鍍敷的原因是無電解鍍敷比電鍍更可靠。
無電解鍍敷是一種在不使用外部電源的情況下應用電鍍的方法,且無電解鍍敷的實例包括使用電離趨勢的置換電鍍、使用還原劑的自催化無電解鍍敷(還原電鍍)及作為置換電鍍及還原電鍍的組合的置換還原電鍍。儘管在此處使用自催化無電解鍍敷,但可使用另一種無電解鍍敷。另一方面,電鍍是一種用於藉由利用外部電源來使電流在電極之間流動以自陰極供應電子來應用電鍍的方法。
在該步驟中,用於無電解鍍敷的種金屬(種金屬層15)的露出表面由掩模R限定。因此,阻擋金屬層16在由掩模R限定的區域內(在開口Ra內)生長。掩模R限制阻擋金屬層16的橫向生長。結果,開口Ra經阻擋金屬層16填充。
隨後,在阻擋金屬層16上形成Au層51(見圖2)。Au層51藉由例如無電解鍍敷、電鍍、氣相沈積及剝離或濺射形成。此後,如圖4中所示,掩模R經移除。在掩模R經移除之後,可用氧電漿短時間照射有機絕緣層14的表面。此允許有機絕緣層14的有機組分與氧反應以使有機絕緣層14的表面狀況更好。
此後,在阻擋金屬層16上(在Au層51上)形成焊球17(見圖2)(第五步驟)。在該步驟中,在施加焊劑之後,藉由在例如250℃下進行回流焊接(熱處理)來形成具有例如160μm直徑的焊球17。在該步驟中,與種金屬層15連續形成的Au幾乎全部擴散至焊球17中。此後,洗掉焊劑。藉由以上步驟,製造在圖1及2中所示本實施例的半導體裝置1A。
將給出藉由根據上述本實施例的半導體裝置1A的製造方法獲得的效果以及習知製造方法的問題的描述。圖12是用於根據習知方法製造的焊球17的基礎結構的放大截面圖。根據習知方法,在不利用圖3A中所示的掩模R的情況下形成阻擋金屬層16。利用此類配置,如圖12中所示,阻擋金屬層16橫向生長超過種金屬層15且到達未經種金屬層15覆蓋的有機絕緣層14。
通常,BGA型半導體裝置安裝在具有根據BGA的配線圖案的列印線路板上。在很多情況下,使用樹脂基板作為基礎形成列印線路板。另一方面,半導體裝置的基板由半導體或無機絕緣體製成。因此,列印線路板及半導體裝置的基板之間的熱膨脹係數的差異是大的,且因此在焊球17的形成期間溫度的變化、在使用環境下的環境溫度的變化及其類似因素對列印線路板及半導體裝置的基板施加應力。通常,由於半導體裝置小於列印線路板,因此假設焊球在某種程度上吸收此應力,但一些應力亦施加至半導體裝置的基板。該應力導致焊球的基礎結構自半導體裝置分離。特別地,如圖12中所示,當存在種金屬層15未置入有機絕緣層14及阻擋金屬層16之間的部分時,由於有機絕緣層14及阻擋金屬層16之間的熱膨脹係數的差異大,且有機絕緣層14及阻擋金屬層16之間的黏附性低,因此阻擋金屬層16易於自有機絕緣層14分離。注意,構成有機絕緣層14的聚醯亞胺的熱膨脹係數約為25×10-6
/℃,且構成阻擋金屬層16的Ni的熱膨脹係數在13×10-6
/℃至16×10-6
/℃的範圍中。
為了解決此類問題,根據本實施例,在半導體裝置1A的製造期間,形成覆蓋種金屬層15的邊緣15a的掩模R,且使得阻擋金屬層16僅在掩模R的開口Ra內生長。此僅允許阻擋金屬層16的縱向生長且限制阻擋金屬層16的橫向生長。因此,能夠防止阻擋金屬層16超過種金屬層15的邊緣15a而生長至有機絕緣層14上。因此,根據本實施例,能夠減少由於焊料的入侵而引起的在阻擋金屬層16及金屬配線12之間的界面處的斷裂,且繼而提高半導體裝置1A的可靠性。此外,根據本實施例,僅需要將形成及移除掩模R的步驟添加至習知製造方法,且因此能夠抑制製造步驟的數目增加。
本實施例的掩模R主要包含有機材料。亦能夠想到掩模R由諸如Cu的金屬製成,但使用有機材料形成掩模R帶來以下優點。即,當使得阻擋金屬層16更厚以進一步提高半導體裝置的可靠性時,需要對應地使掩模R更厚。與金屬相比,有機材料具有低剛性及高可撓性,使得即使當使掩模R更厚時,掩模R亦不易受環境應力的影響。
在形成阻擋金屬層16的步驟之後,可提供在阻擋金屬層16上形成焊球17的步驟。當形成焊球17時,由於回流焊接而導致存在大的溫度變化。根據本實施例的製造方法,即使在此類情況下,亦能夠防止阻擋金屬層16分離且提高半導體裝置1A的可靠性。
在形成阻擋金屬層16的步驟之後,可在無中斷的情況下提供在阻擋金屬層16上形成Au層51的步驟。此使得能夠增加阻擋金屬層16面向焊球17的表面的可潤濕性且因此易於形成焊球17。隨後的熱處理步驟將幾乎全部的Au層51擴散至焊球17中且最終使Au層51消失。
掩模R可包含負性抗蝕劑,且可在形成阻擋金屬層16的步驟之後提供移除掩模R的步驟。當使用正性抗蝕劑時,在曝光期間用光照射的部分上的抗蝕劑藉由顯影移除,而在曝光期間未用光照射的部分得以留下。不均勻的光照射可能在抗蝕劑的開口中(即,在種金屬層15上)產生殘留物。該殘留物可能降低種金屬層15及阻擋金屬層16之間的黏附性。另一方面,當使用負性抗蝕劑時,在顯影時,在曝光期間用光照射的部分上的抗蝕劑得以留下,而在曝光期間未用光照射的部分藉由顯影移除。此使得殘留物不太可能在抗蝕劑的開口中(即,在種金屬層15上)產生。因此,能夠抑制種金屬層15及阻擋金屬層16之間的黏附性的降低。
與正性抗蝕劑相比,負性抗蝕劑傾向於具有低黏度、短曝光時間及低所需曝光。因此,由於與正性抗蝕劑相比,負性抗蝕劑易於顯影,因此殘留物不太可能存在。此外,與正性抗蝕劑相比,負性抗蝕劑能夠在短時間內用移除劑容易地溶解,且因此能夠抑制半導體裝置1A的特性的變化。
將負性抗蝕劑更厚地形成允許開口的內側面易於形成為擴口形狀。當抗蝕劑的開口的內側面具有擴口形狀時,阻擋金屬層16具有梯形形狀。相反,當抗蝕劑的開口的內側面具有漸縮形狀時,阻擋金屬層16具有倒梯形形狀。在阻擋金屬層16上形成的焊球17藉由可潤濕性而結合,且因此具有倒梯形形狀的阻擋金屬層16使得焊球17難以到達阻擋金屬層16的側表面,使得結合表面更小,引起製程變化,且引起空氣進入以產生空隙。當阻擋金屬層16具有梯形形狀時,焊球17結合至阻擋金屬層16的幾乎整個表面,此消除上述不便且增加黏附性。如上所述,將抗蝕劑的開口的內側面形成為擴口形狀允許容易地改變阻擋金屬層16的形狀,且因此允許提高與焊球17的黏附強度。
阻擋金屬層16可為Ni層,且具有在3μm至6μm的範圍中的厚度。Ni及焊料不太可能相互擴散,因此Ni適合作為焊球17的基礎。此外,提供具有此類厚度的Ni層使得能夠進一步提高半導體裝置1A的可靠性。
種金屬層15可包括Ti層及設置在Ti層上的Pd層,Ti層可具有50nm的厚度,且Pd層可具有100nm的厚度。利用此配置,Ti層的存在增加在種金屬層15及金屬配線12之間的黏附性,而Pd層的存在允許容易地在阻擋金屬層16上進行無電解鍍敷。
在形成掩模R的步驟中,種金屬層15的邊緣15a及掩模R的內邊緣之間的距離W2可在4μm至8μm的範圍中。此使得能夠在移除掩模R之後確保阻擋金屬層16的邊緣16a及種金屬層15的邊緣15a之間的距離W1在4μm至8μm的範圍中,因此令人滿意地獲得本實施例的上述效果。
(第二實施例)
圖5是示出用於根據第二實施例的半導體裝置的焊球17的基礎結構的放大截面圖。注意,未示出焊球17。本實施例與上述第一實施例的不同之處在於掩模的材料。根據本實施例,提供主要包含無機介電材料的掩模18來代替第一實施例的主要包含有機材料的掩模R。在一個實例中,掩模18主要包含絕緣矽化合物。絕緣矽化合物是例如SiN或SiO2
。即使在製造半導體裝置之後,掩模18亦留在半導體裝置中。換言之,除了第一實施例的組件之外,本實施例的半導體裝置進一步包括掩模18。
掩模18在種金屬層15上具有開口18a,且開口18a的直徑大於開口14a且直徑小於種金屬層15。因此,當在半導體區域10的厚度方向上觀察時,開口18a處於種金屬層15內,且掩模18的靠近開口18a的部分覆蓋種金屬層15的邊緣15a。掩模18的開口18a的內側面及種金屬層15的邊緣15a之間的距離W3例如在4μm至8μm的範圍中。此外,掩模18的開口18a露出種金屬層15的在開口13a、14a中形成的部分。掩模18的厚度根據阻擋金屬層16的厚度確定,且例如在1.0μm至3.5μm的範圍中。
阻擋金屬層16設置在自掩模18露出的種金屬層15上。阻擋金屬層16的外側面(外邊緣16a)與掩模18的開口18a的內側面相接觸且位於種金屬層15的邊緣15a內側(比種金屬層15的邊緣15a更靠近開口14a)。換言之,當在阻擋金屬層16的厚度方向上觀察時,阻擋金屬層16設置在由掩模18限定的區域內。注意,掩模18在平面圖中具有例如環形形狀。
圖6A至圖6C是示出根據本實施例的半導體裝置製造方法的步驟的截面圖。首先,如在第一實施例中,依次形成半導體區域10、無機絕緣層11、金屬配線12、無機絕緣層13、有機絕緣層14及種金屬層15。接下來,在有機絕緣層14上形成掩模18。具體地,如圖6A中所示,首先在整個半導體區域10上形成由掩模18的構成材料製成的膜18A。接下來,藉由光刻在邊緣15a上形成抗蝕劑掩模。接著,藉由蝕刻移除自抗蝕劑掩模露出的膜18A。如圖6B中所示,此允許形成覆蓋邊緣15a的掩模18。此後,移除抗蝕劑掩模。
隨後,如圖6C中所示,在自掩模18露出的種金屬層15上形成阻擋金屬層16。此時,使用種金屬層15作為種金屬藉由無電解鍍敷形成阻擋金屬層16。在該步驟中,種金屬(種金屬層15)的用於無電解鍍敷的露出表面由掩模18限定。因此,阻擋金屬層16在由掩模18限定的區域內(在開口18a內)生長。掩模18限制阻擋金屬層16的橫向生長。結果,開口18a經阻擋金屬層16填充。隨後的步驟與第一實施例中的相同。
根據本實施例,在半導體裝置的製造期間,形成覆蓋種金屬層15的邊緣15a的掩模18,且使得阻擋金屬層16僅在掩模18的開口18a內生長。此僅允許阻擋金屬層16的縱向生長且限制阻擋金屬層16的橫向生長。因此,能夠防止阻擋金屬層16超過種金屬層15的邊緣15a而生長至有機絕緣層14上。因此,根據本實施例,亦能夠減少由於焊料的侵入而引起的在阻擋金屬層16及金屬配線12之間的界面處的斷裂,繼而提高半導體裝置1A的可靠性。
根據本實施例,與第一實施例不同,掩模18主要包含無機介電材料。該配置允許掩模18得以保留而不被移除,且因此使得能夠防止種金屬層15的邊緣15a及邊緣15a的附近露出。此繼而使得能夠抑制種金屬層15的周邊的劣化。
無機介電材料(例如,SiN)及有機材料(例如,聚醯亞胺)具有彼此相等的熱膨脹係數。此能夠減小由溫度變化而產生的應力,因此抑制掩模18自有機絕緣層14的分離,繼而使得能夠進一步提高半導體裝置1A的可靠性。注意,掩模18與阻擋金屬層16相接觸,且在阻擋金屬層16及掩模18之間的熱膨脹係數的差異大。因此,當阻擋金屬層16響應於溫度變化而反覆膨脹及收縮時,應力被施加至掩模18。然而,即使在掩模18中形成裂縫,該裂縫亦不會進一步增長,使得掩模18及有機絕緣層14之間的黏附性得以維持,且抑制焊料的侵入。
用於進一步增加在掩模18及有機絕緣層14之間的黏附性的方法的實例包括改變掩模18在厚度方向上的膜品質。即,較佳的是,掩模18與有機絕緣層14相接觸的部分的無機介電材料的密度低,且隨著與有機絕緣層14的距離增加,無機介電材料的密度逐漸增加。此類掩模18能夠藉由堆疊具有不同膜品質的複數個層或藉由在厚度方向上連續地改變膜品質來形成。
(改型)
圖7A至11B是示出在根據第一實施例的改型的半導體裝置的製造方法中所包括的步驟的圖。首先,如圖7A中所示,在半導體基板21上進行半導體層22的外延生長,以形成半導體區域10。接下來,電極23在半導體層22上形成以與半導體層22形成接觸,且電極23及半導體層22的各自的表面經鈍化膜24覆蓋。電極23例如是歐姆電極。鈍化膜24例如是SiN膜。接著,在鈍化膜24中形成開口,以露出電極23。
接下來,如圖7B中所示,塗佈聚醯亞胺層25(底層),且在聚醯亞胺層25上形成SiN層26。聚醯亞胺層25的厚度例如為1.4μm,且SiN層26的厚度例如為100nm。接著,在SiN層26上形成抗蝕劑圖案,且藉由抗蝕劑圖案蝕刻SiN層26,以形成露出聚醯亞胺層25的開口。在移除抗蝕劑圖案之後,藉由SiN層26的開口蝕刻聚醯亞胺層25,以形成露出電極23的開口。
隨後,如圖7C中所示,在電極23上形成種金屬27及金屬配線28(底層)。種金屬27具有例如515nm的厚度。金屬配線28由例如Au製成且具有例如1μm的厚度。具體地,首先,在整個半導體區域10上氣相沈積種金屬27,且當在厚度方向上觀察時,在種金屬27上形成具有開口的抗蝕劑圖案,該開口包括SiN層26的開口。之後,藉由電鍍在抗蝕劑圖案的開口中形成金屬配線28。在剝離抗蝕劑圖案之後,種金屬27自金屬配線28露出的一部分藉由蝕刻移除。之後,進行熱處理。熱處理溫度例如為350℃。由於緊接在電鍍之後的金屬處於所謂的稀疏狀態,因此熱處理使金屬恢復至正常狀態。
隨後,如圖8A中所示,依次形成SiN層29、聚醯亞胺層30(中間層)及SiN層31。聚醯亞胺層30具有例如2.0μm的厚度,且SiN層31具有例如130nm的厚度。在SiN層31上形成抗蝕劑圖案,且藉由抗蝕劑圖案蝕刻SiN層31,以形成露出聚醯亞胺層30的開口。在移除抗蝕劑圖案之後,經SiN層31的開口蝕刻聚醯亞胺層30及SiN層29,以形成露出金屬配線28的開口。
隨後,如圖8B中所示,在金屬配線28上形成種金屬32及金屬配線33(中間層)。種金屬32具有例如205nm的厚度。金屬配線33由例如Au製成且具有例如1μm的厚度。注意,用於形成種金屬32及金屬配線33的方法與用於形成上述種金屬27及金屬配線28的方法相同。
隨後,如圖8C中所示,依次形成SiN層34、聚醯亞胺層35及SiN層36。SiN層34的厚度例如為300nm,聚醯亞胺層35的厚度例如為2.0μm,且SiN層36的厚度例如為300nm。在SiN層36上形成抗蝕劑圖案,且藉由抗蝕劑圖案蝕刻SiN層36,以形成露出聚醯亞胺層35的開口。在移除抗蝕劑圖案之後,藉由SiN層36的開口蝕刻聚醯亞胺層35及SiN層34,以形成露出金屬配線33的開口。
隨後,如圖9A中所示,在金屬配線33上形成種金屬37及金屬配線38(中間層)。種金屬37具有例如205nm的厚度。金屬配線38由例如Au製成且具有例如1μm的厚度。注意,用於形成種金屬37及金屬配線38的方法與用於形成上述種金屬27及金屬配線28的方法相同。
隨後,如圖9B中所示,依次形成SiN層39、聚醯亞胺層40(中間層)及SiN層41。SiN層39的厚度例如為200nm,聚醯亞胺層40的厚度例如為2.0μm,且SiN層41的厚度例如為200nm。在SiN層41上形成抗蝕劑圖案,且藉由抗蝕劑圖案蝕刻SiN層41,以形成露出聚醯亞胺層40的開口。在移除抗蝕劑圖案之後,藉由SiN層41的開口蝕刻聚醯亞胺層40及SiN層39,以形成露出金屬配線38的開口。
隨後,如圖10A中所示,在金屬配線38上形成種金屬42及金屬配線43(頂層)。種金屬42具有例如205nm的厚度。金屬配線43由例如Au製成且具有例如2μm的厚度。注意,用於形成種金屬42及金屬配線43的方法與用於形成上述種金屬27及金屬配線28的方法相同。
隨後,如圖10B中所示,依次形成SiN層44、聚醯亞胺層45(頂層)及SiN層46。SiN層44的厚度例如為200nm,聚醯亞胺層45的厚度例如為6.0μm,且SiN層46的厚度例如為200nm。在SiN層46上形成抗蝕劑圖案,且藉由抗蝕劑圖案蝕刻SiN層46,以形成露出聚醯亞胺層45的開口。在移除抗蝕劑圖案之後,藉由SiN層46的開口蝕刻聚醯亞胺層45及SiN層44,以形成露出金屬配線43的開口。注意,根據本改型,金屬配線43對應於第一實施例的金屬配線12,SiN層44對應於第一實施例的無機絕緣層13,且聚醯亞胺層45對應於第一實施例的有機絕緣層14。
隨後,如圖11A中所示,在金屬配線43上形成種金屬層15。具體地,首先,形成抗蝕劑圖案,該抗蝕劑圖案具有開口,該開口包括有金屬配線43的露出部分。種金屬層15的金屬材料氣相沈積在抗蝕劑圖案的開口中及抗蝕劑圖案上,且抗蝕劑圖案上的金屬材料與抗蝕劑圖案一起移除(剝離)。注意,種金屬層15的組分與上述第一實施例中的相同。
隨後,如圖11B中所示,形成具有開口Ra的掩模R,且藉由無電解鍍敷在開口Ra中形成阻擋金屬層16。掩模R及阻擋金屬層16的具體形狀及構成材料與上述第一實施例中的相同。阻擋金屬層16的厚度例如在3μm至6μm的範圍中。之後,藉由無電解鍍敷在阻擋金屬層16上形成Au層51(見圖1)。Au層51的厚度例如為10nm。移除掩模R,且形成焊球17(見圖1),接著半導體裝置得以完成。
根據本發明的半導體裝置製造方法及半導體裝置不限於上述實施例,且各種其他修改是可能的。例如,根據第一實施例,已給出光致抗蝕劑作為構成限制阻擋金屬層的橫向生長的掩模的有機介電材料的實例。可使用各種其他材料作為有機介電材料。此外,根據第二實施例,絕緣矽化合物(SiN或SiO2
)已用作構成限制阻擋金屬層的橫向生長的掩模的無機介電材料的實例。可使用各種其他材料作為無機介電材料。根據上述實施例中的每一個,已給出HEMT作為半導體區域的實例,但根據本發明的製造方法不限於HEMT,且適用於設置有金屬配線及焊球的各種半導體裝置。
相關申請的交叉引用
本申請案主張2018年9月19日提交的日本申請案第JP2018-175212號之優先權,其全部內容藉由引用併入本文。
1A:半導體裝置
10:半導體區域
11:無機絕緣層
12:金屬配線
13:無機絕緣層
13a:開口
14:有機絕緣層
14a:開口
14b:表面
15a:邊緣
15:種金屬層
16:阻擋金屬層
16a:邊緣
17:焊球
18:掩模
18a:開口
18A:膜
21:半導體基板
22:半導體層
23:電極
24:鈍化膜
25:聚醯亞胺層
26:SiN層
27:種金屬
28:金屬配線
29:SiN層
30:聚醯亞胺層
31:SiN層
32:種金屬
33:金屬配線
34:SiN層
35:聚醯亞胺層
36:SiN層
37:種金屬
38:金屬配線
39:SiN層
40:聚醯亞胺層
41:SiN層
42:種金屬
43:金屬配線
44:SiN層
45:聚醯亞胺層
46:SiN層
51:Au層
藉由以下參考附圖對本發明的較佳實施例的詳細描述,將更好地理解前述及其他目的、態樣及優點,其中:
圖1是示出根據第一實施例的半導體裝置1A的平面圖;
圖2是沿圖1中所示的II-II線截取的截面(用於焊球17的基礎結構)的放大圖;
圖3A及3B是示出根據半導體裝置1A的製造方法的步驟的截面圖;
圖4是示出根據半導體裝置1A的製造方法的步驟的截面圖;
圖5是示出用於根據第二實施例的半導體裝置的焊球17的基礎結構的放大截面圖;
圖6A至6C是示出根據第二實施例的半導體裝置製造方法的步驟的截面圖;
圖7A至7C是示出根據一個改型的半導體裝置製造方法中包括的步驟的圖;
圖8A至8C是示出根據一個改型的半導體裝置製造方法中包括的步驟的圖;
圖9A及9B是示出根據一個改型的半導體裝置製造方法中包括的步驟的圖;
圖10A及10B是示出根據一個改型的半導體裝置製造方法中包括的步驟的圖;
圖11A及11B是示出根據一個改型的半導體裝置製造方法中包括的步驟的圖;且
圖12是用於根據習知方法製造的焊球17的基礎結構的放大截面圖。
1A:半導體裝置
10:半導體區域
17:焊球
Claims (19)
- 一種半導體裝置製造方法,包括: 在上面設置有金屬配線的半導體上形成有機絕緣層,該有機絕緣層具有開口,以露出該金屬配線的一部分; 形成種金屬,該種金屬覆蓋該金屬配線自該開口露出的該一部分、以及該有機絕緣層的該開口的內側面及該有機絕緣層的該開口的周緣部; 形成掩模,該掩模覆蓋該種金屬的邊緣,且露出該種金屬在該開口中所形成的一部分;且 藉由無電解鍍敷在自該掩模露出的該種金屬上形成阻擋金屬, 其中,該掩模包括有機材料或無機介電材料。
- 如請求項1之半導體裝置製造方法,進一步包括: 在形成該阻擋金屬之後,在該阻擋金屬上形成焊球。
- 如請求項2之半導體裝置製造方法,其中 該焊球在250℃下回流焊接,且 該焊球的直徑為160μm。
- 如請求項1至3中任一項之半導體裝置製造方法,進一步包括: 在形成該阻擋金屬之後,不間斷地在該阻擋金屬上形成金(Au)層, 其中,該Au層的厚度為10nm。
- 如請求項1至4中任一項之半導體裝置製造方法,進一步包括: 在形成該掩模之後,移除該掩模, 其中,該掩模包括負性抗蝕劑。
- 如請求項1至5中任一項之半導體裝置製造方法, 其中,該掩模包括絕緣矽化合物。
- 如請求項1至6中任一項之半導體裝置製造方法, 其中,該阻擋金屬是鎳(Ni)層,且該Ni層的厚度為3μm至6μm。
- 如請求項1至7中任一項之半導體裝置製造方法,其中 該種金屬包括鈦(Ti)及該鈦上的鈀(Pd),且 該鈦的厚度為50nm,且該鈀的厚度為100nm。
- 如請求項1至8中任一項之半導體裝置製造方法, 其中,在該種金屬的該邊緣及該掩模的內側邊緣之間的距離為4μm至8μm。
- 一種半導體裝置製造方法,包括: 在上面設置金屬配線的半導體上形成有機絕緣層,該有機絕緣層具有第一開口,以露出該金屬配線的一部分; 形成種金屬層,該種金屬層覆蓋該金屬配線自該第一開口露出的該一部分以及該有機絕緣層的該第一開口的內側面及周緣部; 形成掩模,該掩模覆蓋該種金屬層的邊緣及該有機絕緣層,該掩模具有第二開口,以露出該種金屬層的一部分;且 在自該掩模的該第二開口露出的該種金屬層上形成阻擋金屬層, 其中,該阻擋金屬層與該有機絕緣層相分隔。
- 如請求項10之半導體裝置製造方法,進一步包括: 在形成該阻擋金屬層之後,在該阻擋金屬層上形成焊球。
- 如請求項11之半導體裝置製造方法, 其中,藉由在250℃下進行回流焊接來形成具有160μm的直徑的該焊球。
- 如請求項10至12中任一項之半導體裝置製造方法,進一步包括: 在形成該阻擋金屬層之後,不間斷地在該阻擋金屬層上形成Au層, 其中,該Au層的厚度為10nm。
- 如請求項10至13中任一項之半導體裝置製造方法,進一步包括: 在形成該掩模之後,移除該掩模, 其中,該掩模包括負性抗蝕劑。
- 如請求項10至14中任一項之半導體裝置製造方法,其中 該掩模包括絕緣矽化合物,且 該掩模保留在該種金屬層的該邊緣上。
- 如請求項10至15中任一項之半導體裝置製造方法, 其中,該阻擋金屬層是Ni層,且該Ni層的厚度為3μm至6μm。
- 如請求項10至16中任一項之半導體裝置製造方法,其中 該種金屬層包括Ti層及該Ti層上的Pd層,且 該Ti層的厚度為50nm,且該Pd層的厚度為100nm。
- 如請求項10至17中任一項之半導體裝置製造方法, 其中,在該種金屬層的該邊緣及該掩模的內側邊緣之間的距離為4μm至8μm。
- 一種半導體裝置,包括: 半導體區域; 位於該半導體區域的表面上的金屬配線; 位於該半導體區域的該表面上的有機絕緣層,該有機絕緣層具有第一開口,以露出該金屬配線的一部分; 種金屬層,該種金屬層覆蓋該金屬配線自該第一開口露出的該一部分以及該有機絕緣層的該第一開口的內側面及周緣部; 掩模,該掩模覆蓋該種金屬層的邊緣,該掩模具有第二開口,以露出該種金屬層的一部分;及 阻擋金屬層,該阻擋金屬層位於自該掩模的該第二開口露出的該種金屬層上,該阻擋金屬層具有與該掩模的該第二開口的內側面相接觸的外側面, 其中,該掩模主要包含無機介電材料,且 其中,在平面圖中,該阻擋金屬層位於由該掩模限定的區域內。
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Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6413851B1 (en) * | 2001-06-12 | 2002-07-02 | Advanced Interconnect Technology, Ltd. | Method of fabrication of barrier cap for under bump metal |
US6605524B1 (en) * | 2001-09-10 | 2003-08-12 | Taiwan Semiconductor Manufacturing Company | Bumping process to increase bump height and to create a more robust bump structure |
US7276801B2 (en) * | 2003-09-22 | 2007-10-02 | Intel Corporation | Designs and methods for conductive bumps |
JP2005150578A (ja) | 2003-11-19 | 2005-06-09 | Renesas Technology Corp | 半導体装置及びその製造方法 |
TW200603698A (en) * | 2004-04-13 | 2006-01-16 | Unitive International Ltd | Methods of forming solder bumps on exposed metal pads and related structures |
JP4327657B2 (ja) * | 2004-05-20 | 2009-09-09 | Necエレクトロニクス株式会社 | 半導体装置 |
JP2006278551A (ja) * | 2005-03-28 | 2006-10-12 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2007095894A (ja) * | 2005-09-28 | 2007-04-12 | Fujikura Ltd | 半導体装置及びその製造方法 |
JP2007220959A (ja) * | 2006-02-17 | 2007-08-30 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US20070210450A1 (en) * | 2006-03-13 | 2007-09-13 | Jang Woo-Jin | Method of forming a bump and a connector structure having the bump |
US8314500B2 (en) * | 2006-12-28 | 2012-11-20 | Ultratech, Inc. | Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers |
US7838991B1 (en) * | 2007-02-05 | 2010-11-23 | National Semiconductor Corporation | Metallurgy for copper plated wafers |
US7964961B2 (en) * | 2007-04-12 | 2011-06-21 | Megica Corporation | Chip package |
US8039960B2 (en) * | 2007-09-21 | 2011-10-18 | Stats Chippac, Ltd. | Solder bump with inner core pillar in semiconductor package |
JP5331610B2 (ja) * | 2008-12-03 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
US8531015B2 (en) * | 2009-03-26 | 2013-09-10 | Stats Chippac, Ltd. | Semiconductor device and method of forming a thin wafer without a carrier |
CN102439719B (zh) * | 2009-05-14 | 2015-06-24 | 高通股份有限公司 | 系统级封装 |
JP2012204788A (ja) * | 2011-03-28 | 2012-10-22 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
US20130341785A1 (en) * | 2012-06-22 | 2013-12-26 | Lei Fu | Semiconductor chip with expansive underbump metallization structures |
US9142501B2 (en) * | 2013-03-14 | 2015-09-22 | International Business Machines Corporation | Under ball metallurgy (UBM) for improved electromigration |
US9978637B2 (en) * | 2013-10-11 | 2018-05-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanism for forming patterned metal pad connected to multiple through silicon vias (TSVs) |
JP2017130527A (ja) | 2016-01-19 | 2017-07-27 | 力祥半導體股▲フン▼有限公司UBIQ Semiconductor Corp. | 半導体装置 |
JP6705592B2 (ja) * | 2016-06-20 | 2020-06-03 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
US10026707B2 (en) * | 2016-09-23 | 2018-07-17 | Microchip Technology Incorportated | Wafer level package and method |
US10446504B2 (en) * | 2017-05-18 | 2019-10-15 | Xintec Inc. | Chip package and method for forming the same |
TW201930646A (zh) * | 2018-01-05 | 2019-08-01 | 頎邦科技股份有限公司 | 具凸塊結構之半導體裝置及其製造方法 |
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