TW202017180A - 積體電路裝置 - Google Patents
積體電路裝置 Download PDFInfo
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- TW202017180A TW202017180A TW108136812A TW108136812A TW202017180A TW 202017180 A TW202017180 A TW 202017180A TW 108136812 A TW108136812 A TW 108136812A TW 108136812 A TW108136812 A TW 108136812A TW 202017180 A TW202017180 A TW 202017180A
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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Abstract
此處提供具有鰭狀場效電晶體裝置的積體電路與形成積體電路的方法。在一些例子中,積體電路裝置包括基板;鰭狀物,自基板延伸;閘極,位於鰭狀物的第一側上;以及閘極間隔物,沿著閘極的側部。閘極間隔物具有沿著閘極延伸且具有第一寬度的第一部份,以及延伸於閘極上且具有第二寬度的第二部份,而第二寬度大於第一寬度。在這些例子中,閘極間隔物的第二部份包括位於閘極上的閘極間隔物層。
Description
本發明實施例關於積體電路裝置,更特別關於薄化閘極間隔物的製程。
半導體積體電路產業已經歷快速成長。在積體電路演進中,功能密度(比如單位晶片面積的內連線裝置數目)通常隨著幾何尺寸(比如採用的製作製程所產生的最小構件或線路)縮小而增加。尺寸縮小的製程通常有利於增加產能並降低相關成本。然而尺寸縮小亦增加設計與形成含有這些積體電路的裝置之複雜度。形成方法的平行進展可準確與可靠地製作複雜設計。
舉例來說,製作方法的進展使三維設計可行,比如鰭狀場效電晶體。鰭狀場效電晶體可視作一般平面裝置自基板向外突出至閘極中。例示性的鰭狀場效電晶體具有自基板向上延伸的薄鰭狀物或鰭狀結構,場效電晶體的通道區形成於垂直鰭狀物中,而閘極位於鰭狀物的通道區上(如包覆通道區)。閘極包覆鰭狀物可增加通道區與閘極之間的接觸面積,使閘極可自多側控制通道。可由多種方式利用此結構。在一些應用中,鰭狀場效電晶體可降低短通道效應、減少漏電流、並增加電流。換言之,鰭狀場效電晶體比平面裝置更快、更小、且更有效。
隨著裝置尺寸縮小,越來越難以形成及對準積體電路的結構如閘極與耦接至閘極的接點。改善形成最小構件的技術或提供額外空間以形成較大結構的進展,有增加產能、改善效能、降低變異、減少電路面積、與提供其他優點的潛力。
本發明一實施例提供之積體電路裝置,包括:基板;鰭狀物,自基板延伸;第一閘極,位於鰭狀物的第一側上;以及閘極間隔物,沿著第一閘極的側部,其中閘極間隔物具有沿著第一閘極延伸且具有第一寬度的第一部份,以及延伸於第一閘極上且具有第二寬度的第二部份,而第二寬度大於第一寬度。
本發明一實施例提供之積體電路裝置,包括:基板,具有鰭狀物;隔離介電層,位於基板上,使鰭狀物延伸高於隔離介電層;一對閘極結構,位於鰭狀物的兩側上的隔離介電層上;閘極間隔物,位於一對閘極結構之側表面上與鰭狀物上;以及層間介電層,位於隔離介電層上與鰭狀物上,其中層間介電層延伸於閘極間隔物上並沿著閘極間隔物的側部。
本發明一實施例提供之積體電路裝置的製作方法,包括:接收基板,其具有自基板延伸的鰭狀物,以及位於鰭狀物上及鰭狀物的兩側上的占位閘極;形成閘極間隔物於占位閘極的側表面上;進行閘極置換製程,以將占位閘極置換成功能閘極;以及形成額外閘極間隔物層於閘極間隔物的側表面上與功能閘極的上表面上。
下述內容提供的不同實施例或實例可實施本發明的不同結構。下述特定構件、與配置的實施例係用以簡化本發明內容而非侷限本發明。舉例來說,形成第一構件於第二構件上的敘述包含兩者直接接觸的實施例,或兩者之間隔有其他額外構件而非直接接觸的實施例。
此外,空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件,而非侷限於圖示方向。另一方面,本發明之多個實例可重複採用相同標號以求簡潔,但多種實施例及/或設置中具有相同標號的元件並不必然具有相同的對應關係。
積體電路包括越來越多的主動與被動電路裝置形成於基板或晶圓上,而鰭狀場效電晶體為一例。鰭狀場效電晶體可包含數個隆起的半導體部份(如鰭狀物),其包含源極/汲極結構與通道區,而閘極結構包覆通道區。此技術的一些例子可減少沿著閘極側部的介電閘極間隔物的厚度,以改良耦接至源極/汲極結構與閘極結構的接點之形成方法。較薄的閘極間隔物可增加接點所用的空間,以簡單製作並對準接點。此外在這些例子中,沿著閘極側部的閘極間隔物的部份,比可形成接點處的閘極上的閘極間隔物的部份薄。閘極間隔物的較薄部份可提供較寬的凹陷以形成閘極於其中,其可易於製作並對準閘極。較寬的閘極結構亦可降低不利的短通道效應。閘極間隔物的較厚部份額外提供接點之間的隔離,可降低時間相關的閘極氧化物擊穿,並提供其他優點。
此技術可完全省略鰭狀物上的閘極結構,並保留沿著鰭狀物側部的閘極結構,以避免形成閘極結構於閘極間隔物較厚的區域中。相反地,形成導電蓋於電性耦接至鰭狀物兩側上的閘極結構的鰭狀物上。這可降低閘極結構中的導電材料量。除了簡化閘極,亦可降低閘極電容並增加裝置切換速度。這些優點僅用以舉例,且任何特定實施例不必具有特定優點。
本發明的例子提供含有多個鰭狀場效電晶體與相關的閘極結構之積體電路。在此考量下,圖1A與1B係本發明多種實施例中,製作具有鰭狀場效電晶體的閘極結構之工件200的方法100之流程圖。在方法100之前、之中、與之後可提供額外步驟,且方法100的其他實施例可置換或省略一些所述步驟。圖2係本發明多種實施例中,以方法100製作的工件200之透視圖。圖3至11、13、15、17、19、21、23、25、27、與29係本發明多種實施例中,工件200沿著切穿鰭狀物的鰭狀物長度方向(如平面202)的剖視圖。圖12、14、16、18、20、22、24、26、28、與30係本發明多種實施例中,工件200沿著切穿隔離結構的鰭狀物長度方向(如平面204)的剖視圖。圖31係本發明多種實施例中,工件200沿著切穿閘極結構的閘極長度方向之剖視圖。
如圖1A的步驟102與圖2所示,接收工件200。工件200包括裝置將形成其上的基板208。在多種例子中,基板208包含半導體元素(單一元素)如結晶結構的矽或鍺、半導體化合物(如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦)、半導體合金(如矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、及/或磷砷化鎵銦)、非半導體材料(如鈉鈣玻璃、熔融氧化矽、熔融石英、及/或氟化鈣)、及/或上述之組合。
基板208可具有一致的組成或包含多種層狀物,且可選擇性蝕刻一些基板以形成鰭狀物。層狀物可具有類似或不同組成。在多種實施例中,一些基板層具有不一致的組成,可誘發裝置應力以調整裝置效能。層狀基板的例子包含絕緣層上矽基板208。在一些例子中,基板208的一層可包含絕緣層如半導體氧化物、半導體氮化物、半導體氮氧化物、半導體碳化物、及/或其他合適的絕緣材料。
摻雜區如井區可形成於基板208上。在此考量下,基板208的一些部份可摻雜p型摻質如硼、二氟化硼、或銦,而基板208的其他部份可摻雜n型摻質如磷或砷,及/或含有上述之組合的其他合適摻質。
在一些實施例中,形成於基板208上的裝置延伸出基板208。舉例來說,鰭狀場效電晶體及/或其他非平面裝置可形成在位於基板208上的鰭狀物210上。鰭狀物210可表示任何隆起結構,並包含鰭狀場效電晶體的鰭狀物210,以及形成其他隆起的主動與被動裝置於基板上208上所用的鰭狀物210。鰭狀物210的組成可與基板208的組成類似或不同。舉例來說,一些實施例的基板208主要可包含矽,而鰭狀物210包含的一或多層主要為鍺或矽鍺半導體。在一些實施例中,基板208包含矽鍺半導體,而鰭狀物210包含的矽鍺半導體之矽鍺比例不同於基板208的矽鍺比例。
鰭狀物210的形成方法可為蝕刻基板208的部份、沉積多種層狀物於基板上並蝕刻層狀物、及/或其他合適技術。舉例來說,可採用一或多道光微影製程圖案化鰭狀物210,包括雙重圖案化或多重圖案化製程。一般而言,雙重圖案化或多重圖案化製程結合光微影與自對準製程,其產生的圖案間距小於採用單一的直接光微影製程所產生的圖案間距。舉例來說,一實施例形成犧牲層於鰭狀物210與一或多個鰭狀物頂部的硬遮罩212上。採用光微影製程圖案化犧牲層。採用自對準製程沿著圖案化的犧牲層之側部形成間隔物。接著移除犧牲層,並採用保留的間隔物圖案化鰭狀物210,比如移除間隔物未覆蓋的鰭狀物頂部的硬遮罩212與基板208,以保留鰭狀物210。
鰭狀物頂部的硬遮罩212可用於控制定義鰭狀物210的蝕刻製程,且可在後續製程實保護鰭狀物210。綜上所述,可選擇鰭狀物頂部的硬遮罩212以與鰭狀物210的材料之間具有蝕刻選擇性。鰭狀物頂部的硬遮罩212可包含介電材料如半導體氧化物、半導體氮化物、半導體氮氧化物、半導體碳化物、半導體碳氮化物、半導體碳氮氧化物、及/或金屬氧化物。在一些例子中,鰭狀物頂部的硬遮罩212包含氧化矽或氮化矽。鰭狀物頂部的硬遮罩212可具有任何合適厚度。在多種例子中,鰭狀物頂部的硬遮罩212的厚度介於約1nm至約10nm之間。
工件200亦可包含隔離介電層216於鰭狀物210之間的基板208上,以形成隔離結構(如淺溝槽隔離結構)。隔離介電層216可包含介電材料如半導體氧化物、半導體氮化物、半導體氮氧化物、半導體碳化物、半導體碳氮化物、半導體碳氮氧化物、金屬氧化物、或類似物。在一些例子中,隔離介電層216包括不同介電材料的多個子層。隔離介電層216的形成方法可為任何合適製程。在一些例子中,隔離介電層216的沉積方法採用原子層沉積、電漿輔助原子層沉積、化學氣相沉積、電漿輔助化學氣相沉積、高密度電漿化學氣相沉積、及/或其他合適沉積製程。在沉積之後,可回蝕刻隔離介電層216,使鰭狀物210的最上側部份凸起高於隔離介電層。在多種例子中,鰭狀物210與鰭狀物頂部的硬遮罩212延伸高於隔離介電層216的最頂部表面的距離,介於約100nm至約500nm之間。
輸入/輸出氧化物層214可位於鰭狀物頂部的硬遮罩212上與鰭狀物210的側部上。輸入/輸出氧化物層214可包含介電材料如半導體氧化物、半導體氮氧化物、半導體碳氮氧化物、及/或金屬氧化物。輸入/輸出氧化物層214的形成方法可為任何合適製程,包括原子層沉積、電漿輔助原子層沉積、化學氣相沉積、電漿輔助化學氣相沉積、高密度電漿化學氣相沉積、熱成長、及/或其他合適技術。在多種例子中,輸入/輸出氧化物層214的沉積厚度介於約1nm至約5nm之間。
工件亦可包含占位閘極218形成於鰭狀物210的通道區上並圍繞通道區。當功能閘極的材料對製作製程敏感或難以圖案化時,一些製作製程可採用多晶矽、介電層、及/或其他彈性材料的占位閘極218。在閘極後製製程中,之後移除占位閘極,並取代為功能閘極的單元(如閘極、閘極介電層、與界面層等等)。在此方式中,占位閘極218保留區域以用於後續形成的功能閘極。
占位閘極218可包含任何合適材料,比如多晶矽、一或多種介電材料(如半導體氧化物、半導體氮化物、半導體氮氧化物、半導體碳化物、半導體碳氮化物、半導體碳氮氧化物、或類似物)、及/或其他合適材料。占位閘極218的材料之形成方法可為任何合適製程,包含化學氣相沉積、電漿輔助化學氣相沉積、高密度電漿化學氣相沉積、物理氣相沉積、原子層沉積、電漿輔助原子層沉積、及/或其他合適沉積製程。在一些例子中,毯覆性地沉積占位閘極218的材料,並選擇性地蝕刻移除部份材料以保留占位閘極218於鰭狀物210的通道區上。為助圖案化,可在蝕刻之前形成介電材料或其他合適材料的一或多個閘極硬遮罩層(如閘極硬遮罩層220與222)於占位閘極材料的頂部上。閘極硬遮罩層220與222可具有類似或不同的組成。在一例中,閘極硬遮罩層220包括半導體氮化物,而閘極硬遮罩層222包括半導體氧化物。
占位閘極218垂直於鰭狀物210,並延伸高於鰭狀物210的頂部(包含任何鰭狀物頂部的硬遮罩212)一段距離223。在鰭狀物210與鰭狀物頂部的硬遮罩212延伸高於隔離介電層216的距離介於約100nm至約500nm的例子中,占位閘極218自鰭狀物頂部的硬遮罩212的最上側表面延伸的距離介於約50nm至約150nm之間。
如圖1A的步驟104與圖3所示,形成閘極間隔物302於占位閘極218的側表面與任何閘極硬遮罩層220及222上。在多種例子中,閘極間隔物302包括一或多層的合適材料如介電材料(例如半導體氧化物、半導體氮化物、半導體氮氧化物、半導體碳化物、半導體碳氮氧化物、或類似物)。在這些例子中,閘極間隔物302各自包含低介電常數的介電材料(如碳氮化矽、碳氧化矽、碳氮氧化矽、或類似物)之第一間隔物層304,以及相同或其他的低介電常數的介電材料之第二間隔物層306。在此例中,第一間隔物層304的厚度介於約1nm至約5nm之間,而第二間隔物層306的厚度介於約1nm至約5nm之間。
第一間隔物層304與第二間隔物層306的形成方法可採用任何合適的沉積技術如原子層沉積、化學氣相沉積、高密度電漿化學氣相沉積、或類似方法。在一例中,第一間隔物層304與第二間隔物層306以順應性的技術沉積於占位閘極218、鰭狀物210、與隔離介電層216上。接著自閘極硬遮罩層220與222、鰭狀物210、與隔離介電層216的水平表面選擇性蝕刻移除第一間隔物層304與第二間隔物層306,並保留第一間隔物層304與第二間隔物層306於占位閘極218的垂直表面上。保留的材料可定義閘極間隔物302。蝕刻製程可採用任何合適的蝕刻方法,比如非等相乾蝕刻、濕蝕刻、反應性離子蝕刻、及/或其他蝕刻方法,且可採用任何合適的蝕刻劑。蝕刻方法與蝕刻劑可隨第一閘極間隔物層304與第二間隔物層306等蝕刻目標的特定材料而改變,並最小化非預期地蝕刻非蝕刻目標的材料。
如圖1A的步驟106與圖4所示,形成源極/汲極結構402於占位閘極218的兩側上。源極/汲極結構402的形成方法可為使鰭狀物210的一部份凹陷,並採用化學氣相沉積技術(如氣相磊晶及/或超高真空化學氣相沉積)、分子束磊晶、及/或其他合適製程沉積材料於凹陷中。磊晶製程可採用氣態及/或液態前驅物,其與鰭狀物210的保留部份之組成(如矽或矽鍺)作用,以形成源極/汲極結構402。源極/汲極結構402的半導體組成可與鰭狀物210的保留部份類似或不同。舉例來說,可形成含矽的源極/汲極結構402於含矽鍺的鰭狀物210上,反之亦然。當源極/汲極結構402與鰭狀物210包含超過一種半導體時,兩者之半導體元素比例可實質上類似或不同。
可原位摻雜源極/汲極結構402使其包含p型摻質如硼、二氟化硼、或銦、n型摻質如磷或砷、及/或包含上述之組合的其他合適摻質。在額外實施例或其他實施例中,在形成源極/汲極結構402之後採用佈植製程(如接面佈植製程)摻雜源極/汲極結構402。關於摻質的具體種類,可摻雜源極/汲極結構402使其與鰭狀物210的其餘部份具有相反型態。對p型通道裝置而言,鰭狀物210摻雜n型摻質而源極/汲極結構402摻雜p型摻質,且對n型通道裝置而言則相反。一旦將摻質導入源極/汲極結構402,可進行摻質活化製程(如快速熱退火及/或雷射退火製程)以活化摻質。
如圖1A的步驟108與圖5所示,進行蝕刻製程以薄化閘極間隔物302的層狀物或最外層(如第二間隔物層306)。薄化閘極間隔物302可提供接點所用的額外空間,使接點沿著閘極間隔物302的側部延伸並接觸源極/汲極結構402。此外外空間可加寬接點溝槽與接點。由於窄的接點溝槽更難以一致地填入接點材料,薄化閘極間隔物302可改善沉積的接點材料之填入品質。較寬的接點亦可降低接點電阻,並在沉積後續材料時容許較多層疊誤差。在這些方式與其他方式中,薄化的閘極間隔物302可提供更可靠的電路裝置。
製程可採用任何合適的蝕刻技術,包括乾蝕刻、濕蝕刻、反應性離子蝕刻、或其他合適技術。在一些例子中,採用標準清潔液1 (氫氧化銨、過氧化氫、與水的混合物)及/或標準清潔液2 (氯化氫、過氧化氫、與水的混合物)的濕蝕刻薄化閘極間隔物302。製程可移除任何合適的厚度502。在多種實施例中,移除約1nm至約2nm的外側的第二間隔物層306,而保留的閘極間隔物302的總寬度介於約1nm至約10nm之間。在一些例子中,薄化技術可保留閘極間隔物302的最底部不被蝕刻,使閘極間隔物302的最底部比最頂部厚約1nm至約2nm。
如圖1A的步驟110與圖6所示,底接點蝕刻停止層602形成於源極/汲極結構402上,並沿著占位閘極218及閘極硬遮罩層220與222的頂部與側部。底接點蝕刻停止層602的形成方法可為任何合適技術,包括原子層沉積、電漿輔助原子層沉積、化學氣相沉積、電漿輔助化學氣相沉積、及/或高密度電漿化學氣相沉積,且可形成為任何合適厚度。在一些例子中,底接點蝕刻停止層602的厚度介於約1nm至約10nm之間。底接點蝕刻停止層602可包含介電層(如半導體氧化物、半導體氮化物、半導體氮氧化物、半導體碳化物、或類似物)及/或其他合適材料。在多種實施例中,底接點蝕刻停止層602包括氮化矽、氧化矽、氮氧化矽、及/或碳化矽。
如圖1A的步驟112與圖7所示,形成層間介電層702於工件200上。層間介電層702作為絕緣層以支撐並隔離電性多層內連線結構的導電線路。多層內連線結構可電性內連線工件200的單元,比如源極/汲極結構402與功能閘極。層間介電層702的形成方法可為任何合適製程,包括化學氣相沉積、物理氣相沉積、旋轉塗佈沉積、及/或其他合適製程。層間介電層702可包含介電材料(如半導體氧化物、半導體氮化物、半導體氮氧化物、半導體碳化物、或類似物)、旋轉塗佈玻璃、摻雜氟的矽酸鹽玻璃、磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、Black Diamond® (加州Santa Clara的Applied Materials)、乾凝膠、氣膠、非晶氟化碳、聚對二甲苯、苯并環丁烯、SiLK® (密西根州Midland的Dow Chemical)、及/或上述之組合。
如圖8所示,在沉積層間介電層702之後可進行化學機械研磨製程,以平坦化層間介電層702、底接點蝕刻停止層602、閘極間隔物302、與占位閘極218。具體而言,化學機械研磨製程可自占位閘極218的頂部移除閘極硬遮罩層220與222。
如圖1A的步驟114與圖9所示,移除保留的占位閘極218。移除占位閘極218可形成凹陷於閘極間隔物302之間,且凹陷中將形成功能閘極。占位閘極218的移除方法可採用多種蝕刻技術之一或重複進行蝕刻技術,比如乾蝕刻、濕蝕刻、反應性離子蝕刻、或類似方法,其各自設置以選擇性地蝕刻占位閘極218的材料組或特定材料。
一般而言,技術與蝕刻劑可設置為避免明顯蝕刻周圍材料(如層間介電層702與閘極間隔物302)。然而在一些例子中,蝕刻可設置微薄化閘極間隔物302的材料(如第一間隔物層304)。薄化閘極間隔物302可加寬功能閘極所用的凹陷。較寬的凹陷可改善閘極材料的品質與一致性。較寬凹陷亦可形成較寬的功能閘極,其可增加對通道區的控制、降低閘極電阻、並減少對準問題。在此方式或其他方式中,薄化的閘極間隔物302可提供更可靠的電路裝置。蝕刻可移除任何合適厚度。在多種例子中,移除約1nm至約2nm的第一間隔物層304,以保留約1nm至約10nm寬的閘極間隔物302。
用於移除占位閘極218的蝕刻技術亦可非預期地蝕刻一些層間介電層702,如圖9所示。
如圖1A的步驟116與圖10所示,移除占位閘極218所露出的輸入/輸出氧化物層214的部份被移除。移除輸入/輸出氧化物層214的方法,可採用任何合適的蝕刻技術如乾蝕刻、濕蝕刻、反應性離子蝕刻、及/或其他合適技術。移除輸入/輸出氧化物層214可露出位於鰭狀物210頂部上的鰭狀物頂部的硬遮罩212,亦可露出鰭狀物210的側表面。
如圖1A的步驟118與圖11及12所示,形成功能閘極1102於移除占位閘極218所留下的凹陷中。功能閘極1102可包含介電材料與導電材料的多層。為清楚說明,中間階段的圖式中的閘極1106為單一結構,但其可包含不同材料的多層。形成閘極1106的例示性層狀物將顯示於最終結構中。
在一些例子中,形成功能閘極1102於凹陷中的步驟,先形成界面層於鰭狀物210的側表面上。界面層可包含界面材料如半導體氧化物、半導體氮化物、半導體氮氧化物、其他半導體介電層、其他合適的介電材料、及/或上述之組合。界面層可具有任何合適厚度,且其形成方法可採用任何合適製程如熱成長、原子層沉積、化學氣相沉積、高密度電漿化學氣相沉積、物理氣相沉積、旋轉塗佈沉積、及/或其他合適的沉積製程。在一些例子中,界面層的形成方法為熱氧化製程,且可包含鰭狀物210中存在的半導體之熱氧化物(比如含矽鰭狀物210所形成的氧化矽、含矽鍺鰭狀物210所形成的氧化矽鍺、或類似物)。
閘極介電層1104形成於鰭狀物210的側表面上的界面層上,並形成於鰭狀物210之頂部上的鰭狀物頂部的硬遮罩212上。閘極介電層1104可包含一或多種介電材料,一般以相對於氧化矽的介電常數來分類。在一些實施例中,閘極介電層1104包含高介電常數的介電材料,比如氧化鉿、氧化鉿矽、氮氧化鉿矽、氧化鉿鉭、氧化鉿鈦、氧化鉿鋯、氧化鋯、氧化鋁、氧化鉿-氧化鋁合金、其他合適的高介電常數的介電材料、及/或上述之組合。在額外實施例或其他實施例中,閘極介電層1104可包含其他介電材料,比如半導體氧化物、半導體氮化物、半導體氮氧化物、半導體碳化物、非晶碳、四乙氧矽烷的氧化物、其他合適的介電材料、及/或上述之組合。閘極介電層1104的形成方法可採用任何合適製程,包含原子層沉積、電漿輔助原子層沉積、化學氣相沉積、電漿輔助化學氣相沉積、高密度電漿化學氣相沉積、物理氣相沉積、旋轉塗佈沉積、及/或其他合適沉積製程。閘極介電層1104可具有任何合適厚度。在一些例子中,閘極介電層1104的厚度介於約1nm至約3nm之間。
閘極1106形成於鰭狀物210之上與之間的閘極介電層1104上。閘極1106可包含數個不同導電層如蓋層、功函數層、與閘極填充層。舉例來說,形成閘極的方法可包括形成一或多個蓋層於閘極介電層1104上,以避免其他閘極材料遷移至閘極介電層1104中。蓋層可包含任何合適的導電材料,包括金屬(如鎢、鋁、鉭、鈦、鎳、銅、鈷、或類似物)、金屬氮化物、及/或金屬矽氮化物,且其沉積方法可為化學氣相沉積、原子層沉積、電漿輔助化學氣相沉積、電漿輔助原子層沉積、物理氣相沉積、及/或其他合適沉積製程。在多種實施例中,蓋層包括氮化鉭矽、氮化鉭、及/或氮化鈦。
在一些例子中,形成閘極1106的方法包括形成一或多個功函數層於蓋層上。合適的功函數層材料包括n型及/或p型的功函數材料,端視形成的電路裝置型態而定。例示性的p型功函數金屬包括氮化鈦、氮化鉭、釕、鉬、鋁、氮化鎢、鋯矽化物、鉬矽化物、鉭矽化物、鎳矽化物、其他合適的p型功函數材料、及/或上述之組合。例示性的n型功函數金屬包括鈦、銀、鉭鋁、碳化鉭鋁、氮化鈦鋁、碳化鉭、碳氮化鉭、氮化鉭矽、錳、鋯、其他合適的n型功函數材料、及/或上述之組合。功函數層的沉積方法可為任何合適技術,包括原子層沉積、電漿輔助原子層沉積、化學氣相沉積、電漿輔助化學氣相沉積、物理氣相沉積、及/或上述之組合。由於p型通道與n型通道的裝置可具有不同功函數層,一些例子中在沉積p型功函數層的第一沉積製程中,可採用介電硬遮罩以避免沉積於n型通道裝置的電極上。在沉積n型功函數層的第二沉積製程中,可採用介電硬遮罩層以避免沉積於p型通道裝置的電極上。
在一些實施例中,形成閘極1106的方法包括形成閘極填充層於功函數層上。閘極填充層可包含任何合適材料如金屬(例如鎢、鋁、鉭、鈦、鎳、銅、鈷、或類似物)、金屬氧化物、金屬氮化物、及/或上述之組合。在一例中,閘極填充層包括鎢。電極填充層的沉積方法可為任何合適技術,包括原子層沉積、電漿輔助原子層沉積、化學氣相沉積、電漿輔助化學氣相沉積、物理氣相沉積、及/或上述之組合。
功能閘極1102的形成方法亦可包含形成導電蓋層1108於閘極1106上。導電蓋層1108可包含任何合適的導電材料,包括金屬(如鎢、鋁、鉭、鈦、鎳、銅、鈷、或類似物)、金屬氧化物、金屬氮化物、及/或上述之組合。導電蓋層1108的材料的沉積方法可為任何合適技術,包括原子層沉積、電漿輔助原子層沉積、化學氣相沉積、電漿輔助化學氣相沉積、物理氣相沉積、及/或上述之組合。在一些例子中,導電蓋層1108包括無氟的原子層沉積製程所形成的鎢。
如圖1A的步驟120與圖13及14所示,在沉積材料以形成功能閘極1102之後,在工件200上進行化學機械研磨製程。化學機械研磨製程可自鰭狀物210上移除一些或所有的導電蓋層1108。
如圖1B的步驟122與圖15及16所示,回蝕刻功能閘極1102的材料以自鰭狀物210的頂部移除功能閘極1102,並保留沿著鰭狀物210的側部的功能閘極1102之材料。此步驟可包含進行一或多道蝕刻製程(如乾蝕刻、濕蝕刻、反應性離子蝕刻、或類似製程),其設置為蝕刻閘極介電層1104與閘極1106,而不明顯地蝕刻周圍材料(如閘極間隔物302、鰭狀物頂部的硬遮罩212、與層間介電層702)。具體而言,步驟122的製程可設置以在露出鰭狀物頂部的硬遮罩212時停止蝕刻。在此方式中,沿著圖16中的鰭狀物210的閘極介電層1104與閘極1106之最頂部表面,可與圖15中的鰭狀物頂部的硬遮罩212的最頂部表面實質上共平面。
如圖1B的步驟124與圖15及16所示,回蝕刻閘極間隔物302 (如第一間隔物層304與第二間隔物層306)的最上側部份,可產生額外空間以用於耦接至功能閘極1102的閘極接點。這可包含回蝕刻底接點蝕刻停止層602,使底接點蝕刻停止層的頂部與閘極間隔物302的頂部維持實質上共平面。回蝕刻閘極間隔物302的方法可包括一或多道蝕刻製程(比如乾蝕刻、濕蝕刻、反應性離子蝕刻、或類似製程),其設置為蝕刻第一間隔物層304與第二間隔物層306及/或底接點蝕刻停止層602,而不明顯蝕刻周圍材料。蝕刻設置為停止時,可保留閘極間隔物302的一些部份於鰭狀物210及功能閘極1102上。在層間介電層702延伸高於鰭狀物210的高度1502為約100nm的多種例子中,保留的閘極間隔物302的高度1504可介於約25nm至約75nm之間。不含閘極間隔物302的層間介電層702之高度1506介於約25nm至約75nm之間。在多種例子中,在鰭狀物210上的閘極間隔物302的高度1504,為鰭狀物210上的層間介電層702的高度1502之約30%至約60%之間。
藉由回蝕刻閘極間隔物302,可產生閘極接點所用的額外空間。在一些例子中,閘極間隔物302之間的凹陷之寬度1508介於約10nm至約15nm之間,而高於閘極間隔物302的 凹陷之寬度1510介於約15nm至約25nm之間。由於凹陷的深寬比影響接點材料沉積的一致性,減少閘極間隔物302之間的較窄凹陷高度,可改善最終接點的品質與一致性。
如圖1B的步驟126與圖17及18所示,可形成額外的閘極間隔物層(如第三間隔物層1702)於現存的閘極間隔物302之側表面上。第三間隔物層1702亦可形成於閘極間隔物302、底接點蝕刻停止層602、鰭狀物頂部的硬遮罩212、閘極介電層1104、與閘極1106的上表面上,以及層間介電層702的側表面上。第三間隔物層1702的形成方法可採用任何合適的沉積技術如原子層沉積、化學氣相沉積、高密度電漿化學氣相沉積、或類似方法。第三間隔物層1702可具有任何合適厚度。在這些例子中,第三間隔物層1702的厚度介於約1nm至約5nm之間。在形成閘極之後形成第三間隔物層1702於功能閘極1102上,沿著功能閘極1102之側部的閘極間隔物302可比功能閘極1102上的閘極間隔物302薄,這可改善形成功能閘極1102的層狀物於閘極間隔物302之間的能力。
第三間隔物層1702可包含一或多層的合適材料,比如介電材料(如半導體氧化物、半導體氮化物、半導體氮氧化物、半導體碳化物、半導體碳氮氧化物、或類似物)。在這些例子中,第三間隔物層1702包括低介電常數的介電材料(如碳氮化矽、探氧化矽、碳氮氧化矽、或類似物),其可與第一間隔物層304與第二間隔物層306的材料相同或不同。
如圖1B的步驟128與圖19及20所示,在第三間隔物層1702上進行穿透蝕刻,以至少露出閘極1106的頂部。在一些例子中,穿透蝕刻設置以自水平表面(如閘極間隔物302、底接點蝕刻停止層602、鰭狀物頂部的硬遮罩212、閘極介電層1104、及/或閘極1106的上表面)移除第三間隔物層1702,並保留第三間隔物層1702於閘極間隔物302及/或層間介電層702的垂直表面上。蝕刻可採用任何合適技術,包括非等向的乾蝕刻、濕蝕刻、及/或反應性離子蝕刻,其可設置為自水平表面移除第三間隔物層1702,而不明顯地蝕刻周圍材料。
如圖1B的步驟130與圖21及22所示,形成第二導電蓋層2102於閘極1106及鰭狀物頂部的硬遮罩212上。第二導電蓋層2102延伸於鰭狀物210與鰭狀物頂部的硬遮罩212上,以耦接鰭狀物210之兩側上的閘極1106。具體而言,第二導電蓋層2102延伸於閘極間隔物302之間,並物理接觸閘極間隔物302的第三間隔物層1702。第二導電蓋層2102可包含任何合適的導電材料,包括金屬(如鎢、鋁、鉭、鈦、鎳、銅、鈷、或類似物)、金屬氧化物、金屬氮化物、及/或上述之組合。在一例中,第二導電蓋層2102包括鎢。第二導電蓋層2102的沉積方法可為任何合適技術,包括原子層沉積、電漿輔助原子層沉積、化學氣相沉積、電漿輔助化學氣相沉積、物理氣相沉積、及/或上述之組合。在一些例子中,第二導電蓋層2102包括無氟的原子層沉積製程所形成的鎢。第二導電蓋層2102可具有任何合適厚度。在一些例子中,第二導電蓋層2102的厚度介於約2nm至約10nm之間。
在形成第三間隔物層1702於層間介電層702之側表面上的實施例中,可自這些表面移除第三間隔物層1702,如步驟132至138所示。如圖1B的步驟132與圖21及22所示,形成犧牲材料2104於第三間隔物層1702所定義的凹陷中的第二導電蓋層2102上。犧牲材料2104可包含任何合適材料如介電層、非晶矽、及/或其他合適材料,其材料選擇為與第三間隔物層1702及第二導電蓋層2102具有不同的蝕刻選擇性。
如圖1B的步驟134與圖23及24所示,回蝕刻犧牲材料2104以露出層間介電層702的側表面上的第三間隔物層1702。可控制蝕刻以保護閘極間隔物302之側表面上的第三間隔物層1702的部份。綜上所述,蝕刻之後的犧牲材料2104的上表面、閘極間隔物302的上表面、與底接點蝕刻停止層602的上表面可實質上共平面。蝕刻製程可採用任何合適的蝕刻技術,包含濕蝕刻、乾蝕刻、及/或反應性離子蝕刻。
如圖1B的步驟136與圖25及26所示,移除層間介電層702的側表面上的第三間隔物層1702的露出部份。第三間隔物層1702的移除方法可採用任何合適的蝕刻技術,包括濕蝕刻、乾蝕刻、及/或反應性離子蝕刻。可選擇特定蝕刻技術與蝕刻劑,以避免明顯蝕刻周圍材料如層間介電層702、閘極間隔物302、及/或底接點蝕刻停止層602。
如圖1B的步驟138與圖25及26所示,可移除殘留的犧牲材料2104。此步驟實質上如步驟134。
如圖1B的步驟140與圖27及28所示,形成自對準接點介電層2702於功能閘極1102上及鰭狀物210上的第二導電蓋層2102上。自對準接點介電層2702可包含任何合適材料如一或多種介電材料,包含半導體氧化物、半導體氮化物、半導體氮氧化物、半導體碳化物、半導體碳氮化物、半導體碳氮氧化物、及/或金屬氧化物。在多種實施例中,自對準接點介電層2702包括氧化鉿、氧化鋯、氧化鋁、氧化鑭、氮化硼、在多種例子中,自對準接點介電層2702包括氧化鉿、氧化鋯、氧化鋁、氧化鑭、氮化硼、氧化矽、氮化矽、碳氮化矽、氮氧化矽、及/或碳氮氧化矽。
自對準接點介電層2702的形成方法可為任何合適製程。在一些例子中,自對準接點介電層2702的沉積方法採用化學氣相沉積、電漿輔助化學氣相沉積、高密度電漿化學氣相沉積、物理氣相沉積、原子層沉積、電漿輔助原子層沉積、及/或其他沉積製程。在沉積之後可進行化學機械研磨以移除閘極區之外的材料,且化學機械研磨製程之後的閘極區中平坦化的自對準接點層2702可具有任何合適厚度。在多種例子中,自對準接點介電層2702的厚度介於約50nm至約150nm之間。
如圖1B的步驟142與圖29至31所示,接著提供工件200以進行後續製作。在多種例子中,此步驟可包括形成接點2902以電性耦接至源極/汲極結構402與功能閘極1102、形成底接點蝕刻停止層2904於層間介電層702與接點2902上、形成電性內連線結構的其餘部份、切割、封裝、與其他製作製程。
本發明一些例子薄化第一間隔物層304與第二間隔物層306,並形成第三間隔物層1702於功能閘極1102的頂部上而非功能閘極1102的側壁上,可提供較寬的凹陷以形成功能閘極1102於其中。一般而言,較寬的功能閘極1102對穿過通道區的載子控制較佳,並減少或避免不利的短通道效應如汲極誘發的能障降低、擊穿、速率飽和、與熱載子劣化。較寬的功能閘極1102亦可減少接點對準問題。綜上所述,此技術可達這些優點與其他優點,且不腐蝕接點2902而損害接點形成。此外,自鰭狀物210的頂部移除功能閘極1102可降低閘極電容,進而改善電晶體的切換速度與交流電回應。
圖30與31顯示閘極1106的材料層細節,包括蓋層3002、功函數層3004、與閘極填充層3006,其各自如上所述。
圖31顯示工件200的兩個區域。在第一區域3102中,功能閘極1102沿著鰭狀物210與鰭狀物頂部的硬遮罩212的側部延伸至鰭狀物頂部的硬遮罩212的上表面。然而製程條件如蝕刻速率會使第二區域3104中的功能閘極1102沿著鰭狀物210的側部延伸,但止於鰭狀物頂部的硬遮罩212之底部或其附近處。相反地,第三間隔物層1702覆蓋鰭狀物頂部的硬遮罩212之側表面。這些設置同樣合適。
圖32至34係方法100所形成的另一工件3200的剖視圖。圖32係本發明多種實施例中,工件3200沿著切穿鰭狀物的鰭狀物長度方向的剖視圖。圖33係本發明多種實施例中,工件3200沿著切穿隔離結構的鰭狀物長度方向的剖視圖。圖34係本發明多種實施例中,工件3200沿著切穿閘極結構的閘極長度方向之剖視圖。
工件3200與工件200實質上類似,差別在於省略步驟132至138中,自層間介電層702的側表面移除第三間隔物層1702的步驟。綜上所述,第三間隔物層1702位於層間介電層702與自對準接點介電層2702之間,及/或位於層間介電層702與接點2902之間,端視特定位置的自對準接點介電層2702是否取代為接點2902。
採用另一技術已形成底接點蝕刻停止層的其他例子,將搭配圖35至50說明。圖35係本發明多種實施例中,採用選擇性沉積製作工件3600的方法3500之流程圖。在方法3500之前、之中、或之後可提供額外步驟,且方法3500的其他實施例可置換或省略一些所述步驟。圖36至38、40、42、44、與46係本發明多種實施例中,工件3600沿著切穿鰭狀物的鰭狀物長度方向的剖視圖。圖39、41、43、45、47、與49係本發明多種實施例中,工件3600沿著切穿隔離結構的鰭狀物長度方向的剖視圖。圖50係本發明多種實施例中,工件3600沿著切穿閘極結構的閘極長度方向的剖視圖。
如圖35的步驟3502與圖35及36所示,進行與圖1A的步驟102至108類似的上述製程。綜上所述,可接收與工件200類似的工件3600。工件3600包含基板208、自基板延伸的鰭狀物210、位於鰭狀物210上的鰭狀物頂部的硬遮罩212、位於鰭狀物210與鰭狀物頂部的硬遮罩212上的輸入/輸出氧化物層214、位於鰭狀物上的占位閘極218、以及位於占位閘極218上的閘極硬遮罩層220與222。閘極間隔物302 (如第一間隔物層304與第二間隔物層306)形成於占位閘極218的側表面上。源極/汲極結構402形成於占位閘極218的兩側上。進行蝕刻製程以薄化閘極間隔物302的最外層(如第二間隔物層306)。
如圖35的步驟3504與圖37所示,選擇性地形成底接點蝕刻停止層3702於源極/汲極結構402上。數種合適技術可用於避免形成底接點蝕刻停止層3702於閘極間隔物302的側表面上。在這些例子中,可對工件3600進行預處理以自源極/汲極結構402移除原生氧化物。預處理可包含施加化學溶液(如氫氟酸、氯化氫、及/或其他溶液)至工件3600、施加真空如超高真空(比如近似10-8
Torr的級數或更低)、及/或其他合適的清潔技術。
可選擇性地形成抑制劑於欲排除底接點蝕刻停止層3702的表面上。舉例來說,可沉積抑制劑於閘極間隔物302 (如第二間隔物層306)的側表面上。抑制劑可設置以避免後續形成的底接點蝕刻停止層3702黏著,且可包含介電層、聚合物、及/或其他合適材料。
在施加抑制劑之後,形成底接點蝕刻停止層3702於源極/汲極結構402上。底接點蝕刻停止層3702的沉積方法可為任何合適技術,包括原子層沉積、電漿輔助原子層沉積、化學氣相沉積、電漿輔助化學氣相沉積、及/或高密度電漿化學氣相沉積,而抑制劑可避免底接點蝕刻停止層3702形成於抑制劑存在的表面上。
底接點蝕刻停止層3702可包含介電層(如半導體氧化物、半導體氮化物、半導體氮氧化物、半導體碳化物、或類似物)及/或其他合適材料。在多種實施例中,底接點蝕刻停止層3702包括氮化矽、氧化矽、氮氧化矽、及/或碳化矽。底接點蝕刻停止層3702可具有任何合適厚度。在一些例子中,底接點蝕刻停止層3702的厚度介於約1nm至約10nm之間。
在形成底接點蝕刻停止層3702之後,可移除任何殘留的抑制劑。
如圖35的步驟3506與圖38及39所示,在工件3600上進行圖1A至1B的步驟112至124。在一些例子中,形成層間介電層702於工件3600上,並移除殘留的占位閘極218。移除占位閘極218所露出的輸入/輸出氧化物層214的一部份亦被移除。形成功能閘極1102於凹陷中的方法,可為移除占位閘極218,並在工件3600上進行化學機械研磨製程。回蝕刻功能閘極1102的材料,以自鰭狀物210的頂部移除功能閘極1102,並留下沿著鰭狀物210之側部的功能閘極1102的材料。回蝕刻閘極間隔物302 (如第一間隔物層304與第二間隔物層306)的最上側部份,可產生額外的空間以用於耦接至功能閘極1102的閘極接點。
如圖35的步驟3508與圖40及41所示,形成額外的閘極間隔物層(如第三間隔物層4002)於現存的閘極間隔物302的側表面上。第三間隔物層4002亦可形成於功能閘極1102的上表面上。在一些例子中,選擇性沉積技術用於避免形成第三間隔物層4002於某處,比如避免形成於層間介電層702的側表面上。
這可包含選擇性形成抑制劑於欲排除第三間隔物層4002處的表面上。舉例來說,抑制劑可沉積於層間介電層702的側表面上。抑制劑可設置以避免後續形成的第三間隔物層4002黏著,且可包含介電層、聚合物、及/或其他合適材料。
在施加抑制劑之後,形成第三間隔物層4002於源極/汲極結構402上。第三間隔物層4002的沉積方法可為任何合適技術,包括原子層沉積、電漿輔助原子層沉積、化學氣相沉積、電漿輔助化學氣相沉積、及/或高密度電漿化學氣相沉積,而抑制劑可避免第三間隔物層4002沉積於抑制劑存在的表面上。
第三間隔物層4002可包含一或多層的合適材料如介電材料(例如半導體氧化物、半導體氮化物、半導體氮氧化物、半導體碳化物、半導體碳氮氧化物、或類似物)。在一些例子中,第三間隔物層4002包括低介電常數的介電材料(比如碳氮化矽、碳氧化矽、碳氮氧化矽、或類似物),其可與第一間隔物層304與第二間隔物層306的材料相同或不同。第三間隔物層4002可具有任何合適厚度。在這些例子中,第三間隔物層4002的厚度介於約1nm至約5nm之間。
在形成第三間隔物層4002之後,可移除任何殘留的抑制劑。
如圖35的步驟3510與圖43及44所示,在第三間隔物層4002上進行穿透蝕刻,以至少露出閘極1106的頂部。此步驟可與圖1B的步驟128實質上類似。
如圖35的步驟3512與圖44及45所示,形成第二導電蓋層2102於閘極1106及鰭狀物頂部的硬遮罩212上。此步驟可與圖1B的步驟130實質上類似。
如圖35的步驟3514與圖46及47所示,形成自對準接點介電層2702於功能閘極1102上與鰭狀物210上的第二導電蓋層2102上。此步驟可與圖1B的步驟140實質上類似。
如圖35的步驟3516與圖48至50所示,可提供工件3600以進行後續製作。在多種實施例中,這包含形成接點2902以耦接至源極/汲極結構402與功能閘極1102、形成底接點蝕刻停止層2904於層間介電層702與接點2902上、形成電性內連線結構的其餘部份、切割、封裝、與其他製作製程。藉由不形成底接點蝕刻停止層3702於閘極間隔物302的側表面上,方法3500可形成更寬的接點2902,且接點2902與功能閘極1102之間的分隔更短。所有的其他尺寸與方法100的例子類似。
因此本發明實施例提供具有鰭狀場效電晶體閘極的積體電路與形成積體電路的方法。在一些實施例中,積體電路裝置包括:基板;鰭狀物,自基板延伸;第一閘極,位於鰭狀物的第一側上;以及閘極間隔物,沿著第一閘極的側部。閘極間隔物具有沿著第一閘極延伸且具有第一寬度的第一部份,以及延伸於第一閘極上且具有第二寬度的第二部份,而第二寬度大於第一寬度。在一些實施例中,閘極間隔物的第二部份包括位於第一閘極上的閘極間隔物層。在這些實施例中,閘極間隔物層物理接觸第一閘極的閘極介電層,並物理接觸另一閘極間隔物層的側表面。在這些實施例中,積體電路裝置更包括第二閘極,位於鰭狀物的第二側上;以及導電蓋層,位於鰭狀物、第一閘極、與第二閘極上,以電性耦接第一閘極與第二閘極。在這些實施例中,閘極間隔物的第二部份包括物理接觸導電蓋的側表面與第一閘極的上表面之閘極間隔物層。在這些實施例中,積體電路裝置更包括硬遮罩位於鰭狀物與導電蓋之間的鰭狀物上。在這些實施例中,第一閘極的上表面與硬遮罩的上表面實質上共平面。在這些實施例中,積體電路裝置更包括層間介電層於鰭狀物上。層間介電層延伸高於閘極間隔物的上表面。在這些實施例中,積體電路裝置更包括接點蝕刻停止層位於沿著閘極間隔物側部的鰭狀物上。接點蝕刻停止層的上表面與閘極間隔物的上表面實質上共平面。在這些實施例中,閘極間隔物更具有位於鰭狀物上並具有第三寬度的第三部份,以及位於第三部份上並具有第四寬度的第四部份,且第四寬度小於第三寬度。
在另一實施例中,積體電路裝置包括:基板,具有鰭狀物;隔離介電層,位於基板上,使鰭狀物延伸高於隔離介電層;一對閘極結構,位於鰭狀物的兩側上的隔離介電層上;閘極間隔物,位於一對閘極結構之側表面上與鰭狀物上;以及層間介電層,位於隔離介電層上與鰭狀物上。層間介電層延伸於閘極間隔物上並沿著閘極間隔物的側部。在這些實施例中,與一對閘極結構相鄰的閘極間隔物具有第一厚度,而高於一對閘極結構與鰭狀物的閘極間隔物具有第二厚度,且第二厚度大於第一厚度。在這些實施例中,層間介電層物理接觸閘極間隔物。在這些實施例中,積體電路裝置更包括接點以電性耦接至一對閘極結構,其中層間介電層物理接觸接點。在這些實施例中,積體電路裝置更包括導電蓋於鰭狀物及一對閘極結構上以電性耦接一對閘極結構。導電蓋位於鰭狀物與接點之間。
在又一實施例中,積體電路裝置的製作方法包括:接收基板,其具有自基板延伸的鰭狀物,以及位於鰭狀物上及鰭狀物的兩側上的占位閘極。形成閘極間隔物於占位閘極的側表面上,並進行閘極置換製程,以將占位閘極置換成功能閘極。形成額外閘極間隔物層於閘極間隔物的側表面上與功能閘極的上表面上。在這些實施例中,在形成額外閘極間隔物層之前,使功能閘極凹陷以自鰭狀物的上表面移除功能閘極。在這些實施例中,形成導電蓋於鰭狀物上,以電性耦接功能閘極位於鰭狀物之第一側上的第一部份至功能閘極位於鰭狀物之第二側上的第二部份。在這些實施例中,額外閘極間隔物層沿著導電蓋的側表面延伸。在這些實施例中,形成層間介電層於基板上;以及自層間介電層的側表面移除額外閘極間隔物層。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明實施例。本技術領域中具有通常知識者應理解可採用本發明實施例作基礎,設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解,這些等效置換並未脫離本發明精神與範疇,並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
100、3500:方法
102、104、106、108、110、112、114、116、118、120、122、124、126、128、130、132、134、136、138、140、142、3502、3504、3506、3508、3510、3512、3514、3516:步驟
200、3200、3600:工件
202、204:平面
208:基板
210:鰭狀物
212:鰭狀物頂部的硬遮罩
214:輸入/輸出氧化物層
216:隔離介電層
218:占位閘極
220、222:閘極硬遮罩層
223:距離
302:閘極間隔物
304:第一間隔物層
306:第二間隔物層
402:源極/汲極結構
502:厚度
602、2904:底接點蝕刻停止層
702:層間介電層
1102:功能閘極
1104:閘極介電層
1106:閘極
1108:導電蓋層
1502、1504、1506:高度
1508、1510:寬度
1702、4002:第三間隔物層
2102:第二導電蓋層
2104:犧牲材料
2702:自對準接點介電層
2902:接點
3002:蓋層
3004:功函數層
3006:閘極填充層
3102:第一區域
3104:第二區域
3702:底接點蝕刻停止層
圖1A與1B係本發明多種實施例中,製作具有鰭狀場效電晶體的閘極結構之工件的方法之流程圖。
圖2係本發明多種實施例中,以方法製作的工件透視圖。
圖3至11、13、15、17、19、21、23、25、27、與29係本發明多種實施例中,工件沿著切穿鰭狀物的鰭狀物長度方向的剖視圖。
圖12、14、16、18、20、22、24、26、28、與30係本發明多種實施例中,工件沿著切穿隔離結構的鰭狀物長度方向的剖視圖。
圖31係本發明多種實施例中,工件沿著切穿閘極結構的閘極長度方向之剖視圖。
圖32係本發明多種實施例中,工件沿著切穿鰭狀物的鰭狀物長度方向之剖視圖。
圖33係本發明多種實施例中,工件沿著切穿隔離結構的鰭狀物長度方向的剖視圖。
圖34係本發明多種實施例中,工件沿著切穿閘極結構的閘極長度方向的剖視圖。
圖35係本發明多種實施例中,採用選擇性沉積製作工件的方法之流程圖。
圖36至38、40、42、44、46、與48係本發明多種實施例中,工件沿著切穿鰭狀物的鰭狀物長度方向的剖視圖。
圖39、41、43、45、47、與49係本發明多種實施例中,工件沿著切穿隔離結構的鰭狀物長度方向的剖視圖。
圖50係本發明多種實施例中,工件沿著切穿閘極結構的閘極長度方向的剖視圖。
200:工件
208:基板
210:鰭狀物
212:鰭狀物頂部的硬遮罩
214:輸入/輸出氧化物層
218:占位閘極
220、222:閘極硬遮罩層
302:閘極間隔物
304:第一間隔物層
306:第二間隔物層
402:源極/汲極結構
502:厚度
Claims (1)
- 一種積體電路裝置,包括: 一基板; 一鰭狀物,自該基板延伸; 一第一閘極,位於該鰭狀物的第一側上;以及 一閘極間隔物,沿著該第一閘極的側部,其中該閘極間隔物具有沿著該第一閘極延伸且具有一第一寬度的一第一部份,以及延伸於該第一閘極上且具有一第二寬度的一第二部份,而該第二寬度大於該第一寬度。
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US16/360,502 US11380682B2 (en) | 2018-10-23 | 2019-03-21 | Integrated circuits with FinFET gate structures |
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